src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 #include <llvm-c/Target.h>
  34 #include <llvm-c/TargetMachine.h>
  35
  36 /*
  37  * pipe_context
  38  */
  39 static void si_destroy_context(struct pipe_context *context)
  40 {
  41         struct si_context *sctx = (struct si_context *)context;
  42
  43         si_release_all_descriptors(sctx);
  44
  45         pipe_resource_reference(&sctx->esgs_ring, NULL);
  46         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  47         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  48         r600_resource_reference(&sctx->border_color_table, NULL);
  49         r600_resource_reference(&sctx->scratch_buffer, NULL);
  50
  51         si_pm4_free_state(sctx, sctx->init_config, ~0);
  52         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  53         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  54         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  55
  56         if (sctx->pstipple_sampler_state)
  57                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  58         if (sctx->dummy_pixel_shader) {
  59                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  60         }
  61         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  62         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  63         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  64         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  65         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  66
  67         util_blitter_destroy(sctx->blitter);
  68
  69         si_pm4_cleanup(sctx);
  70
  71         r600_common_context_cleanup(&sctx->b);
  72         FREE(sctx);
  73 }
  74
  75 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  76 {
  77         struct si_context *sctx = CALLOC_STRUCT(si_context);
  78         struct si_screen* sscreen = (struct si_screen *)screen;
  79         struct radeon_winsys *ws = sscreen->b.ws;
  80         int shader, i;
  81
  82         if (sctx == NULL)
  83                 return NULL;
  84
  85         sctx->b.b.screen = screen; /* this must be set first */
  86         sctx->b.b.priv = priv;
  87         sctx->b.b.destroy = si_destroy_context;
  88         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
  89
  90         if (!r600_common_context_init(&sctx->b, &sscreen->b))
  91                 goto fail;
  92
  93         si_init_blit_functions(sctx);
  94         si_init_compute_functions(sctx);
  95
  96         if (sscreen->b.info.has_uvd) {
  97                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
  98                 sctx->b.b.create_video_buffer = si_video_buffer_create;
  99         } else {
 100                 sctx->b.b.create_video_codec = vl_create_decoder;
 101                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 102         }
 103
 104         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
 105                                              sctx, sscreen->b.trace_bo ?
 106                                                 sscreen->b.trace_bo->cs_buf : NULL);
 107         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 108
 109         si_init_all_descriptors(sctx);
 110
 111         /* Initialize cache_flush. */
 112         sctx->cache_flush = si_atom_cache_flush;
 113         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 114
 115         sctx->msaa_config = si_atom_msaa_config;
 116         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 117
 118         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 119         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 120
 121         switch (sctx->b.chip_class) {
 122         case SI:
 123         case CIK:
 124                 si_init_state_functions(sctx);
 125                 si_init_shader_functions(sctx);
 126                 si_init_config(sctx);
 127                 break;
 128         default:
 129                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 130                 goto fail;
 131         }
 132
 133         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 134                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 135
 136         sctx->blitter = util_blitter_create(&sctx->b.b);
 137         if (sctx->blitter == NULL)
 138                 goto fail;
 139         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 140
 141         /* these must be last */
 142         si_begin_new_cs(sctx);
 143         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 144
 145         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 146          * with a NULL buffer). We need to use a dummy buffer instead. */
 147         if (sctx->b.chip_class == CIK) {
 148                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 149                                                                  PIPE_USAGE_DEFAULT, 16);
 150                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 151
 152                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 153                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 154                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 155                                                               &sctx->null_const_buf);
 156                         }
 157                 }
 158
 159                 /* Clear the NULL constant buffer, because loads should return zeros. */
 160                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 161                                      sctx->null_const_buf.buffer->width0, 0, false);
 162         }
 163
 164         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 165          * this for non-cs shaders.  Using the wrong value here can result in
 166          * GPU lockups, but the maximum value seems to always work.
 167          */
 168         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 169
 170         return &sctx->b.b;
 171 fail:
 172         si_destroy_context(&sctx->b.b);
 173         return NULL;
 174 }
 175
 176 /*
 177  * pipe_screen
 178  */
 179
 180 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 181 {
 182         struct si_screen *sscreen = (struct si_screen *)pscreen;
 183
 184         switch (param) {
 185         /* Supported features (boolean caps). */
 186         case PIPE_CAP_TWO_SIDED_STENCIL:
 187         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 188         case PIPE_CAP_ANISOTROPIC_FILTER:
 189         case PIPE_CAP_POINT_SPRITE:
 190         case PIPE_CAP_OCCLUSION_QUERY:
 191         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 192         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 193         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 194         case PIPE_CAP_TEXTURE_SWIZZLE:
 195         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 196         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 197         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 198         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 199         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 200         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 201         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 202         case PIPE_CAP_SM3:
 203         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 204         case PIPE_CAP_PRIMITIVE_RESTART:
 205         case PIPE_CAP_CONDITIONAL_RENDER:
 206         case PIPE_CAP_TEXTURE_BARRIER:
 207         case PIPE_CAP_INDEP_BLEND_ENABLE:
 208         case PIPE_CAP_INDEP_BLEND_FUNC:
 209         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 210         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 211         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 212         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 213         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 214         case PIPE_CAP_USER_INDEX_BUFFERS:
 215         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 216         case PIPE_CAP_START_INSTANCE:
 217         case PIPE_CAP_NPOT_TEXTURES:
 218         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 219         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 220         case PIPE_CAP_TGSI_INSTANCEID:
 221         case PIPE_CAP_COMPUTE:
 222         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 223         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 224         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 225         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 226         case PIPE_CAP_CUBE_MAP_ARRAY:
 227         case PIPE_CAP_SAMPLE_SHADING:
 228         case PIPE_CAP_DRAW_INDIRECT:
 229         case PIPE_CAP_CLIP_HALFZ:
 230         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 231         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 232         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 233                 return 1;
 234
 235         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 236                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 237
 238         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 239                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 240                 return sscreen->b.chip_class < CIK ||
 241                        sscreen->b.info.drm_minor >= 35;
 242
 243         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 244                 return R600_MAP_BUFFER_ALIGNMENT;
 245
 246         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 247         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 248                 return 4;
 249
 250         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 251                 return 330;
 252
 253         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 254                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 255
 256         case PIPE_CAP_TEXTURE_QUERY_LOD:
 257         case PIPE_CAP_TEXTURE_GATHER_SM5:
 258                 return HAVE_LLVM >= 0x0305;
 259         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 260                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 261
 262         /* Unsupported features. */
 263         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 264         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 265         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 266         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 267         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 268         case PIPE_CAP_USER_VERTEX_BUFFERS:
 269         case PIPE_CAP_TGSI_TEXCOORD:
 270         case PIPE_CAP_FAKE_SW_MSAA:
 271         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 272         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 273         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 274         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 275         case PIPE_CAP_VERTEXID_NOBASE:
 276                 return 0;
 277
 278         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 279                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 280
 281         /* Stream output. */
 282         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 283                 return sscreen->b.has_streamout ? 4 : 0;
 284         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 285                 return sscreen->b.has_streamout ? 1 : 0;
 286         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 287         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 288                 return sscreen->b.has_streamout ? 32*4 : 0;
 289
 290         /* Geometry shader output. */
 291         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 292                 return 1024;
 293         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 294                 return 4095;
 295         case PIPE_CAP_MAX_VERTEX_STREAMS:
 296                 return 1;
 297
 298         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 299                 return 2048;
 300
 301         /* Texturing. */
 302         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 303         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 304                 return 15; /* 16384 */
 305         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 306                 /* textures support 8192, but layered rendering supports 2048 */
 307                 return 12;
 308         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 309                 /* textures support 8192, but layered rendering supports 2048 */
 310                 return 2048;
 311
 312         /* Render targets. */
 313         case PIPE_CAP_MAX_RENDER_TARGETS:
 314                 return 8;
 315
 316         case PIPE_CAP_MAX_VIEWPORTS:
 317                 return 1;
 318
 319         /* Timer queries, present when the clock frequency is non zero. */
 320         case PIPE_CAP_QUERY_TIMESTAMP:
 321         case PIPE_CAP_QUERY_TIME_ELAPSED:
 322                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 323
 324         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 325         case PIPE_CAP_MIN_TEXEL_OFFSET:
 326                 return -32;
 327
 328         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 329         case PIPE_CAP_MAX_TEXEL_OFFSET:
 330                 return 31;
 331
 332         case PIPE_CAP_ENDIANNESS:
 333                 return PIPE_ENDIAN_LITTLE;
 334
 335         case PIPE_CAP_VENDOR_ID:
 336                 return 0x1002;
 337         case PIPE_CAP_DEVICE_ID:
 338                 return sscreen->b.info.pci_id;
 339         case PIPE_CAP_ACCELERATED:
 340                 return 1;
 341         case PIPE_CAP_VIDEO_MEMORY:
 342                 return sscreen->b.info.vram_size >> 20;
 343         case PIPE_CAP_UMA:
 344                 return 0;
 345         }
 346         return 0;
 347 }
 348
 349 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 350 {
 351         switch(shader)
 352         {
 353         case PIPE_SHADER_FRAGMENT:
 354         case PIPE_SHADER_VERTEX:
 355         case PIPE_SHADER_GEOMETRY:
 356                 break;
 357         case PIPE_SHADER_COMPUTE:
 358                 switch (param) {
 359                 case PIPE_SHADER_CAP_PREFERRED_IR:
 360 #if HAVE_LLVM < 0x0306
 361                         return PIPE_SHADER_IR_LLVM;
 362 #else
 363                         return PIPE_SHADER_IR_NATIVE;
 364 #endif
 365                 case PIPE_SHADER_CAP_DOUBLES:
 366                         return HAVE_LLVM >= 0x0307;
 367
 368                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 369                         uint64_t max_const_buffer_size;
 370                         pscreen->get_compute_param(pscreen,
 371                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 372                                 &max_const_buffer_size);
 373                         return max_const_buffer_size;
 374                 }
 375                 default:
 376                         return 0;
 377                 }
 378         default:
 379                 /* TODO: support tessellation */
 380                 return 0;
 381         }
 382
 383         switch (param) {
 384         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 385         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 386         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 387         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 388                 return 16384;
 389         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 390                 return 32;
 391         case PIPE_SHADER_CAP_MAX_INPUTS:
 392                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 393         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 394                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 395         case PIPE_SHADER_CAP_MAX_TEMPS:
 396                 return 256; /* Max native temporaries. */
 397         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 398                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 399         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 400                 return SI_NUM_USER_CONST_BUFFERS;
 401         case PIPE_SHADER_CAP_MAX_PREDS:
 402                 return 0; /* FIXME */
 403         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 404                 return 1;
 405         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 406                 return 0;
 407         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 408                 /* Indirection of geometry shader input dimension is not
 409                  * handled yet
 410                  */
 411                 return shader < PIPE_SHADER_GEOMETRY;
 412         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 413         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 414         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 415                 return 1;
 416         case PIPE_SHADER_CAP_INTEGERS:
 417                 return 1;
 418         case PIPE_SHADER_CAP_SUBROUTINES:
 419                 return 0;
 420         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 421         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 422                 return 16;
 423         case PIPE_SHADER_CAP_PREFERRED_IR:
 424                 return PIPE_SHADER_IR_TGSI;
 425         case PIPE_SHADER_CAP_DOUBLES:
 426         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 427         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 428                 return 0;
 429         }
 430         return 0;
 431 }
 432
 433 static void si_destroy_screen(struct pipe_screen* pscreen)
 434 {
 435         struct si_screen *sscreen = (struct si_screen *)pscreen;
 436
 437         if (sscreen == NULL)
 438                 return;
 439
 440         if (!sscreen->b.ws->unref(sscreen->b.ws))
 441                 return;
 442
 443 #if HAVE_LLVM >= 0x0306
 444         // r600_destroy_common_screen() frees sscreen, so we need to make
 445         // sure to dispose the TargetMachine before we call it.
 446         LLVMDisposeTargetMachine(sscreen->tm);
 447 #endif
 448
 449         r600_destroy_common_screen(&sscreen->b);
 450 }
 451
 452 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 453
 454 /* Initialize pipe config. This is especially important for GPUs
 455  * with 16 pipes and more where it's initialized incorrectly by
 456  * the TILING_CONFIG ioctl. */
 457 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 458 {
 459         unsigned mode2d;
 460
 461         /* This is okay, because there can be no 2D tiling without
 462          * the tile mode array, so we won't need the pipe config.
 463          * Return "success".
 464          */
 465         if (!sscreen->b.info.si_tile_mode_array_valid)
 466                 return true;
 467
 468         /* The same index is used for the 2D mode on CIK too. */
 469         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 470
 471         switch (G_009910_PIPE_CONFIG(mode2d)) {
 472         case V_02803C_ADDR_SURF_P2:
 473                 sscreen->b.tiling_info.num_channels = 2;
 474                 break;
 475         case V_02803C_X_ADDR_SURF_P4_8X16:
 476         case V_02803C_X_ADDR_SURF_P4_16X16:
 477         case V_02803C_X_ADDR_SURF_P4_16X32:
 478         case V_02803C_X_ADDR_SURF_P4_32X32:
 479                 sscreen->b.tiling_info.num_channels = 4;
 480                 break;
 481         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 482         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 483         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 484         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 485         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 486         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 487         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 488                 sscreen->b.tiling_info.num_channels = 8;
 489                 break;
 490         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 491         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 492                 sscreen->b.tiling_info.num_channels = 16;
 493                 break;
 494         default:
 495                 assert(0);
 496                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 497                         G_009910_PIPE_CONFIG(mode2d));
 498                 return false;
 499         }
 500         return true;
 501 }
 502
 503 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 504 {
 505         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 506         LLVMTargetRef r600_target;
 507 #if HAVE_LLVM >= 0x0306
 508         const char *triple = "amdgcn--";
 509 #else
 510         const char *triple = "r600--";
 511 #endif
 512         if (sscreen == NULL) {
 513                 return NULL;
 514         }
 515
 516         /* Set functions first. */
 517         sscreen->b.b.context_create = si_create_context;
 518         sscreen->b.b.destroy = si_destroy_screen;
 519         sscreen->b.b.get_param = si_get_param;
 520         sscreen->b.b.get_shader_param = si_get_shader_param;
 521         sscreen->b.b.is_format_supported = si_is_format_supported;
 522         sscreen->b.b.resource_create = r600_resource_create_common;
 523
 524         if (!r600_common_screen_init(&sscreen->b, ws) ||
 525             !si_initialize_pipe_config(sscreen)) {
 526                 FREE(sscreen);
 527                 return NULL;
 528         }
 529
 530         sscreen->b.has_cp_dma = true;
 531         sscreen->b.has_streamout = true;
 532
 533         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 534                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 535
 536         /* Create the auxiliary context. This must be done last. */
 537         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 538
 539 #if HAVE_LLVM >= 0x0306
 540         /* Initialize LLVM TargetMachine */
 541         r600_target = radeon_llvm_get_r600_target(triple);
 542         sscreen->tm = LLVMCreateTargetMachine(r600_target, triple,
 543                                 r600_get_llvm_processor_name(sscreen->b.family),
 544                                 "+DumpCode,+vgpr-spilling", LLVMCodeGenLevelDefault, LLVMRelocDefault,
 545                                 LLVMCodeModelDefault);
 546 #endif
 547         return &sscreen->b.b;
 548 }