2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
44 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
45 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
48 #include <llvm/Config/llvm-config.h>
50 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
53 static const struct debug_named_value debug_options
[] = {
54 /* Shader logging options: */
55 { "vs", DBG(VS
), "Print vertex shaders" },
56 { "ps", DBG(PS
), "Print pixel shaders" },
57 { "gs", DBG(GS
), "Print geometry shaders" },
58 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
59 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
60 { "cs", DBG(CS
), "Print compute shaders" },
61 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
62 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
63 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
64 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
66 /* Shader compiler options the shader cache should be aware of: */
67 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
68 { "gisel", DBG(GISEL
), "Enable LLVM global instruction selector." },
69 { "w32ge", DBG(W32_GE
), "Use Wave32 for vertex, tessellation, and geometry shaders." },
70 { "w32ps", DBG(W32_PS
), "Use Wave32 for pixel shaders." },
71 { "w32cs", DBG(W32_CS
), "Use Wave32 for computes shaders." },
72 { "w64ge", DBG(W64_GE
), "Use Wave64 for vertex, tessellation, and geometry shaders." },
73 { "w64ps", DBG(W64_PS
), "Use Wave64 for pixel shaders." },
74 { "w64cs", DBG(W64_CS
), "Use Wave64 for computes shaders." },
76 /* Shader compiler options (with no effect on the shader cache): */
77 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
78 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
79 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
81 /* Information logging options: */
82 { "info", DBG(INFO
), "Print driver information" },
83 { "tex", DBG(TEX
), "Print texture info" },
84 { "compute", DBG(COMPUTE
), "Print compute info" },
85 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
88 { "forcedma", DBG(FORCE_SDMA
), "Use SDMA for all operations when possible." },
89 { "nodma", DBG(NO_SDMA
), "Disable SDMA" },
90 { "nodmaclear", DBG(NO_SDMA_CLEARS
), "Disable SDMA clears" },
91 { "nodmacopyimage", DBG(NO_SDMA_COPY_IMAGE
), "Disable SDMA image copies" },
92 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
93 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
94 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
95 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
97 /* 3D engine options: */
98 { "nogfx", DBG(NO_GFX
), "Disable graphics. Only multimedia compute paths can be used." },
99 { "nongg", DBG(NO_NGG
), "Disable NGG and use the legacy pipeline." },
100 { "alwayspd", DBG(ALWAYS_PD
), "Always enable the primitive discard compute shader." },
101 { "pd", DBG(PD
), "Enable the primitive discard compute shader for large draw calls." },
102 { "nopd", DBG(NO_PD
), "Disable the primitive discard compute shader." },
103 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
104 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
105 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
106 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
107 { "dpbb", DBG(DPBB
), "Enable DPBB." },
108 { "dfsm", DBG(DFSM
), "Enable DFSM." },
109 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
110 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
111 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
112 { "notiling", DBG(NO_TILING
), "Disable tiling" },
113 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
114 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
115 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
116 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
117 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
120 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
121 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
122 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
123 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
124 { "testdmaperf", DBG(TEST_DMA_PERF
), "Test DMA performance" },
125 { "testgds", DBG(TEST_GDS
), "Test GDS." },
126 { "testgdsmm", DBG(TEST_GDS_MM
), "Test GDS memory management." },
127 { "testgdsoamm", DBG(TEST_GDS_OA_MM
), "Test GDS OA memory management." },
129 DEBUG_NAMED_VALUE_END
/* must be last */
132 void si_init_compiler(struct si_screen
*sscreen
, struct ac_llvm_compiler
*compiler
)
134 /* Only create the less-optimizing version of the compiler on APUs
135 * predating Ryzen (Raven). */
136 bool create_low_opt_compiler
= !sscreen
->info
.has_dedicated_vram
&&
137 sscreen
->info
.chip_class
<= GFX8
;
139 enum ac_target_machine_options tm_options
=
140 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
141 (sscreen
->debug_flags
& DBG(GISEL
) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
142 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
143 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
144 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
145 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0) |
146 (create_low_opt_compiler
? AC_TM_CREATE_LOW_OPT
: 0);
149 ac_init_llvm_compiler(compiler
, sscreen
->info
.family
, tm_options
);
150 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
152 if (compiler
->tm_wave32
)
153 compiler
->passes_wave32
= ac_create_llvm_passes(compiler
->tm_wave32
);
154 if (compiler
->low_opt_tm
)
155 compiler
->low_opt_passes
= ac_create_llvm_passes(compiler
->low_opt_tm
);
158 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
160 ac_destroy_llvm_compiler(compiler
);
166 static void si_destroy_context(struct pipe_context
*context
)
168 struct si_context
*sctx
= (struct si_context
*)context
;
171 util_queue_finish(&sctx
->screen
->shader_compiler_queue
);
172 util_queue_finish(&sctx
->screen
->shader_compiler_queue_low_priority
);
174 /* Unreference the framebuffer normally to disable related logic
177 struct pipe_framebuffer_state fb
= {};
178 if (context
->set_framebuffer_state
)
179 context
->set_framebuffer_state(context
, &fb
);
181 si_release_all_descriptors(sctx
);
183 if (sctx
->chip_class
>= GFX10
&& sctx
->has_graphics
)
184 gfx10_destroy_query(sctx
);
186 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
187 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
188 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
189 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
190 pipe_resource_reference(&sctx
->sample_pos_buffer
, NULL
);
191 si_resource_reference(&sctx
->border_color_buffer
, NULL
);
192 free(sctx
->border_color_table
);
193 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
194 si_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
195 si_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
197 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
198 if (sctx
->init_config_gs_rings
)
199 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
200 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
201 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
203 if (sctx
->fixed_func_tcs_shader
.cso
)
204 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
205 if (sctx
->custom_dsa_flush
)
206 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
207 if (sctx
->custom_blend_resolve
)
208 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
209 if (sctx
->custom_blend_fmask_decompress
)
210 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
211 if (sctx
->custom_blend_eliminate_fastclear
)
212 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
213 if (sctx
->custom_blend_dcc_decompress
)
214 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
215 if (sctx
->vs_blit_pos
)
216 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
217 if (sctx
->vs_blit_pos_layered
)
218 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
219 if (sctx
->vs_blit_color
)
220 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
221 if (sctx
->vs_blit_color_layered
)
222 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
223 if (sctx
->vs_blit_texcoord
)
224 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
225 if (sctx
->cs_clear_buffer
)
226 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_buffer
);
227 if (sctx
->cs_copy_buffer
)
228 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_buffer
);
229 if (sctx
->cs_copy_image
)
230 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image
);
231 if (sctx
->cs_copy_image_1d_array
)
232 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image_1d_array
);
233 if (sctx
->cs_clear_render_target
)
234 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target
);
235 if (sctx
->cs_clear_render_target_1d_array
)
236 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target_1d_array
);
237 if (sctx
->cs_clear_12bytes_buffer
)
238 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_12bytes_buffer
);
239 if (sctx
->cs_dcc_retile
)
240 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_dcc_retile
);
242 for (unsigned i
= 0; i
< ARRAY_SIZE(sctx
->cs_fmask_expand
); i
++) {
243 for (unsigned j
= 0; j
< ARRAY_SIZE(sctx
->cs_fmask_expand
[i
]); j
++) {
244 if (sctx
->cs_fmask_expand
[i
][j
]) {
245 sctx
->b
.delete_compute_state(&sctx
->b
,
246 sctx
->cs_fmask_expand
[i
][j
]);
252 util_blitter_destroy(sctx
->blitter
);
254 /* Release DCC stats. */
255 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
256 assert(!sctx
->dcc_stats
[i
].query_active
);
258 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
259 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
260 sctx
->b
.destroy_query(&sctx
->b
,
261 sctx
->dcc_stats
[i
].ps_stats
[j
]);
263 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
266 if (sctx
->query_result_shader
)
267 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
268 if (sctx
->sh_query_result_shader
)
269 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->sh_query_result_shader
);
272 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
274 sctx
->ws
->cs_destroy(sctx
->sdma_cs
);
276 sctx
->ws
->ctx_destroy(sctx
->ctx
);
278 if (sctx
->b
.stream_uploader
)
279 u_upload_destroy(sctx
->b
.stream_uploader
);
280 if (sctx
->b
.const_uploader
)
281 u_upload_destroy(sctx
->b
.const_uploader
);
282 if (sctx
->cached_gtt_allocator
)
283 u_upload_destroy(sctx
->cached_gtt_allocator
);
285 slab_destroy_child(&sctx
->pool_transfers
);
286 slab_destroy_child(&sctx
->pool_transfers_unsync
);
288 if (sctx
->allocator_zeroed_memory
)
289 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
291 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
292 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
293 sctx
->ws
->fence_reference(&sctx
->last_ib_barrier_fence
, NULL
);
294 si_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
295 si_resource_reference(&sctx
->index_ring
, NULL
);
296 si_resource_reference(&sctx
->barrier_buf
, NULL
);
297 si_resource_reference(&sctx
->last_ib_barrier_buf
, NULL
);
298 pb_reference(&sctx
->gds
, NULL
);
299 pb_reference(&sctx
->gds_oa
, NULL
);
301 si_destroy_compiler(&sctx
->compiler
);
303 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
305 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
306 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
308 util_dynarray_fini(&sctx
->resident_tex_handles
);
309 util_dynarray_fini(&sctx
->resident_img_handles
);
310 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
311 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
312 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
313 si_unref_sdma_uploads(sctx
);
314 free(sctx
->sdma_uploads
);
318 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
320 struct si_context
*sctx
= (struct si_context
*)ctx
;
321 struct si_screen
*sscreen
= sctx
->screen
;
322 enum pipe_reset_status status
= sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
324 if (status
!= PIPE_NO_RESET
) {
325 /* Call the state tracker to set a no-op API dispatch. */
326 if (sctx
->device_reset_callback
.reset
) {
327 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
,
331 /* Re-create the auxiliary context, because it won't submit
332 * any new IBs due to a GPU reset.
334 simple_mtx_lock(&sscreen
->aux_context_lock
);
336 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
337 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
338 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
340 sscreen
->aux_context
= si_create_context(&sscreen
->b
,
341 (sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0) |
342 (sscreen
->info
.has_graphics
? 0 : PIPE_CONTEXT_COMPUTE_ONLY
));
343 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, aux_log
);
344 simple_mtx_unlock(&sscreen
->aux_context_lock
);
349 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
350 const struct pipe_device_reset_callback
*cb
)
352 struct si_context
*sctx
= (struct si_context
*)ctx
;
355 sctx
->device_reset_callback
= *cb
;
357 memset(&sctx
->device_reset_callback
, 0,
358 sizeof(sctx
->device_reset_callback
));
361 /* Apitrace profiling:
362 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
363 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
364 * and remember its number.
365 * 3) In Mesa, enable queries and performance counters around that draw
366 * call and print the results.
367 * 4) glretrace --benchmark --markers ..
369 static void si_emit_string_marker(struct pipe_context
*ctx
,
370 const char *string
, int len
)
372 struct si_context
*sctx
= (struct si_context
*)ctx
;
374 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
377 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
380 static void si_set_debug_callback(struct pipe_context
*ctx
,
381 const struct pipe_debug_callback
*cb
)
383 struct si_context
*sctx
= (struct si_context
*)ctx
;
384 struct si_screen
*screen
= sctx
->screen
;
386 util_queue_finish(&screen
->shader_compiler_queue
);
387 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
392 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
395 static void si_set_log_context(struct pipe_context
*ctx
,
396 struct u_log_context
*log
)
398 struct si_context
*sctx
= (struct si_context
*)ctx
;
402 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
405 static void si_set_context_param(struct pipe_context
*ctx
,
406 enum pipe_context_param param
,
409 struct radeon_winsys
*ws
= ((struct si_context
*)ctx
)->ws
;
412 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
:
413 ws
->pin_threads_to_L3_cache(ws
, value
);
419 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
422 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
424 /* Don't create a context if it's not compute-only and hw is compute-only. */
425 if (!sscreen
->info
.has_graphics
&&
426 !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
429 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
430 struct radeon_winsys
*ws
= sscreen
->ws
;
432 bool stop_exec_on_failure
= (flags
& PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET
) != 0;
437 sctx
->has_graphics
= sscreen
->info
.chip_class
== GFX6
||
438 !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
);
440 if (flags
& PIPE_CONTEXT_DEBUG
)
441 sscreen
->record_llvm_ir
= true; /* racy but not critical */
443 sctx
->b
.screen
= screen
; /* this must be set first */
445 sctx
->b
.destroy
= si_destroy_context
;
446 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
447 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
449 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
450 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
452 sctx
->ws
= sscreen
->ws
;
453 sctx
->family
= sscreen
->info
.family
;
454 sctx
->chip_class
= sscreen
->info
.chip_class
;
456 if (sctx
->chip_class
== GFX7
||
457 sctx
->chip_class
== GFX8
||
458 sctx
->chip_class
== GFX9
) {
459 sctx
->eop_bug_scratch
= si_resource(
460 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
461 16 * sscreen
->info
.num_render_backends
));
462 if (!sctx
->eop_bug_scratch
)
466 /* Initialize context allocators. */
467 sctx
->allocator_zeroed_memory
=
468 u_suballocator_create(&sctx
->b
, 128 * 1024,
469 0, PIPE_USAGE_DEFAULT
,
470 SI_RESOURCE_FLAG_UNMAPPABLE
|
471 SI_RESOURCE_FLAG_CLEAR
, false);
472 if (!sctx
->allocator_zeroed_memory
)
475 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
476 0, PIPE_USAGE_STREAM
,
477 SI_RESOURCE_FLAG_READ_ONLY
);
478 if (!sctx
->b
.stream_uploader
)
481 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
482 0, PIPE_USAGE_STAGING
, 0);
483 if (!sctx
->cached_gtt_allocator
)
486 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
490 if (sscreen
->info
.num_rings
[RING_DMA
] &&
491 !(sscreen
->debug_flags
& DBG(NO_SDMA
)) &&
492 /* SDMA causes corruption on RX 580:
493 * https://gitlab.freedesktop.org/mesa/mesa/issues/1399
494 * https://gitlab.freedesktop.org/mesa/mesa/issues/1889
496 (sctx
->chip_class
!= GFX8
|| sscreen
->debug_flags
& DBG(FORCE_SDMA
)) &&
497 /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
498 * https://bugs.freedesktop.org/show_bug.cgi?id=111481
499 * https://gitlab.freedesktop.org/mesa/mesa/issues/1907
501 (sctx
->chip_class
!= GFX10
|| sscreen
->debug_flags
& DBG(FORCE_SDMA
))) {
502 sctx
->sdma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
503 (void*)si_flush_dma_cs
,
504 sctx
, stop_exec_on_failure
);
507 bool use_sdma_upload
= sscreen
->info
.has_dedicated_vram
&& sctx
->sdma_cs
;
508 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 256 * 1024,
509 0, PIPE_USAGE_DEFAULT
,
510 SI_RESOURCE_FLAG_32BIT
|
512 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA
: 0));
513 if (!sctx
->b
.const_uploader
)
517 u_upload_enable_flush_explicit(sctx
->b
.const_uploader
);
519 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
,
520 sctx
->has_graphics
? RING_GFX
: RING_COMPUTE
,
521 (void*)si_flush_gfx_cs
, sctx
, stop_exec_on_failure
);
524 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
525 sizeof(*sctx
->border_color_table
));
526 if (!sctx
->border_color_table
)
529 sctx
->border_color_buffer
= si_resource(
530 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
531 SI_MAX_BORDER_COLORS
*
532 sizeof(*sctx
->border_color_table
)));
533 if (!sctx
->border_color_buffer
)
536 sctx
->border_color_map
=
537 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
538 NULL
, PIPE_TRANSFER_WRITE
);
539 if (!sctx
->border_color_map
)
542 sctx
->ngg
= sscreen
->use_ngg
;
544 /* Initialize context functions used by graphics and compute. */
545 if (sctx
->chip_class
>= GFX10
)
546 sctx
->emit_cache_flush
= gfx10_emit_cache_flush
;
548 sctx
->emit_cache_flush
= si_emit_cache_flush
;
550 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
551 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
552 sctx
->b
.set_log_context
= si_set_log_context
;
553 sctx
->b
.set_context_param
= si_set_context_param
;
554 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
555 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
557 si_init_all_descriptors(sctx
);
558 si_init_buffer_functions(sctx
);
559 si_init_clear_functions(sctx
);
560 si_init_blit_functions(sctx
);
561 si_init_compute_functions(sctx
);
562 si_init_compute_blit_functions(sctx
);
563 si_init_debug_functions(sctx
);
564 si_init_fence_functions(sctx
);
565 si_init_query_functions(sctx
);
566 si_init_state_compute_functions(sctx
);
567 si_init_context_texture_functions(sctx
);
569 /* Initialize graphics-only context functions. */
570 if (sctx
->has_graphics
) {
571 if (sctx
->chip_class
>= GFX10
)
572 gfx10_init_query(sctx
);
573 si_init_msaa_functions(sctx
);
574 si_init_shader_functions(sctx
);
575 si_init_state_functions(sctx
);
576 si_init_streamout_functions(sctx
);
577 si_init_viewport_functions(sctx
);
579 sctx
->blitter
= util_blitter_create(&sctx
->b
);
580 if (sctx
->blitter
== NULL
)
582 sctx
->blitter
->skip_viewport_restore
= true;
584 /* Some states are expected to be always non-NULL. */
585 sctx
->noop_blend
= util_blitter_get_noop_blend_state(sctx
->blitter
);
586 sctx
->queued
.named
.blend
= sctx
->noop_blend
;
588 sctx
->noop_dsa
= util_blitter_get_noop_dsa_state(sctx
->blitter
);
589 sctx
->queued
.named
.dsa
= sctx
->noop_dsa
;
591 sctx
->discard_rasterizer_state
=
592 util_blitter_get_discard_rasterizer_state(sctx
->blitter
);
593 sctx
->queued
.named
.rasterizer
= sctx
->discard_rasterizer_state
;
595 si_init_draw_functions(sctx
);
597 /* If aux_context == NULL, we are initializing aux_context right now. */
598 bool is_aux_context
= !sscreen
->aux_context
;
599 si_initialize_prim_discard_tunables(sscreen
, is_aux_context
,
600 &sctx
->prim_discard_vertex_count_threshold
,
601 &sctx
->index_ring_size_per_ib
);
604 /* Initialize SDMA functions. */
605 if (sctx
->chip_class
>= GFX7
)
606 cik_init_sdma_functions(sctx
);
608 sctx
->dma_copy
= si_resource_copy_region
;
610 if (sscreen
->debug_flags
& DBG(FORCE_SDMA
))
611 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
613 sctx
->sample_mask
= 0xffff;
615 /* Initialize multimedia functions. */
616 if (sscreen
->info
.has_hw_decode
) {
617 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
618 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
620 sctx
->b
.create_video_codec
= vl_create_decoder
;
621 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
624 if (sctx
->chip_class
>= GFX9
) {
625 sctx
->wait_mem_scratch
= si_resource(
626 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 8));
627 if (!sctx
->wait_mem_scratch
)
630 /* Initialize the memory. */
631 si_cp_write_data(sctx
, sctx
->wait_mem_scratch
, 0, 4,
632 V_370_MEM
, V_370_ME
, &sctx
->wait_mem_number
);
635 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
636 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
637 if (sctx
->chip_class
== GFX7
) {
638 sctx
->null_const_buf
.buffer
=
639 pipe_aligned_buffer_create(screen
,
640 SI_RESOURCE_FLAG_32BIT
,
641 PIPE_USAGE_DEFAULT
, 16,
642 sctx
->screen
->info
.tcc_cache_line_size
);
643 if (!sctx
->null_const_buf
.buffer
)
645 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
647 unsigned start_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
648 for (shader
= start_shader
; shader
< SI_NUM_SHADERS
; shader
++) {
649 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
650 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
651 &sctx
->null_const_buf
);
655 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
656 &sctx
->null_const_buf
);
657 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
658 &sctx
->null_const_buf
);
659 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
660 &sctx
->null_const_buf
);
661 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
662 &sctx
->null_const_buf
);
663 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
664 &sctx
->null_const_buf
);
667 uint64_t max_threads_per_block
;
668 screen
->get_compute_param(screen
, PIPE_SHADER_IR_NIR
,
669 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
670 &max_threads_per_block
);
672 /* The maximum number of scratch waves. Scratch space isn't divided
673 * evenly between CUs. The number is only a function of the number of CUs.
674 * We can decrease the constant to decrease the scratch buffer size.
676 * sctx->scratch_waves must be >= the maximum posible size of
677 * 1 threadgroup, so that the hw doesn't hang from being unable
680 * The recommended value is 4 per CU at most. Higher numbers don't
681 * bring much benefit, but they still occupy chip resources (think
682 * async compute). I've seen ~2% performance difference between 4 and 32.
684 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
685 max_threads_per_block
/ 64);
687 /* Bindless handles. */
688 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
689 _mesa_key_pointer_equal
);
690 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
691 _mesa_key_pointer_equal
);
693 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
694 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
695 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
696 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
697 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
699 sctx
->sample_pos_buffer
=
700 pipe_buffer_create(sctx
->b
.screen
, 0, PIPE_USAGE_DEFAULT
,
701 sizeof(sctx
->sample_positions
));
702 pipe_buffer_write(&sctx
->b
, sctx
->sample_pos_buffer
, 0,
703 sizeof(sctx
->sample_positions
), &sctx
->sample_positions
);
705 /* this must be last */
706 si_begin_new_gfx_cs(sctx
);
708 if (sctx
->chip_class
== GFX7
) {
709 /* Clear the NULL constant buffer, because loads should return zeros.
710 * Note that this forces CP DMA to be used, because clover deadlocks
711 * for some reason when the compute codepath is used.
713 uint32_t clear_value
= 0;
714 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
715 sctx
->null_const_buf
.buffer
->width0
,
716 &clear_value
, 4, SI_COHERENCY_SHADER
, true);
720 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
721 si_destroy_context(&sctx
->b
);
725 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
726 void *priv
, unsigned flags
)
728 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
729 struct pipe_context
*ctx
;
731 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
732 flags
|= PIPE_CONTEXT_DEBUG
;
734 ctx
= si_create_context(screen
, flags
);
736 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
739 /* Clover (compute-only) is unsupported. */
740 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
743 /* When shaders are logged to stderr, asynchronous compilation is
745 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
748 /* Use asynchronous flushes only on amdgpu, since the radeon
749 * implementation for fence_server_sync is incomplete. */
750 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
751 si_replace_buffer_storage
,
752 sscreen
->info
.is_amdgpu
? si_create_fence
: NULL
,
753 &((struct si_context
*)ctx
)->tc
);
759 static void si_destroy_screen(struct pipe_screen
* pscreen
)
761 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
762 struct si_shader_part
*parts
[] = {
764 sscreen
->tcs_epilogs
,
771 if (!sscreen
->ws
->unref(sscreen
->ws
))
774 simple_mtx_destroy(&sscreen
->aux_context_lock
);
776 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
778 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
779 u_log_context_destroy(aux_log
);
783 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
785 util_queue_destroy(&sscreen
->shader_compiler_queue
);
786 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
788 /* Release the reference on glsl types of the compiler threads. */
789 glsl_type_singleton_decref();
791 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
792 si_destroy_compiler(&sscreen
->compiler
[i
]);
794 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
795 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
797 /* Free shader parts. */
798 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
800 struct si_shader_part
*part
= parts
[i
];
802 parts
[i
] = part
->next
;
803 si_shader_binary_clean(&part
->binary
);
807 simple_mtx_destroy(&sscreen
->shader_parts_mutex
);
808 si_destroy_shader_cache(sscreen
);
810 si_destroy_perfcounters(sscreen
);
811 si_gpu_load_kill_thread(sscreen
);
813 simple_mtx_destroy(&sscreen
->gpu_load_mutex
);
815 slab_destroy_parent(&sscreen
->pool_transfers
);
817 disk_cache_destroy(sscreen
->disk_shader_cache
);
818 sscreen
->ws
->destroy(sscreen
->ws
);
822 static void si_init_gs_info(struct si_screen
*sscreen
)
824 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
825 sscreen
->info
.family
);
828 static void si_test_vmfault(struct si_screen
*sscreen
)
830 struct pipe_context
*ctx
= sscreen
->aux_context
;
831 struct si_context
*sctx
= (struct si_context
*)ctx
;
832 struct pipe_resource
*buf
=
833 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
836 puts("Buffer allocation failed.");
840 si_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
842 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
843 si_cp_dma_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0,
844 SI_COHERENCY_NONE
, L2_BYPASS
);
845 ctx
->flush(ctx
, NULL
, 0);
846 puts("VM fault test: CP - done.");
848 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
849 si_sdma_clear_buffer(sctx
, buf
, 0, 4, 0);
850 ctx
->flush(ctx
, NULL
, 0);
851 puts("VM fault test: SDMA - done.");
853 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
854 util_test_constant_buffer(ctx
, buf
);
855 puts("VM fault test: Shader - done.");
860 static void si_test_gds_memory_management(struct si_context
*sctx
,
861 unsigned alloc_size
, unsigned alignment
,
862 enum radeon_bo_domain domain
)
864 struct radeon_winsys
*ws
= sctx
->ws
;
865 struct radeon_cmdbuf
*cs
[8];
866 struct pb_buffer
*gds_bo
[ARRAY_SIZE(cs
)];
868 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
869 cs
[i
] = ws
->cs_create(sctx
->ctx
, RING_COMPUTE
,
871 gds_bo
[i
] = ws
->buffer_create(ws
, alloc_size
, alignment
, domain
, 0);
875 for (unsigned iterations
= 0; iterations
< 20000; iterations
++) {
876 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
877 /* This clears GDS with CP DMA.
879 * We don't care if GDS is present. Just add some packet
880 * to make the GPU busy for a moment.
882 si_cp_dma_clear_buffer(sctx
, cs
[i
], NULL
, 0, alloc_size
, 0,
883 SI_CPDMA_SKIP_BO_LIST_UPDATE
|
884 SI_CPDMA_SKIP_CHECK_CS_SPACE
|
885 SI_CPDMA_SKIP_GFX_SYNC
, 0, 0);
887 ws
->cs_add_buffer(cs
[i
], gds_bo
[i
], domain
,
888 RADEON_USAGE_READWRITE
, 0);
889 ws
->cs_flush(cs
[i
], PIPE_FLUSH_ASYNC
, NULL
);
895 static void si_disk_cache_create(struct si_screen
*sscreen
)
897 /* Don't use the cache if shader dumping is enabled. */
898 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
901 struct mesa_sha1 ctx
;
902 unsigned char sha1
[20];
903 char cache_id
[20 * 2 + 1];
905 _mesa_sha1_init(&ctx
);
907 if (!disk_cache_get_function_identifier(si_disk_cache_create
, &ctx
) ||
908 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
,
912 _mesa_sha1_final(&ctx
, sha1
);
913 disk_cache_format_hex_id(cache_id
, sha1
, 20 * 2);
915 /* These flags affect shader compilation. */
916 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
917 uint64_t shader_debug_flags
= sscreen
->debug_flags
& ALL_FLAGS
;
919 /* Add the high bits of 32-bit addresses, which affects
920 * how 32-bit addresses are expanded to 64 bits.
922 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
923 assert((int16_t)sscreen
->info
.address32_hi
== (int32_t)sscreen
->info
.address32_hi
);
924 shader_debug_flags
|= (uint64_t)(sscreen
->info
.address32_hi
& 0xffff) << 32;
926 sscreen
->disk_shader_cache
=
927 disk_cache_create(sscreen
->info
.name
,
932 static void si_set_max_shader_compiler_threads(struct pipe_screen
*screen
,
933 unsigned max_threads
)
935 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
937 /* This function doesn't allow a greater number of threads than
938 * the queue had at its creation. */
939 util_queue_adjust_num_threads(&sscreen
->shader_compiler_queue
,
941 /* Don't change the number of threads on the low priority queue. */
944 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen
*screen
,
946 enum pipe_shader_type shader_type
)
948 struct si_shader_selector
*sel
= (struct si_shader_selector
*)shader
;
950 return util_queue_fence_is_signalled(&sel
->ready
);
953 static struct pipe_screen
*
954 radeonsi_screen_create_impl(struct radeon_winsys
*ws
,
955 const struct pipe_screen_config
*config
)
957 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
958 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
;
965 ws
->query_info(ws
, &sscreen
->info
);
967 if (sscreen
->info
.chip_class
== GFX10
&& LLVM_VERSION_MAJOR
< 9) {
968 fprintf(stderr
, "radeonsi: Navi family support requires LLVM 9 or higher\n");
973 if (sscreen
->info
.chip_class
>= GFX9
) {
974 sscreen
->se_tile_repeat
= 32 * sscreen
->info
.max_se
;
976 ac_get_raster_config(&sscreen
->info
,
977 &sscreen
->pa_sc_raster_config
,
978 &sscreen
->pa_sc_raster_config_1
,
979 &sscreen
->se_tile_repeat
);
982 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
984 sscreen
->debug_flags
|= debug_get_flags_option("AMD_DEBUG",
987 if (sscreen
->debug_flags
& DBG(NO_GFX
))
988 sscreen
->info
.has_graphics
= false;
990 /* Set functions first. */
991 sscreen
->b
.context_create
= si_pipe_create_context
;
992 sscreen
->b
.destroy
= si_destroy_screen
;
993 sscreen
->b
.set_max_shader_compiler_threads
=
994 si_set_max_shader_compiler_threads
;
995 sscreen
->b
.is_parallel_shader_compilation_finished
=
996 si_is_parallel_shader_compilation_finished
;
997 sscreen
->b
.finalize_nir
= si_finalize_nir
;
999 si_init_screen_get_functions(sscreen
);
1000 si_init_screen_buffer_functions(sscreen
);
1001 si_init_screen_fence_functions(sscreen
);
1002 si_init_screen_state_functions(sscreen
);
1003 si_init_screen_texture_functions(sscreen
);
1004 si_init_screen_query_functions(sscreen
);
1006 /* Set these flags in debug_flags early, so that the shader cache takes
1007 * them into account.
1009 if (driQueryOptionb(config
->options
,
1010 "glsl_correct_derivatives_after_discard"))
1011 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
1012 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
1013 sscreen
->debug_flags
|= DBG(SI_SCHED
);
1015 if (sscreen
->debug_flags
& DBG(INFO
))
1016 ac_print_gpu_info(&sscreen
->info
);
1018 slab_create_parent(&sscreen
->pool_transfers
,
1019 sizeof(struct si_transfer
), 64);
1021 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1022 if (sscreen
->force_aniso
== -1) {
1023 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1026 if (sscreen
->force_aniso
>= 0) {
1027 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1028 /* round down to a power of two */
1029 1 << util_logbase2(sscreen
->force_aniso
));
1032 (void) simple_mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
1033 (void) simple_mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
1035 si_init_gs_info(sscreen
);
1036 if (!si_init_shader_cache(sscreen
)) {
1042 #define OPT_BOOL(name, dflt, description) \
1043 sscreen->options.name = \
1044 driQueryOptionb(config->options, "radeonsi_"#name);
1045 #include "si_debug_options.h"
1048 si_disk_cache_create(sscreen
);
1050 /* Determine the number of shader compiler threads. */
1051 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
1053 if (hw_threads
>= 12) {
1054 num_comp_hi_threads
= hw_threads
* 3 / 4;
1055 num_comp_lo_threads
= hw_threads
/ 3;
1056 } else if (hw_threads
>= 6) {
1057 num_comp_hi_threads
= hw_threads
- 2;
1058 num_comp_lo_threads
= hw_threads
/ 2;
1059 } else if (hw_threads
>= 2) {
1060 num_comp_hi_threads
= hw_threads
- 1;
1061 num_comp_lo_threads
= hw_threads
/ 2;
1063 num_comp_hi_threads
= 1;
1064 num_comp_lo_threads
= 1;
1067 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
1068 ARRAY_SIZE(sscreen
->compiler
));
1069 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
1070 ARRAY_SIZE(sscreen
->compiler_lowp
));
1072 /* Take a reference on the glsl types for the compiler threads. */
1073 glsl_type_singleton_init_or_ref();
1075 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "sh",
1076 64, num_comp_hi_threads
,
1077 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1078 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
)) {
1079 si_destroy_shader_cache(sscreen
);
1081 glsl_type_singleton_decref();
1085 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
1087 64, num_comp_lo_threads
,
1088 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1089 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
|
1090 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
1091 si_destroy_shader_cache(sscreen
);
1093 glsl_type_singleton_decref();
1097 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1098 si_init_perfcounters(sscreen
);
1100 unsigned prim_discard_vertex_count_threshold
, tmp
;
1101 si_initialize_prim_discard_tunables(sscreen
, false,
1102 &prim_discard_vertex_count_threshold
,
1104 /* Compute-shader-based culling doesn't support VBOs in user SGPRs. */
1105 if (prim_discard_vertex_count_threshold
!= UINT_MAX
)
1106 sscreen
->num_vbos_in_user_sgprs
= sscreen
->info
.chip_class
>= GFX9
? 5 : 1;
1108 /* Determine tessellation ring info. */
1109 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= GFX7
&&
1110 sscreen
->info
.family
!= CHIP_CARRIZO
&&
1111 sscreen
->info
.family
!= CHIP_STONEY
;
1112 /* This must be one less than the maximum number due to a hw limitation.
1113 * Various hardware bugs need this.
1115 unsigned max_offchip_buffers_per_se
;
1117 if (sscreen
->info
.chip_class
>= GFX10
)
1118 max_offchip_buffers_per_se
= 256;
1119 /* Only certain chips can use the maximum value. */
1120 else if (sscreen
->info
.family
== CHIP_VEGA12
||
1121 sscreen
->info
.family
== CHIP_VEGA20
)
1122 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1124 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
1126 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1127 sscreen
->info
.max_se
;
1128 unsigned offchip_granularity
;
1130 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1131 * around by setting 4K granularity.
1133 if (sscreen
->info
.family
== CHIP_HAWAII
) {
1134 sscreen
->tess_offchip_block_dw_size
= 4096;
1135 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1137 sscreen
->tess_offchip_block_dw_size
= 8192;
1138 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1141 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
1142 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
1143 sscreen
->tess_offchip_block_dw_size
* 4;
1145 if (sscreen
->info
.chip_class
>= GFX7
) {
1146 if (sscreen
->info
.chip_class
>= GFX8
)
1147 --max_offchip_buffers
;
1148 sscreen
->vgt_hs_offchip_param
=
1149 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1150 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1152 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
1153 sscreen
->vgt_hs_offchip_param
=
1154 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1157 sscreen
->has_draw_indirect_multi
=
1158 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
1159 (sscreen
->info
.chip_class
== GFX8
&&
1160 sscreen
->info
.pfp_fw_version
>= 121 &&
1161 sscreen
->info
.me_fw_version
>= 87) ||
1162 (sscreen
->info
.chip_class
== GFX7
&&
1163 sscreen
->info
.pfp_fw_version
>= 211 &&
1164 sscreen
->info
.me_fw_version
>= 173) ||
1165 (sscreen
->info
.chip_class
== GFX6
&&
1166 sscreen
->info
.pfp_fw_version
>= 79 &&
1167 sscreen
->info
.me_fw_version
>= 142);
1169 sscreen
->has_out_of_order_rast
= sscreen
->info
.has_out_of_order_rast
&&
1170 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
1171 sscreen
->assume_no_z_fights
=
1172 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
1173 sscreen
->commutative_blend_add
=
1174 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
1176 sscreen
->use_ngg
= sscreen
->info
.chip_class
>= GFX10
&&
1177 sscreen
->info
.family
!= CHIP_NAVI14
&&
1178 !(sscreen
->debug_flags
& DBG(NO_NGG
));
1179 sscreen
->use_ngg_streamout
= false;
1181 /* Only enable primitive binning on APUs by default. */
1182 if (sscreen
->info
.chip_class
>= GFX10
) {
1183 sscreen
->dpbb_allowed
= true;
1184 sscreen
->dfsm_allowed
= !sscreen
->info
.has_dedicated_vram
;
1185 } else if (sscreen
->info
.chip_class
== GFX9
) {
1186 sscreen
->dpbb_allowed
= !sscreen
->info
.has_dedicated_vram
;
1187 sscreen
->dfsm_allowed
= !sscreen
->info
.has_dedicated_vram
;
1190 /* Process DPBB enable flags. */
1191 if (sscreen
->debug_flags
& DBG(DPBB
)) {
1192 sscreen
->dpbb_allowed
= true;
1193 if (sscreen
->debug_flags
& DBG(DFSM
))
1194 sscreen
->dfsm_allowed
= true;
1197 /* Process DPBB disable flags. */
1198 if (sscreen
->debug_flags
& DBG(NO_DPBB
)) {
1199 sscreen
->dpbb_allowed
= false;
1200 sscreen
->dfsm_allowed
= false;
1201 } else if (sscreen
->debug_flags
& DBG(NO_DFSM
)) {
1202 sscreen
->dfsm_allowed
= false;
1205 /* While it would be nice not to have this flag, we are constrained
1206 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1208 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
!= GFX9
;
1210 sscreen
->dcc_msaa_allowed
=
1211 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1213 (void) simple_mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1214 sscreen
->use_monolithic_shaders
=
1215 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1217 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SCACHE
|
1218 SI_CONTEXT_INV_VCACHE
;
1219 if (sscreen
->info
.chip_class
<= GFX8
) {
1220 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_L2
;
1221 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WB_L2
;
1224 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1225 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1232 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1234 * s >= z >= c (ignoring this only wastes memory)
1239 * Only MSAA color and depth buffers are overriden.
1241 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1242 const char *eqaa
= debug_get_option("EQAA", NULL
);
1245 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1246 sscreen
->eqaa_force_coverage_samples
= s
;
1247 sscreen
->eqaa_force_z_samples
= z
;
1248 sscreen
->eqaa_force_color_samples
= f
;
1252 sscreen
->ge_wave_size
= 64;
1253 sscreen
->ps_wave_size
= 64;
1254 sscreen
->compute_wave_size
= 64;
1256 if (sscreen
->info
.chip_class
>= GFX10
) {
1257 /* Pixels shaders: Wave64 is recommended.
1258 * Compute shaders: There are piglit failures with Wave32.
1260 sscreen
->ge_wave_size
= 32;
1262 if (sscreen
->debug_flags
& DBG(W32_GE
))
1263 sscreen
->ge_wave_size
= 32;
1264 if (sscreen
->debug_flags
& DBG(W32_PS
))
1265 sscreen
->ps_wave_size
= 32;
1266 if (sscreen
->debug_flags
& DBG(W32_CS
))
1267 sscreen
->compute_wave_size
= 32;
1269 if (sscreen
->debug_flags
& DBG(W64_GE
))
1270 sscreen
->ge_wave_size
= 64;
1271 if (sscreen
->debug_flags
& DBG(W64_PS
))
1272 sscreen
->ps_wave_size
= 64;
1273 if (sscreen
->debug_flags
& DBG(W64_CS
))
1274 sscreen
->compute_wave_size
= 64;
1277 /* Create the auxiliary context. This must be done last. */
1278 sscreen
->aux_context
= si_create_context(&sscreen
->b
,
1279 (sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0) |
1280 (sscreen
->info
.has_graphics
? 0 : PIPE_CONTEXT_COMPUTE_ONLY
));
1281 if (sscreen
->options
.aux_debug
) {
1282 struct u_log_context
*log
= CALLOC_STRUCT(u_log_context
);
1283 u_log_context_init(log
);
1284 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, log
);
1287 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1288 si_test_dma(sscreen
);
1290 if (sscreen
->debug_flags
& DBG(TEST_DMA_PERF
)) {
1291 si_test_dma_perf(sscreen
);
1294 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1295 DBG(TEST_VMFAULT_SDMA
) |
1296 DBG(TEST_VMFAULT_SHADER
)))
1297 si_test_vmfault(sscreen
);
1299 if (sscreen
->debug_flags
& DBG(TEST_GDS
))
1300 si_test_gds((struct si_context
*)sscreen
->aux_context
);
1302 if (sscreen
->debug_flags
& DBG(TEST_GDS_MM
)) {
1303 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1304 32 * 1024, 4, RADEON_DOMAIN_GDS
);
1306 if (sscreen
->debug_flags
& DBG(TEST_GDS_OA_MM
)) {
1307 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1308 4, 1, RADEON_DOMAIN_OA
);
1314 struct pipe_screen
*radeonsi_screen_create(int fd
, const struct pipe_screen_config
*config
)
1316 drmVersionPtr version
= drmGetVersion(fd
);
1317 struct radeon_winsys
*rw
= NULL
;
1319 switch (version
->version_major
) {
1321 rw
= radeon_drm_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1324 rw
= amdgpu_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1328 drmFreeVersion(version
);
1329 return rw
? rw
->screen
: NULL
;