src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "vl/vl_decoder.h"
  34
  35 #define SI_LLVM_DEFAULT_FEATURES \
  36         "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals"
  37
  38 /*
  39  * pipe_context
  40  */
  41 static void si_destroy_context(struct pipe_context *context)
  42 {
  43         struct si_context *sctx = (struct si_context *)context;
  44         int i;
  45
  46         si_dec_framebuffer_counters(&sctx->framebuffer.state);
  47
  48         si_release_all_descriptors(sctx);
  49
  50         if (sctx->ce_suballocator)
  51                 u_suballocator_destroy(sctx->ce_suballocator);
  52
  53         pipe_resource_reference(&sctx->esgs_ring, NULL);
  54         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  55         pipe_resource_reference(&sctx->tf_ring, NULL);
  56         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  57         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  58         r600_resource_reference(&sctx->border_color_buffer, NULL);
  59         free(sctx->border_color_table);
  60         r600_resource_reference(&sctx->scratch_buffer, NULL);
  61         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  62         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  63
  64         si_pm4_free_state(sctx, sctx->init_config, ~0);
  65         if (sctx->init_config_gs_rings)
  66                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  67         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  68                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  69
  70         if (sctx->fixed_func_tcs_shader.cso)
  71                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  72         if (sctx->custom_dsa_flush)
  73                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  74         if (sctx->custom_blend_resolve)
  75                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  76         if (sctx->custom_blend_decompress)
  77                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  78         if (sctx->custom_blend_fastclear)
  79                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  80         if (sctx->custom_blend_dcc_decompress)
  81                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  82         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  83
  84         if (sctx->blitter)
  85                 util_blitter_destroy(sctx->blitter);
  86
  87         r600_common_context_cleanup(&sctx->b);
  88
  89         LLVMDisposeTargetMachine(sctx->tm);
  90
  91         r600_resource_reference(&sctx->trace_buf, NULL);
  92         r600_resource_reference(&sctx->last_trace_buf, NULL);
  93         free(sctx->last_ib);
  94         if (sctx->last_bo_list) {
  95                 for (i = 0; i < sctx->last_bo_count; i++)
  96                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  97                 free(sctx->last_bo_list);
  98         }
  99         FREE(sctx);
 100 }
 101
 102 static enum pipe_reset_status
 103 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 104 {
 105         struct si_context *sctx = (struct si_context *)ctx;
 106
 107         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 108 }
 109
 110 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 111                                               void *priv, unsigned flags)
 112 {
 113         struct si_context *sctx = CALLOC_STRUCT(si_context);
 114         struct si_screen* sscreen = (struct si_screen *)screen;
 115         struct radeon_winsys *ws = sscreen->b.ws;
 116         LLVMTargetRef r600_target;
 117         const char *triple = "amdgcn--";
 118         int shader, i;
 119
 120         if (!sctx)
 121                 return NULL;
 122
 123         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 124                 flags |= PIPE_CONTEXT_DEBUG;
 125
 126         sctx->b.b.screen = screen; /* this must be set first */
 127         sctx->b.b.priv = priv;
 128         sctx->b.b.destroy = si_destroy_context;
 129         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 130         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 131         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 132
 133         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 134                 goto fail;
 135
 136         if (sscreen->b.info.drm_major == 3)
 137                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 138
 139         si_init_blit_functions(sctx);
 140         si_init_compute_functions(sctx);
 141         si_init_cp_dma_functions(sctx);
 142         si_init_debug_functions(sctx);
 143
 144         if (sscreen->b.info.has_uvd) {
 145                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 146                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 147         } else {
 148                 sctx->b.b.create_video_codec = vl_create_decoder;
 149                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 150         }
 151
 152         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 153                                        si_context_gfx_flush, sctx);
 154
 155         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
 156                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 157                 if (!sctx->ce_ib)
 158                         goto fail;
 159
 160                 if (ws->cs_add_const_preamble_ib) {
 161                         sctx->ce_preamble_ib =
 162                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 163
 164                         if (!sctx->ce_preamble_ib)
 165                                 goto fail;
 166                 }
 167
 168                 sctx->ce_suballocator =
 169                                 u_suballocator_create(&sctx->b.b, 1024 * 1024,
 170                                                       PIPE_BIND_CUSTOM,
 171                                                       PIPE_USAGE_DEFAULT, FALSE);
 172                 if (!sctx->ce_suballocator)
 173                         goto fail;
 174         }
 175
 176         sctx->b.gfx.flush = si_context_gfx_flush;
 177
 178         /* Border colors. */
 179         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 180                                           sizeof(*sctx->border_color_table));
 181         if (!sctx->border_color_table)
 182                 goto fail;
 183
 184         sctx->border_color_buffer = (struct r600_resource*)
 185                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 186                                    SI_MAX_BORDER_COLORS *
 187                                    sizeof(*sctx->border_color_table));
 188         if (!sctx->border_color_buffer)
 189                 goto fail;
 190
 191         sctx->border_color_map =
 192                 ws->buffer_map(sctx->border_color_buffer->buf,
 193                                NULL, PIPE_TRANSFER_WRITE);
 194         if (!sctx->border_color_map)
 195                 goto fail;
 196
 197         si_init_all_descriptors(sctx);
 198         si_init_state_functions(sctx);
 199         si_init_shader_functions(sctx);
 200
 201         if (sctx->b.chip_class >= CIK)
 202                 cik_init_sdma_functions(sctx);
 203         else
 204                 si_init_dma_functions(sctx);
 205
 206         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 207                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 208
 209         sctx->blitter = util_blitter_create(&sctx->b.b);
 210         if (sctx->blitter == NULL)
 211                 goto fail;
 212         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 213
 214         sctx->sample_mask.sample_mask = 0xffff;
 215
 216         /* these must be last */
 217         si_begin_new_cs(sctx);
 218         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 219
 220         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 221          * with a NULL buffer). We need to use a dummy buffer instead. */
 222         if (sctx->b.chip_class == CIK) {
 223                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 224                                                                  PIPE_USAGE_DEFAULT, 16);
 225                 if (!sctx->null_const_buf.buffer)
 226                         goto fail;
 227                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 228
 229                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 230                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 231                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 232                                                               &sctx->null_const_buf);
 233                         }
 234                 }
 235
 236                 /* Clear the NULL constant buffer, because loads should return zeros. */
 237                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 238                                      sctx->null_const_buf.buffer->width0, 0,
 239                                      R600_COHERENCY_SHADER);
 240         }
 241
 242         uint64_t max_threads_per_block;
 243         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 244                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 245                                   &max_threads_per_block);
 246
 247         /* The maximum number of scratch waves. Scratch space isn't divided
 248          * evenly between CUs. The number is only a function of the number of CUs.
 249          * We can decrease the constant to decrease the scratch buffer size.
 250          *
 251          * sctx->scratch_waves must be >= the maximum posible size of
 252          * 1 threadgroup, so that the hw doesn't hang from being unable
 253          * to start any.
 254          *
 255          * The recommended value is 4 per CU at most. Higher numbers don't
 256          * bring much benefit, but they still occupy chip resources (think
 257          * async compute). I've seen ~2% performance difference between 4 and 32.
 258          */
 259         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 260                                    max_threads_per_block / 64);
 261
 262         /* Initialize LLVM TargetMachine */
 263         r600_target = radeon_llvm_get_r600_target(triple);
 264         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 265                                            r600_get_llvm_processor_name(sscreen->b.family),
 266 #if HAVE_LLVM >= 0x0308
 267                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 268                                                 SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
 269 #endif
 270                                                 SI_LLVM_DEFAULT_FEATURES,
 271                                            LLVMCodeGenLevelDefault,
 272                                            LLVMRelocDefault,
 273                                            LLVMCodeModelDefault);
 274
 275         return &sctx->b.b;
 276 fail:
 277         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 278         si_destroy_context(&sctx->b.b);
 279         return NULL;
 280 }
 281
 282 /*
 283  * pipe_screen
 284  */
 285
 286 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 287 {
 288         struct si_screen *sscreen = (struct si_screen *)pscreen;
 289
 290         switch (param) {
 291         /* Supported features (boolean caps). */
 292         case PIPE_CAP_TWO_SIDED_STENCIL:
 293         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 294         case PIPE_CAP_ANISOTROPIC_FILTER:
 295         case PIPE_CAP_POINT_SPRITE:
 296         case PIPE_CAP_OCCLUSION_QUERY:
 297         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 298         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 299         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 300         case PIPE_CAP_TEXTURE_SWIZZLE:
 301         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 302         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 303         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 304         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 305         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 306         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 307         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 308         case PIPE_CAP_SM3:
 309         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 310         case PIPE_CAP_PRIMITIVE_RESTART:
 311         case PIPE_CAP_CONDITIONAL_RENDER:
 312         case PIPE_CAP_TEXTURE_BARRIER:
 313         case PIPE_CAP_INDEP_BLEND_ENABLE:
 314         case PIPE_CAP_INDEP_BLEND_FUNC:
 315         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 316         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 317         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 318         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 319         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 320         case PIPE_CAP_USER_INDEX_BUFFERS:
 321         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 322         case PIPE_CAP_START_INSTANCE:
 323         case PIPE_CAP_NPOT_TEXTURES:
 324         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 325         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 326         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 327         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 328         case PIPE_CAP_TGSI_INSTANCEID:
 329         case PIPE_CAP_COMPUTE:
 330         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 331         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 332         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 333         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 334         case PIPE_CAP_CUBE_MAP_ARRAY:
 335         case PIPE_CAP_SAMPLE_SHADING:
 336         case PIPE_CAP_DRAW_INDIRECT:
 337         case PIPE_CAP_CLIP_HALFZ:
 338         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 339         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 340         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 341         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 342         case PIPE_CAP_TGSI_TEXCOORD:
 343         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 344         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 345         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 346         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 347         case PIPE_CAP_SHAREABLE_SHADERS:
 348         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 349         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 350         case PIPE_CAP_TEXTURE_QUERY_LOD:
 351         case PIPE_CAP_TEXTURE_GATHER_SM5:
 352         case PIPE_CAP_TGSI_TXQS:
 353         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 354         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 355         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 356         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 357         case PIPE_CAP_INVALIDATE_BUFFER:
 358         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 359         case PIPE_CAP_QUERY_MEMORY_INFO:
 360         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 361         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 362         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 363         case PIPE_CAP_GENERATE_MIPMAP:
 364                 return 1;
 365
 366         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 367                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 368
 369         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 370                 return (sscreen->b.info.drm_major == 2 &&
 371                         sscreen->b.info.drm_minor >= 43) ||
 372                        sscreen->b.info.drm_major == 3;
 373
 374         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 375                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 376                 return sscreen->b.chip_class < CIK ||
 377                        (sscreen->b.info.drm_major == 2 &&
 378                         sscreen->b.info.drm_minor >= 35) ||
 379                        sscreen->b.info.drm_major == 3;
 380
 381         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 382                 return R600_MAP_BUFFER_ALIGNMENT;
 383
 384         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 385         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 386         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 387                 return 4;
 388         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 389                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 390
 391         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 392                 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
 393                                               PIPE_SHADER_CAP_SUPPORTED_IRS) &
 394                     (1 << PIPE_SHADER_IR_TGSI))
 395                         return 430;
 396                 return HAVE_LLVM >= 0x0309 ? 420 :
 397                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 398
 399         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 400                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 401
 402         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 403                 return 0;
 404
 405         /* Unsupported features. */
 406         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 407         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 408         case PIPE_CAP_USER_VERTEX_BUFFERS:
 409         case PIPE_CAP_FAKE_SW_MSAA:
 410         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 411         case PIPE_CAP_VERTEXID_NOBASE:
 412         case PIPE_CAP_CLEAR_TEXTURE:
 413         case PIPE_CAP_DRAW_PARAMETERS:
 414         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 415         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 416         case PIPE_CAP_STRING_MARKER:
 417         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 418         case PIPE_CAP_CULL_DISTANCE:
 419         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 420         case PIPE_CAP_TGSI_VOTE:
 421         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 422                 return 0;
 423
 424         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 425                 return 30;
 426
 427         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 428                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 429
 430         /* Stream output. */
 431         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 432                 return sscreen->b.has_streamout ? 4 : 0;
 433         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 434                 return sscreen->b.has_streamout ? 1 : 0;
 435         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 436         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 437                 return sscreen->b.has_streamout ? 32*4 : 0;
 438
 439         /* Geometry shader output. */
 440         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 441                 return 1024;
 442         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 443                 return 4095;
 444         case PIPE_CAP_MAX_VERTEX_STREAMS:
 445                 return 4;
 446
 447         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 448                 return 2048;
 449
 450         /* Texturing. */
 451         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 452         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 453                 return 15; /* 16384 */
 454         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 455                 /* textures support 8192, but layered rendering supports 2048 */
 456                 return 12;
 457         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 458                 /* textures support 8192, but layered rendering supports 2048 */
 459                 return 2048;
 460
 461         /* Render targets. */
 462         case PIPE_CAP_MAX_RENDER_TARGETS:
 463                 return 8;
 464
 465         case PIPE_CAP_MAX_VIEWPORTS:
 466                 return R600_MAX_VIEWPORTS;
 467
 468         /* Timer queries, present when the clock frequency is non zero. */
 469         case PIPE_CAP_QUERY_TIMESTAMP:
 470         case PIPE_CAP_QUERY_TIME_ELAPSED:
 471                 return sscreen->b.info.clock_crystal_freq != 0;
 472
 473         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 474         case PIPE_CAP_MIN_TEXEL_OFFSET:
 475                 return -32;
 476
 477         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 478         case PIPE_CAP_MAX_TEXEL_OFFSET:
 479                 return 31;
 480
 481         case PIPE_CAP_ENDIANNESS:
 482                 return PIPE_ENDIAN_LITTLE;
 483
 484         case PIPE_CAP_VENDOR_ID:
 485                 return ATI_VENDOR_ID;
 486         case PIPE_CAP_DEVICE_ID:
 487                 return sscreen->b.info.pci_id;
 488         case PIPE_CAP_ACCELERATED:
 489                 return 1;
 490         case PIPE_CAP_VIDEO_MEMORY:
 491                 return sscreen->b.info.vram_size >> 20;
 492         case PIPE_CAP_UMA:
 493                 return 0;
 494         case PIPE_CAP_PCI_GROUP:
 495                 return sscreen->b.info.pci_domain;
 496         case PIPE_CAP_PCI_BUS:
 497                 return sscreen->b.info.pci_bus;
 498         case PIPE_CAP_PCI_DEVICE:
 499                 return sscreen->b.info.pci_dev;
 500         case PIPE_CAP_PCI_FUNCTION:
 501                 return sscreen->b.info.pci_func;
 502         }
 503         return 0;
 504 }
 505
 506 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 507 {
 508         struct si_screen *sscreen = (struct si_screen *)pscreen;
 509
 510         switch(shader)
 511         {
 512         case PIPE_SHADER_FRAGMENT:
 513         case PIPE_SHADER_VERTEX:
 514         case PIPE_SHADER_GEOMETRY:
 515                 break;
 516         case PIPE_SHADER_TESS_CTRL:
 517         case PIPE_SHADER_TESS_EVAL:
 518                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 519                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 520                         return 0;
 521                 break;
 522         case PIPE_SHADER_COMPUTE:
 523                 switch (param) {
 524                 case PIPE_SHADER_CAP_PREFERRED_IR:
 525                         return PIPE_SHADER_IR_NATIVE;
 526
 527                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 528                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 529
 530                         /* Old kernels disallowed some register writes for SI
 531                          * that are used for indirect dispatches. */
 532                         if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
 533                                                    sscreen->b.info.drm_major == 3 ||
 534                                                    (sscreen->b.info.drm_major == 2 &&
 535                                                     sscreen->b.info.drm_minor >= 45)))
 536                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 537
 538                         return ir;
 539                 }
 540                 case PIPE_SHADER_CAP_DOUBLES:
 541                         return HAVE_LLVM >= 0x0307;
 542
 543                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 544                         uint64_t max_const_buffer_size;
 545                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 546                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 547                                 &max_const_buffer_size);
 548                         return max_const_buffer_size;
 549                 }
 550                 default:
 551                         /* If compute shaders don't require a special value
 552                          * for this cap, we can return the same value we
 553                          * do for other shader types. */
 554                         break;
 555                 }
 556                 break;
 557         default:
 558                 return 0;
 559         }
 560
 561         switch (param) {
 562         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 563         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 564         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 565         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 566                 return 16384;
 567         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 568                 return 32;
 569         case PIPE_SHADER_CAP_MAX_INPUTS:
 570                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 571         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 572                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 573         case PIPE_SHADER_CAP_MAX_TEMPS:
 574                 return 256; /* Max native temporaries. */
 575         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 576                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 577         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 578                 return SI_NUM_CONST_BUFFERS;
 579         case PIPE_SHADER_CAP_MAX_PREDS:
 580                 return 0; /* FIXME */
 581         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 582                 return 1;
 583         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 584                 return 1;
 585         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 586                 /* Indirection of geometry shader input dimension is not
 587                  * handled yet
 588                  */
 589                 return shader != PIPE_SHADER_GEOMETRY;
 590         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 591         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 592         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 593                 return 1;
 594         case PIPE_SHADER_CAP_INTEGERS:
 595                 return 1;
 596         case PIPE_SHADER_CAP_SUBROUTINES:
 597                 return 0;
 598         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 599         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 600                 return SI_NUM_SAMPLERS;
 601         case PIPE_SHADER_CAP_PREFERRED_IR:
 602                 return PIPE_SHADER_IR_TGSI;
 603         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 604                 return 0;
 605         case PIPE_SHADER_CAP_DOUBLES:
 606                 return HAVE_LLVM >= 0x0307;
 607         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 608         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 609                 return 0;
 610         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 611         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 612                 return 1;
 613         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 614                 return 32;
 615         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 616                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 617         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 618                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 619         }
 620         return 0;
 621 }
 622
 623 static void si_destroy_screen(struct pipe_screen* pscreen)
 624 {
 625         struct si_screen *sscreen = (struct si_screen *)pscreen;
 626         struct si_shader_part *parts[] = {
 627                 sscreen->vs_prologs,
 628                 sscreen->vs_epilogs,
 629                 sscreen->tcs_epilogs,
 630                 sscreen->ps_prologs,
 631                 sscreen->ps_epilogs
 632         };
 633         unsigned i;
 634
 635         if (!sscreen)
 636                 return;
 637
 638         if (!sscreen->b.ws->unref(sscreen->b.ws))
 639                 return;
 640
 641         /* Free shader parts. */
 642         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 643                 while (parts[i]) {
 644                         struct si_shader_part *part = parts[i];
 645
 646                         parts[i] = part->next;
 647                         radeon_shader_binary_clean(&part->binary);
 648                         FREE(part);
 649                 }
 650         }
 651         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 652         si_destroy_shader_cache(sscreen);
 653         r600_destroy_common_screen(&sscreen->b);
 654 }
 655
 656 static bool si_init_gs_info(struct si_screen *sscreen)
 657 {
 658         switch (sscreen->b.family) {
 659         case CHIP_OLAND:
 660         case CHIP_HAINAN:
 661         case CHIP_KAVERI:
 662         case CHIP_KABINI:
 663         case CHIP_MULLINS:
 664         case CHIP_ICELAND:
 665         case CHIP_CARRIZO:
 666         case CHIP_STONEY:
 667                 sscreen->gs_table_depth = 16;
 668                 return true;
 669         case CHIP_TAHITI:
 670         case CHIP_PITCAIRN:
 671         case CHIP_VERDE:
 672         case CHIP_BONAIRE:
 673         case CHIP_HAWAII:
 674         case CHIP_TONGA:
 675         case CHIP_FIJI:
 676         case CHIP_POLARIS10:
 677         case CHIP_POLARIS11:
 678                 sscreen->gs_table_depth = 32;
 679                 return true;
 680         default:
 681                 return false;
 682         }
 683 }
 684
 685 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 686 {
 687         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 688
 689         if (!sscreen) {
 690                 return NULL;
 691         }
 692
 693         /* Set functions first. */
 694         sscreen->b.b.context_create = si_create_context;
 695         sscreen->b.b.destroy = si_destroy_screen;
 696         sscreen->b.b.get_param = si_get_param;
 697         sscreen->b.b.get_shader_param = si_get_shader_param;
 698         sscreen->b.b.is_format_supported = si_is_format_supported;
 699         sscreen->b.b.resource_create = r600_resource_create_common;
 700
 701         si_init_screen_state_functions(sscreen);
 702
 703         if (!r600_common_screen_init(&sscreen->b, ws) ||
 704             !si_init_gs_info(sscreen) ||
 705             !si_init_shader_cache(sscreen)) {
 706                 FREE(sscreen);
 707                 return NULL;
 708         }
 709
 710         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 711                 si_init_perfcounters(sscreen);
 712
 713         sscreen->b.has_cp_dma = true;
 714         sscreen->b.has_streamout = true;
 715         pipe_mutex_init(sscreen->shader_parts_mutex);
 716         sscreen->use_monolithic_shaders =
 717                 HAVE_LLVM < 0x0308 ||
 718                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 719
 720         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 721                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 722
 723         /* Create the auxiliary context. This must be done last. */
 724         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 725
 726         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 727                 r600_test_dma(&sscreen->b);
 728
 729         return &sscreen->b.b;
 730 }