src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_log.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_suballoc.h"
  34 #include "util/u_tests.h"
  35 #include "util/xmlconfig.h"
  36 #include "vl/vl_decoder.h"
  37 #include "../ddebug/dd_util.h"
  38
  39 #include "compiler/nir/nir.h"
  40
  41 /*
  42  * pipe_context
  43  */
  44 static void si_destroy_context(struct pipe_context *context)
  45 {
  46         struct si_context *sctx = (struct si_context *)context;
  47         int i;
  48
  49         /* Unreference the framebuffer normally to disable related logic
  50          * properly.
  51          */
  52         struct pipe_framebuffer_state fb = {};
  53         if (context->set_framebuffer_state)
  54                 context->set_framebuffer_state(context, &fb);
  55
  56         si_release_all_descriptors(sctx);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_fmask_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  83         if (sctx->custom_blend_eliminate_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87         if (sctx->vs_blit_pos)
  88                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos);
  89         if (sctx->vs_blit_pos_layered)
  90                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos_layered);
  91         if (sctx->vs_blit_color)
  92                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color);
  93         if (sctx->vs_blit_color_layered)
  94                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color_layered);
  95         if (sctx->vs_blit_texcoord)
  96                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_texcoord);
  97
  98         if (sctx->blitter)
  99                 util_blitter_destroy(sctx->blitter);
 100
 101         si_common_context_cleanup(&sctx->b);
 102
 103         LLVMDisposeTargetMachine(sctx->tm);
 104
 105         si_saved_cs_reference(&sctx->current_saved_cs, NULL);
 106
 107         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 108         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 109
 110         util_dynarray_fini(&sctx->resident_tex_handles);
 111         util_dynarray_fini(&sctx->resident_img_handles);
 112         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 113         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 114         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 115         FREE(sctx);
 116 }
 117
 118 static enum pipe_reset_status
 119 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 120 {
 121         struct si_context *sctx = (struct si_context *)ctx;
 122
 123         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 124 }
 125
 126 /* Apitrace profiling:
 127  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 128  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 129  *      and remember its number.
 130  *   3) In Mesa, enable queries and performance counters around that draw
 131  *      call and print the results.
 132  *   4) glretrace --benchmark --markers ..
 133  */
 134 static void si_emit_string_marker(struct pipe_context *ctx,
 135                                   const char *string, int len)
 136 {
 137         struct si_context *sctx = (struct si_context *)ctx;
 138
 139         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 140
 141         if (sctx->b.log)
 142                 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
 143 }
 144
 145 static LLVMTargetMachineRef
 146 si_create_llvm_target_machine(struct si_screen *sscreen)
 147 {
 148         enum ac_target_machine_options tm_options =
 149                 (sscreen->b.debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
 150                 (sscreen->b.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
 151                 (sscreen->b.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
 152                 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
 153
 154         return ac_create_target_machine(sscreen->b.family, tm_options);
 155 }
 156
 157 static void si_set_debug_callback(struct pipe_context *ctx,
 158                                   const struct pipe_debug_callback *cb)
 159 {
 160         struct si_context *sctx = (struct si_context *)ctx;
 161         struct si_screen *screen = sctx->screen;
 162
 163         util_queue_finish(&screen->shader_compiler_queue);
 164         util_queue_finish(&screen->shader_compiler_queue_low_priority);
 165
 166         if (cb)
 167                 sctx->debug = *cb;
 168         else
 169                 memset(&sctx->debug, 0, sizeof(sctx->debug));
 170 }
 171
 172 static void si_set_log_context(struct pipe_context *ctx,
 173                                struct u_log_context *log)
 174 {
 175         struct si_context *sctx = (struct si_context *)ctx;
 176         sctx->b.log = log;
 177
 178         if (log)
 179                 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
 180 }
 181
 182 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 183                                               unsigned flags)
 184 {
 185         struct si_context *sctx = CALLOC_STRUCT(si_context);
 186         struct si_screen* sscreen = (struct si_screen *)screen;
 187         struct radeon_winsys *ws = sscreen->b.ws;
 188         int shader, i;
 189
 190         if (!sctx)
 191                 return NULL;
 192
 193         if (flags & PIPE_CONTEXT_DEBUG)
 194                 sscreen->record_llvm_ir = true; /* racy but not critical */
 195
 196         sctx->b.b.screen = screen; /* this must be set first */
 197         sctx->b.b.priv = NULL;
 198         sctx->b.b.destroy = si_destroy_context;
 199         sctx->b.b.emit_string_marker = si_emit_string_marker;
 200         sctx->b.b.set_debug_callback = si_set_debug_callback;
 201         sctx->b.b.set_log_context = si_set_log_context;
 202         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 203         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 204         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 205
 206         if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
 207                 goto fail;
 208
 209         if (sscreen->b.info.drm_major == 3)
 210                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 211
 212         si_init_clear_functions(sctx);
 213         si_init_blit_functions(sctx);
 214         si_init_compute_functions(sctx);
 215         si_init_cp_dma_functions(sctx);
 216         si_init_debug_functions(sctx);
 217         si_init_msaa_functions(sctx);
 218         si_init_streamout_functions(sctx);
 219
 220         if (sscreen->b.info.has_hw_decode) {
 221                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 222                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 223         } else {
 224                 sctx->b.b.create_video_codec = vl_create_decoder;
 225                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 226         }
 227
 228         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 229                                        si_context_gfx_flush, sctx);
 230         sctx->b.gfx.flush = si_context_gfx_flush;
 231
 232         /* Border colors. */
 233         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 234                                           sizeof(*sctx->border_color_table));
 235         if (!sctx->border_color_table)
 236                 goto fail;
 237
 238         sctx->border_color_buffer = (struct r600_resource*)
 239                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 240                                    SI_MAX_BORDER_COLORS *
 241                                    sizeof(*sctx->border_color_table));
 242         if (!sctx->border_color_buffer)
 243                 goto fail;
 244
 245         sctx->border_color_map =
 246                 ws->buffer_map(sctx->border_color_buffer->buf,
 247                                NULL, PIPE_TRANSFER_WRITE);
 248         if (!sctx->border_color_map)
 249                 goto fail;
 250
 251         si_init_all_descriptors(sctx);
 252         si_init_fence_functions(sctx);
 253         si_init_state_functions(sctx);
 254         si_init_shader_functions(sctx);
 255         si_init_viewport_functions(sctx);
 256         si_init_ia_multi_vgt_param_table(sctx);
 257
 258         if (sctx->b.chip_class >= CIK)
 259                 cik_init_sdma_functions(sctx);
 260         else
 261                 si_init_dma_functions(sctx);
 262
 263         if (sscreen->b.debug_flags & DBG(FORCE_DMA))
 264                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 265
 266         sctx->blitter = util_blitter_create(&sctx->b.b);
 267         if (sctx->blitter == NULL)
 268                 goto fail;
 269         sctx->blitter->draw_rectangle = si_draw_rectangle;
 270         sctx->blitter->skip_viewport_restore = true;
 271
 272         sctx->sample_mask.sample_mask = 0xffff;
 273
 274         /* these must be last */
 275         si_begin_new_cs(sctx);
 276
 277         if (sctx->b.chip_class >= GFX9) {
 278                 sctx->wait_mem_scratch = (struct r600_resource*)
 279                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 280                 if (!sctx->wait_mem_scratch)
 281                         goto fail;
 282
 283                 /* Initialize the memory. */
 284                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 285                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 286                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 287                             S_370_WR_CONFIRM(1) |
 288                             S_370_ENGINE_SEL(V_370_ME));
 289                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 290                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 291                 radeon_emit(cs, sctx->wait_mem_number);
 292         }
 293
 294         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 295          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 296         if (sctx->b.chip_class == CIK) {
 297                 sctx->null_const_buf.buffer =
 298                         si_aligned_buffer_create(screen,
 299                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 300                                                    PIPE_USAGE_DEFAULT, 16,
 301                                                    sctx->screen->b.info.tcc_cache_line_size);
 302                 if (!sctx->null_const_buf.buffer)
 303                         goto fail;
 304                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 305
 306                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 307                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 308                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 309                                                               &sctx->null_const_buf);
 310                         }
 311                 }
 312
 313                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 314                                  &sctx->null_const_buf);
 315                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 316                                  &sctx->null_const_buf);
 317                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 318                                  &sctx->null_const_buf);
 319                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 320                                  &sctx->null_const_buf);
 321                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 322                                  &sctx->null_const_buf);
 323
 324                 /* Clear the NULL constant buffer, because loads should return zeros. */
 325                 si_clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 326                                 sctx->null_const_buf.buffer->width0, 0,
 327                                 R600_COHERENCY_SHADER);
 328         }
 329
 330         uint64_t max_threads_per_block;
 331         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 332                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 333                                   &max_threads_per_block);
 334
 335         /* The maximum number of scratch waves. Scratch space isn't divided
 336          * evenly between CUs. The number is only a function of the number of CUs.
 337          * We can decrease the constant to decrease the scratch buffer size.
 338          *
 339          * sctx->scratch_waves must be >= the maximum posible size of
 340          * 1 threadgroup, so that the hw doesn't hang from being unable
 341          * to start any.
 342          *
 343          * The recommended value is 4 per CU at most. Higher numbers don't
 344          * bring much benefit, but they still occupy chip resources (think
 345          * async compute). I've seen ~2% performance difference between 4 and 32.
 346          */
 347         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 348                                    max_threads_per_block / 64);
 349
 350         sctx->tm = si_create_llvm_target_machine(sscreen);
 351
 352         /* Bindless handles. */
 353         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 354                                                     _mesa_key_pointer_equal);
 355         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 356                                                     _mesa_key_pointer_equal);
 357
 358         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 359         util_dynarray_init(&sctx->resident_img_handles, NULL);
 360         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 361         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 362         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 363
 364         return &sctx->b.b;
 365 fail:
 366         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 367         si_destroy_context(&sctx->b.b);
 368         return NULL;
 369 }
 370
 371 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 372                                                    void *priv, unsigned flags)
 373 {
 374         struct si_screen *sscreen = (struct si_screen *)screen;
 375         struct pipe_context *ctx;
 376
 377         if (sscreen->b.debug_flags & DBG(CHECK_VM))
 378                 flags |= PIPE_CONTEXT_DEBUG;
 379
 380         ctx = si_create_context(screen, flags);
 381
 382         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 383                 return ctx;
 384
 385         /* Clover (compute-only) is unsupported. */
 386         if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
 387                 return ctx;
 388
 389         /* When shaders are logged to stderr, asynchronous compilation is
 390          * disabled too. */
 391         if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
 392                 return ctx;
 393
 394         /* Use asynchronous flushes only on amdgpu, since the radeon
 395          * implementation for fence_server_sync is incomplete. */
 396         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 397                                        si_replace_buffer_storage,
 398                                        sscreen->b.info.drm_major >= 3 ? si_create_fence : NULL,
 399                                        &((struct si_context*)ctx)->b.tc);
 400 }
 401
 402 /*
 403  * pipe_screen
 404  */
 405 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 406 {
 407         /* Old kernels disallowed some register writes for SI
 408          * that are used for indirect dispatches. */
 409         return (sscreen->b.chip_class >= CIK ||
 410                 sscreen->b.info.drm_major == 3 ||
 411                 (sscreen->b.info.drm_major == 2 &&
 412                  sscreen->b.info.drm_minor >= 45));
 413 }
 414
 415 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 416 {
 417         struct si_screen *sscreen = (struct si_screen *)pscreen;
 418
 419         switch (param) {
 420         /* Supported features (boolean caps). */
 421         case PIPE_CAP_ACCELERATED:
 422         case PIPE_CAP_TWO_SIDED_STENCIL:
 423         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 424         case PIPE_CAP_ANISOTROPIC_FILTER:
 425         case PIPE_CAP_POINT_SPRITE:
 426         case PIPE_CAP_OCCLUSION_QUERY:
 427         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 428         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 429         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 430         case PIPE_CAP_TEXTURE_SWIZZLE:
 431         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 432         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 433         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 434         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 435         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 436         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 437         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 438         case PIPE_CAP_SM3:
 439         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 440         case PIPE_CAP_PRIMITIVE_RESTART:
 441         case PIPE_CAP_CONDITIONAL_RENDER:
 442         case PIPE_CAP_TEXTURE_BARRIER:
 443         case PIPE_CAP_INDEP_BLEND_ENABLE:
 444         case PIPE_CAP_INDEP_BLEND_FUNC:
 445         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 446         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 447         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 448         case PIPE_CAP_START_INSTANCE:
 449         case PIPE_CAP_NPOT_TEXTURES:
 450         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 451         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 452         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 453         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 454         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 455         case PIPE_CAP_TGSI_INSTANCEID:
 456         case PIPE_CAP_COMPUTE:
 457         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 458         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 459         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 460         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 461         case PIPE_CAP_CUBE_MAP_ARRAY:
 462         case PIPE_CAP_SAMPLE_SHADING:
 463         case PIPE_CAP_DRAW_INDIRECT:
 464         case PIPE_CAP_CLIP_HALFZ:
 465         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 466         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 467         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 468         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 469         case PIPE_CAP_TGSI_TEXCOORD:
 470         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 471         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 472         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 473         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 474         case PIPE_CAP_SHAREABLE_SHADERS:
 475         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 476         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 477         case PIPE_CAP_TEXTURE_QUERY_LOD:
 478         case PIPE_CAP_TEXTURE_GATHER_SM5:
 479         case PIPE_CAP_TGSI_TXQS:
 480         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 481         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 482         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 483         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 484         case PIPE_CAP_INVALIDATE_BUFFER:
 485         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 486         case PIPE_CAP_QUERY_MEMORY_INFO:
 487         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 488         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 489         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 490         case PIPE_CAP_GENERATE_MIPMAP:
 491         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 492         case PIPE_CAP_STRING_MARKER:
 493         case PIPE_CAP_CLEAR_TEXTURE:
 494         case PIPE_CAP_CULL_DISTANCE:
 495         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 496         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 497         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 498         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 499         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 500         case PIPE_CAP_DOUBLES:
 501         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 502         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 503         case PIPE_CAP_BINDLESS_TEXTURE:
 504         case PIPE_CAP_QUERY_TIMESTAMP:
 505         case PIPE_CAP_QUERY_TIME_ELAPSED:
 506         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 507         case PIPE_CAP_QUERY_SO_OVERFLOW:
 508         case PIPE_CAP_MEMOBJ:
 509         case PIPE_CAP_LOAD_CONSTBUF:
 510         case PIPE_CAP_INT64:
 511         case PIPE_CAP_INT64_DIVMOD:
 512         case PIPE_CAP_TGSI_CLOCK:
 513         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 514         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 515         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 516         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 517                 return 1;
 518
 519         case PIPE_CAP_TGSI_VOTE:
 520                 return HAVE_LLVM >= 0x0400;
 521
 522         case PIPE_CAP_TGSI_BALLOT:
 523                 return HAVE_LLVM >= 0x0500;
 524
 525         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 526                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 527
 528         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 529                 return (sscreen->b.info.drm_major == 2 &&
 530                         sscreen->b.info.drm_minor >= 43) ||
 531                        sscreen->b.info.drm_major == 3;
 532
 533         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 534                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 535                 return sscreen->b.chip_class < CIK ||
 536                        (sscreen->b.info.drm_major == 2 &&
 537                         sscreen->b.info.drm_minor >= 35) ||
 538                        sscreen->b.info.drm_major == 3;
 539
 540         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 541                 return R600_MAP_BUFFER_ALIGNMENT;
 542
 543         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 544         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 545         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 546         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 547         case PIPE_CAP_MAX_VERTEX_STREAMS:
 548         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 549                 return 4;
 550
 551         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 552                 if (sscreen->b.debug_flags & DBG(NIR))
 553                         return 140; /* no geometry and tessellation shaders yet */
 554                 if (si_have_tgsi_compute(sscreen))
 555                         return 450;
 556                 return 420;
 557
 558         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 559                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 560
 561         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 562         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 563         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 564                 /* SI doesn't support unaligned loads.
 565                  * CIK needs DRM 2.50.0 on radeon. */
 566                 return sscreen->b.chip_class == SI ||
 567                        (sscreen->b.info.drm_major == 2 &&
 568                         sscreen->b.info.drm_minor < 50);
 569
 570         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 571                 /* TODO: GFX9 hangs. */
 572                 if (sscreen->b.chip_class >= GFX9)
 573                         return 0;
 574                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 575                  * faults are mitigated in software.
 576                  */
 577                 if (sscreen->b.chip_class >= CIK &&
 578                     sscreen->b.info.drm_major == 3 &&
 579                     sscreen->b.info.drm_minor >= 13)
 580                         return RADEON_SPARSE_PAGE_SIZE;
 581                 return 0;
 582
 583         /* Unsupported features. */
 584         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 585         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 586         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 587         case PIPE_CAP_USER_VERTEX_BUFFERS:
 588         case PIPE_CAP_FAKE_SW_MSAA:
 589         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 590         case PIPE_CAP_VERTEXID_NOBASE:
 591         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 592         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 593         case PIPE_CAP_TGSI_FS_FBFETCH:
 594         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 595         case PIPE_CAP_UMA:
 596         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 597         case PIPE_CAP_POST_DEPTH_COVERAGE:
 598         case PIPE_CAP_TILE_RASTER_ORDER:
 599         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 600                 return 0;
 601
 602         case PIPE_CAP_NATIVE_FENCE_FD:
 603                 return sscreen->b.info.has_sync_file;
 604
 605         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 606                 return si_have_tgsi_compute(sscreen);
 607
 608         case PIPE_CAP_DRAW_PARAMETERS:
 609         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 610         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 611                 return sscreen->has_draw_indirect_multi;
 612
 613         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 614                 return 30;
 615
 616         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 617                 return sscreen->b.chip_class <= VI ?
 618                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 619
 620         /* Stream output. */
 621         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 622         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 623                 return 32*4;
 624
 625         /* Geometry shader output. */
 626         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 627                 return 1024;
 628         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 629                 return 4095;
 630
 631         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 632                 return 2048;
 633
 634         /* Texturing. */
 635         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 636         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 637                 return 15; /* 16384 */
 638         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 639                 /* textures support 8192, but layered rendering supports 2048 */
 640                 return 12;
 641         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 642                 /* textures support 8192, but layered rendering supports 2048 */
 643                 return 2048;
 644
 645         /* Viewports and render targets. */
 646         case PIPE_CAP_MAX_VIEWPORTS:
 647                 return SI_MAX_VIEWPORTS;
 648         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 649         case PIPE_CAP_MAX_RENDER_TARGETS:
 650                 return 8;
 651
 652         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 653         case PIPE_CAP_MIN_TEXEL_OFFSET:
 654                 return -32;
 655
 656         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 657         case PIPE_CAP_MAX_TEXEL_OFFSET:
 658                 return 31;
 659
 660         case PIPE_CAP_ENDIANNESS:
 661                 return PIPE_ENDIAN_LITTLE;
 662
 663         case PIPE_CAP_VENDOR_ID:
 664                 return ATI_VENDOR_ID;
 665         case PIPE_CAP_DEVICE_ID:
 666                 return sscreen->b.info.pci_id;
 667         case PIPE_CAP_VIDEO_MEMORY:
 668                 return sscreen->b.info.vram_size >> 20;
 669         case PIPE_CAP_PCI_GROUP:
 670                 return sscreen->b.info.pci_domain;
 671         case PIPE_CAP_PCI_BUS:
 672                 return sscreen->b.info.pci_bus;
 673         case PIPE_CAP_PCI_DEVICE:
 674                 return sscreen->b.info.pci_dev;
 675         case PIPE_CAP_PCI_FUNCTION:
 676                 return sscreen->b.info.pci_func;
 677         }
 678         return 0;
 679 }
 680
 681 static int si_get_shader_param(struct pipe_screen* pscreen,
 682                                enum pipe_shader_type shader,
 683                                enum pipe_shader_cap param)
 684 {
 685         struct si_screen *sscreen = (struct si_screen *)pscreen;
 686
 687         switch(shader)
 688         {
 689         case PIPE_SHADER_FRAGMENT:
 690         case PIPE_SHADER_VERTEX:
 691         case PIPE_SHADER_GEOMETRY:
 692         case PIPE_SHADER_TESS_CTRL:
 693         case PIPE_SHADER_TESS_EVAL:
 694                 break;
 695         case PIPE_SHADER_COMPUTE:
 696                 switch (param) {
 697                 case PIPE_SHADER_CAP_PREFERRED_IR:
 698                         return PIPE_SHADER_IR_NATIVE;
 699
 700                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 701                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 702
 703                         if (si_have_tgsi_compute(sscreen))
 704                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 705
 706                         return ir;
 707                 }
 708
 709                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 710                         uint64_t max_const_buffer_size;
 711                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 712                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 713                                 &max_const_buffer_size);
 714                         return MIN2(max_const_buffer_size, INT_MAX);
 715                 }
 716                 default:
 717                         /* If compute shaders don't require a special value
 718                          * for this cap, we can return the same value we
 719                          * do for other shader types. */
 720                         break;
 721                 }
 722                 break;
 723         default:
 724                 return 0;
 725         }
 726
 727         switch (param) {
 728         /* Shader limits. */
 729         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 730         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 731         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 732         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 733         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 734                 return 16384;
 735         case PIPE_SHADER_CAP_MAX_INPUTS:
 736                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 737         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 738                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 739         case PIPE_SHADER_CAP_MAX_TEMPS:
 740                 return 256; /* Max native temporaries. */
 741         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 742                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 743         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 744                 return SI_NUM_CONST_BUFFERS;
 745         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 746         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 747                 return SI_NUM_SAMPLERS;
 748         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 749                 return SI_NUM_SHADER_BUFFERS;
 750         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 751                 return SI_NUM_IMAGES;
 752         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 753                 return 32;
 754         case PIPE_SHADER_CAP_PREFERRED_IR:
 755                 if (sscreen->b.debug_flags & DBG(NIR) &&
 756                     (shader == PIPE_SHADER_VERTEX ||
 757                      shader == PIPE_SHADER_FRAGMENT))
 758                         return PIPE_SHADER_IR_NIR;
 759                 return PIPE_SHADER_IR_TGSI;
 760         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 761                 return 4;
 762
 763         /* Supported boolean features. */
 764         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 765         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 766         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 767         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 768         case PIPE_SHADER_CAP_INTEGERS:
 769         case PIPE_SHADER_CAP_INT64_ATOMICS:
 770         case PIPE_SHADER_CAP_FP16:
 771         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 772         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 773         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 774         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 775         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 776         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 777                 return 1;
 778
 779         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 780                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 781                 return shader != PIPE_SHADER_GEOMETRY &&
 782                        (sscreen->llvm_has_working_vgpr_indexing ||
 783                         /* TCS and TES load inputs directly from LDS or
 784                          * offchip memory, so indirect indexing is trivial. */
 785                         shader == PIPE_SHADER_TESS_CTRL ||
 786                         shader == PIPE_SHADER_TESS_EVAL);
 787
 788         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 789                 return sscreen->llvm_has_working_vgpr_indexing ||
 790                        /* TCS stores outputs directly to memory. */
 791                        shader == PIPE_SHADER_TESS_CTRL;
 792
 793         /* Unsupported boolean features. */
 794         case PIPE_SHADER_CAP_SUBROUTINES:
 795         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 796         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 797         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 798                 return 0;
 799         }
 800         return 0;
 801 }
 802
 803 static const struct nir_shader_compiler_options nir_options = {
 804         .vertex_id_zero_based = true,
 805         .lower_scmp = true,
 806         .lower_flrp32 = true,
 807         .lower_fsat = true,
 808         .lower_fdiv = true,
 809         .lower_sub = true,
 810         .lower_ffma = true,
 811         .lower_pack_snorm_2x16 = true,
 812         .lower_pack_snorm_4x8 = true,
 813         .lower_pack_unorm_2x16 = true,
 814         .lower_pack_unorm_4x8 = true,
 815         .lower_unpack_snorm_2x16 = true,
 816         .lower_unpack_snorm_4x8 = true,
 817         .lower_unpack_unorm_2x16 = true,
 818         .lower_unpack_unorm_4x8 = true,
 819         .lower_extract_byte = true,
 820         .lower_extract_word = true,
 821         .max_unroll_iterations = 32,
 822         .native_integers = true,
 823 };
 824
 825 static const void *
 826 si_get_compiler_options(struct pipe_screen *screen,
 827                         enum pipe_shader_ir ir,
 828                         enum pipe_shader_type shader)
 829 {
 830         assert(ir == PIPE_SHADER_IR_NIR);
 831         return &nir_options;
 832 }
 833
 834 static void si_destroy_screen(struct pipe_screen* pscreen)
 835 {
 836         struct si_screen *sscreen = (struct si_screen *)pscreen;
 837         struct si_shader_part *parts[] = {
 838                 sscreen->vs_prologs,
 839                 sscreen->tcs_epilogs,
 840                 sscreen->gs_prologs,
 841                 sscreen->ps_prologs,
 842                 sscreen->ps_epilogs
 843         };
 844         unsigned i;
 845
 846         if (!sscreen->b.ws->unref(sscreen->b.ws))
 847                 return;
 848
 849         util_queue_destroy(&sscreen->shader_compiler_queue);
 850         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 851
 852         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 853                 if (sscreen->tm[i])
 854                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 855
 856         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 857                 if (sscreen->tm_low_priority[i])
 858                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 859
 860         /* Free shader parts. */
 861         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 862                 while (parts[i]) {
 863                         struct si_shader_part *part = parts[i];
 864
 865                         parts[i] = part->next;
 866                         si_radeon_shader_binary_clean(&part->binary);
 867                         FREE(part);
 868                 }
 869         }
 870         mtx_destroy(&sscreen->shader_parts_mutex);
 871         si_destroy_shader_cache(sscreen);
 872         si_destroy_common_screen(&sscreen->b);
 873 }
 874
 875 static bool si_init_gs_info(struct si_screen *sscreen)
 876 {
 877         /* gs_table_depth is not used by GFX9 */
 878         if (sscreen->b.chip_class >= GFX9)
 879                 return true;
 880
 881         switch (sscreen->b.family) {
 882         case CHIP_OLAND:
 883         case CHIP_HAINAN:
 884         case CHIP_KAVERI:
 885         case CHIP_KABINI:
 886         case CHIP_MULLINS:
 887         case CHIP_ICELAND:
 888         case CHIP_CARRIZO:
 889         case CHIP_STONEY:
 890                 sscreen->gs_table_depth = 16;
 891                 return true;
 892         case CHIP_TAHITI:
 893         case CHIP_PITCAIRN:
 894         case CHIP_VERDE:
 895         case CHIP_BONAIRE:
 896         case CHIP_HAWAII:
 897         case CHIP_TONGA:
 898         case CHIP_FIJI:
 899         case CHIP_POLARIS10:
 900         case CHIP_POLARIS11:
 901         case CHIP_POLARIS12:
 902                 sscreen->gs_table_depth = 32;
 903                 return true;
 904         default:
 905                 return false;
 906         }
 907 }
 908
 909 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 910 {
 911         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 912         unsigned i;
 913
 914         if (!family)
 915                 return;
 916
 917         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 918                 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
 919                         /* Override family and chip_class. */
 920                         sscreen->b.family = sscreen->b.info.family = i;
 921
 922                         if (i >= CHIP_VEGA10)
 923                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 924                         else if (i >= CHIP_TONGA)
 925                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 926                         else if (i >= CHIP_BONAIRE)
 927                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 928                         else
 929                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 930
 931                         /* Don't submit any IBs. */
 932                         setenv("RADEON_NOOP", "1", 1);
 933                         return;
 934                 }
 935         }
 936
 937         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 938         exit(1);
 939 }
 940
 941 static void si_test_vmfault(struct si_screen *sscreen)
 942 {
 943         struct pipe_context *ctx = sscreen->b.aux_context;
 944         struct si_context *sctx = (struct si_context *)ctx;
 945         struct pipe_resource *buf =
 946                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 947
 948         if (!buf) {
 949                 puts("Buffer allocation failed.");
 950                 exit(1);
 951         }
 952
 953         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 954
 955         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_CP)) {
 956                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 957                 ctx->flush(ctx, NULL, 0);
 958                 puts("VM fault test: CP - done.");
 959         }
 960         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SDMA)) {
 961                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 962                 ctx->flush(ctx, NULL, 0);
 963                 puts("VM fault test: SDMA - done.");
 964         }
 965         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SHADER)) {
 966                 util_test_constant_buffer(ctx, buf);
 967                 puts("VM fault test: Shader - done.");
 968         }
 969         exit(0);
 970 }
 971
 972 static void radeonsi_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 973 {
 974         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 975 }
 976
 977 static void radeonsi_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 978 {
 979         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 980
 981         ac_compute_device_uuid(&rscreen->info, uuid, PIPE_UUID_SIZE);
 982 }
 983
 984 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 985                                            const struct pipe_screen_config *config)
 986 {
 987         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 988         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 989
 990         if (!sscreen) {
 991                 return NULL;
 992         }
 993
 994         /* Set functions first. */
 995         sscreen->b.b.context_create = si_pipe_create_context;
 996         sscreen->b.b.destroy = si_destroy_screen;
 997         sscreen->b.b.get_param = si_get_param;
 998         sscreen->b.b.get_shader_param = si_get_shader_param;
 999         sscreen->b.b.get_compiler_options = si_get_compiler_options;
1000         sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
1001         sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
1002         sscreen->b.b.resource_create = si_resource_create_common;
1003
1004         si_init_screen_fence_functions(sscreen);
1005         si_init_screen_state_functions(sscreen);
1006
1007         /* Set these flags in debug_flags early, so that the shader cache takes
1008          * them into account.
1009          */
1010         if (driQueryOptionb(config->options,
1011                             "glsl_correct_derivatives_after_discard"))
1012                 sscreen->b.debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1013         if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
1014                 sscreen->b.debug_flags |= DBG(SI_SCHED);
1015
1016         if (!si_common_screen_init(&sscreen->b, ws) ||
1017             !si_init_gs_info(sscreen) ||
1018             !si_init_shader_cache(sscreen)) {
1019                 FREE(sscreen);
1020                 return NULL;
1021         }
1022
1023         /* Only enable as many threads as we have target machines, but at most
1024          * the number of CPUs - 1 if there is more than one.
1025          */
1026         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
1027         num_threads = MAX2(1, num_threads - 1);
1028         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1029         num_compiler_threads_lowprio =
1030                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1031
1032         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1033                              32, num_compiler_threads,
1034                              UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1035                 si_destroy_shader_cache(sscreen);
1036                 FREE(sscreen);
1037                 return NULL;
1038         }
1039
1040         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1041                              "si_shader_low",
1042                              32, num_compiler_threads_lowprio,
1043                              UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1044                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1045                si_destroy_shader_cache(sscreen);
1046                FREE(sscreen);
1047                return NULL;
1048         }
1049
1050         si_handle_env_var_force_family(sscreen);
1051
1052         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1053                 si_init_perfcounters(sscreen);
1054
1055         /* Hawaii has a bug with offchip buffers > 256 that can be worked
1056          * around by setting 4K granularity.
1057          */
1058         sscreen->tess_offchip_block_dw_size =
1059                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1060
1061         /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1062          * on SI. */
1063         sscreen->has_clear_state = sscreen->b.chip_class >= CIK;
1064
1065         sscreen->has_distributed_tess =
1066                 sscreen->b.chip_class >= VI &&
1067                 sscreen->b.info.max_se >= 2;
1068
1069         sscreen->has_draw_indirect_multi =
1070                 (sscreen->b.family >= CHIP_POLARIS10) ||
1071                 (sscreen->b.chip_class == VI &&
1072                  sscreen->b.info.pfp_fw_version >= 121 &&
1073                  sscreen->b.info.me_fw_version >= 87) ||
1074                 (sscreen->b.chip_class == CIK &&
1075                  sscreen->b.info.pfp_fw_version >= 211 &&
1076                  sscreen->b.info.me_fw_version >= 173) ||
1077                 (sscreen->b.chip_class == SI &&
1078                  sscreen->b.info.pfp_fw_version >= 79 &&
1079                  sscreen->b.info.me_fw_version >= 142);
1080
1081         sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
1082                                          sscreen->b.info.max_se >= 2 &&
1083                                          !(sscreen->b.debug_flags & DBG(NO_OUT_OF_ORDER));
1084         sscreen->assume_no_z_fights =
1085                 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1086         sscreen->commutative_blend_add =
1087                 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1088         sscreen->clear_db_cache_before_clear =
1089                 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1090         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1091                                             sscreen->b.family <= CHIP_POLARIS12) ||
1092                                            sscreen->b.family == CHIP_VEGA10 ||
1093                                            sscreen->b.family == CHIP_RAVEN;
1094         sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
1095                                         sscreen->b.family == CHIP_RAVEN;
1096
1097         if (sscreen->b.debug_flags & DBG(DPBB)) {
1098                 sscreen->dpbb_allowed = true;
1099         } else {
1100                 /* Only enable primitive binning on Raven by default. */
1101                 sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
1102                                         !(sscreen->b.debug_flags & DBG(NO_DPBB));
1103         }
1104
1105         if (sscreen->b.debug_flags & DBG(DFSM)) {
1106                 sscreen->dfsm_allowed = sscreen->dpbb_allowed;
1107         } else {
1108                 sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1109                                         !(sscreen->b.debug_flags & DBG(NO_DFSM));
1110         }
1111
1112         /* While it would be nice not to have this flag, we are constrained
1113          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1114          * on GFX9.
1115          */
1116         sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1117
1118         /* Some chips have RB+ registers, but don't support RB+. Those must
1119          * always disable it.
1120          */
1121         if (sscreen->b.family == CHIP_STONEY ||
1122             sscreen->b.chip_class >= GFX9) {
1123                 sscreen->b.has_rbplus = true;
1124
1125                 sscreen->b.rbplus_allowed =
1126                         !(sscreen->b.debug_flags & DBG(NO_RB_PLUS)) &&
1127                         (sscreen->b.family == CHIP_STONEY ||
1128                          sscreen->b.family == CHIP_RAVEN);
1129         }
1130
1131         sscreen->b.dcc_msaa_allowed =
1132                 !(sscreen->b.debug_flags & DBG(NO_DCC_MSAA)) &&
1133                 (sscreen->b.debug_flags & DBG(DCC_MSAA) ||
1134                  sscreen->b.chip_class == VI);
1135
1136         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1137         sscreen->use_monolithic_shaders =
1138                 (sscreen->b.debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1139
1140         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1141                                             SI_CONTEXT_INV_VMEM_L1;
1142         if (sscreen->b.chip_class <= VI) {
1143                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1144                 sscreen->b.barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1145         }
1146
1147         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1148
1149         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1150                 sscreen->b.debug_flags |= DBG_ALL_SHADERS;
1151
1152         for (i = 0; i < num_compiler_threads; i++)
1153                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1154         for (i = 0; i < num_compiler_threads_lowprio; i++)
1155                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1156
1157         /* Create the auxiliary context. This must be done last. */
1158         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1159
1160         if (sscreen->b.debug_flags & DBG(TEST_DMA))
1161                 si_test_dma(sscreen);
1162
1163         if (sscreen->b.debug_flags & (DBG(TEST_VMFAULT_CP) |
1164                                       DBG(TEST_VMFAULT_SDMA) |
1165                                       DBG(TEST_VMFAULT_SHADER)))
1166                 si_test_vmfault(sscreen);
1167
1168         return &sscreen->b.b;
1169 }