2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
44 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
45 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
48 #include <llvm/Config/llvm-config.h>
50 static const struct debug_named_value debug_options
[] = {
51 /* Shader logging options: */
52 { "vs", DBG(VS
), "Print vertex shaders" },
53 { "ps", DBG(PS
), "Print pixel shaders" },
54 { "gs", DBG(GS
), "Print geometry shaders" },
55 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
56 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
57 { "cs", DBG(CS
), "Print compute shaders" },
58 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
59 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
60 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
61 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
63 /* Shader compiler options the shader cache should be aware of: */
64 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL
), "Enable LLVM global instruction selector." },
66 { "w32ge", DBG(W32_GE
), "Use Wave32 for vertex, tessellation, and geometry shaders." },
67 { "w32ps", DBG(W32_PS
), "Use Wave32 for pixel shaders." },
68 { "w32cs", DBG(W32_CS
), "Use Wave32 for computes shaders." },
69 { "w64ge", DBG(W64_GE
), "Use Wave64 for vertex, tessellation, and geometry shaders." },
70 { "w64ps", DBG(W64_PS
), "Use Wave64 for pixel shaders." },
71 { "w64cs", DBG(W64_CS
), "Use Wave64 for computes shaders." },
73 /* Shader compiler options (with no effect on the shader cache): */
74 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
75 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
76 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
78 /* Information logging options: */
79 { "info", DBG(INFO
), "Print driver information" },
80 { "tex", DBG(TEX
), "Print texture info" },
81 { "compute", DBG(COMPUTE
), "Print compute info" },
82 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
85 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
86 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
87 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
88 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
89 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
90 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
92 /* 3D engine options: */
93 { "nogfx", DBG(NO_GFX
), "Disable graphics. Only multimedia compute paths can be used." },
94 { "nongg", DBG(NO_NGG
), "Disable NGG and use the legacy pipeline." },
95 { "alwayspd", DBG(ALWAYS_PD
), "Always enable the primitive discard compute shader." },
96 { "pd", DBG(PD
), "Enable the primitive discard compute shader for large draw calls." },
97 { "nopd", DBG(NO_PD
), "Disable the primitive discard compute shader." },
98 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
99 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
100 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
101 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
102 { "dpbb", DBG(DPBB
), "Enable DPBB." },
103 { "dfsm", DBG(DFSM
), "Enable DFSM." },
104 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
105 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
106 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
107 { "notiling", DBG(NO_TILING
), "Disable tiling" },
108 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
109 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
110 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
111 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
112 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
115 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
116 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
117 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
118 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
119 { "testdmaperf", DBG(TEST_DMA_PERF
), "Test DMA performance" },
120 { "testgds", DBG(TEST_GDS
), "Test GDS." },
121 { "testgdsmm", DBG(TEST_GDS_MM
), "Test GDS memory management." },
122 { "testgdsoamm", DBG(TEST_GDS_OA_MM
), "Test GDS OA memory management." },
124 DEBUG_NAMED_VALUE_END
/* must be last */
127 static void si_init_compiler(struct si_screen
*sscreen
,
128 struct ac_llvm_compiler
*compiler
)
130 /* Only create the less-optimizing version of the compiler on APUs
131 * predating Ryzen (Raven). */
132 bool create_low_opt_compiler
= !sscreen
->info
.has_dedicated_vram
&&
133 sscreen
->info
.chip_class
<= GFX8
;
135 enum ac_target_machine_options tm_options
=
136 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
137 (sscreen
->debug_flags
& DBG(GISEL
) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
138 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
139 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
140 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
141 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0) |
142 (create_low_opt_compiler
? AC_TM_CREATE_LOW_OPT
: 0);
145 ac_init_llvm_compiler(compiler
, sscreen
->info
.family
, tm_options
);
146 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
148 if (compiler
->tm_wave32
)
149 compiler
->passes_wave32
= ac_create_llvm_passes(compiler
->tm_wave32
);
150 if (compiler
->low_opt_tm
)
151 compiler
->low_opt_passes
= ac_create_llvm_passes(compiler
->low_opt_tm
);
154 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
156 ac_destroy_llvm_compiler(compiler
);
162 static void si_destroy_context(struct pipe_context
*context
)
164 struct si_context
*sctx
= (struct si_context
*)context
;
167 util_queue_finish(&sctx
->screen
->shader_compiler_queue
);
168 util_queue_finish(&sctx
->screen
->shader_compiler_queue_low_priority
);
170 /* Unreference the framebuffer normally to disable related logic
173 struct pipe_framebuffer_state fb
= {};
174 if (context
->set_framebuffer_state
)
175 context
->set_framebuffer_state(context
, &fb
);
177 si_release_all_descriptors(sctx
);
179 if (sctx
->chip_class
>= GFX10
&& sctx
->has_graphics
)
180 gfx10_destroy_query(sctx
);
182 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
183 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
184 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
185 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
186 pipe_resource_reference(&sctx
->sample_pos_buffer
, NULL
);
187 si_resource_reference(&sctx
->border_color_buffer
, NULL
);
188 free(sctx
->border_color_table
);
189 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
190 si_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
191 si_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
193 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
194 if (sctx
->init_config_gs_rings
)
195 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
196 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
197 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
199 if (sctx
->fixed_func_tcs_shader
.cso
)
200 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
201 if (sctx
->custom_dsa_flush
)
202 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
203 if (sctx
->custom_blend_resolve
)
204 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
205 if (sctx
->custom_blend_fmask_decompress
)
206 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
207 if (sctx
->custom_blend_eliminate_fastclear
)
208 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
209 if (sctx
->custom_blend_dcc_decompress
)
210 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
211 if (sctx
->vs_blit_pos
)
212 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
213 if (sctx
->vs_blit_pos_layered
)
214 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
215 if (sctx
->vs_blit_color
)
216 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
217 if (sctx
->vs_blit_color_layered
)
218 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
219 if (sctx
->vs_blit_texcoord
)
220 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
221 if (sctx
->cs_clear_buffer
)
222 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_buffer
);
223 if (sctx
->cs_copy_buffer
)
224 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_buffer
);
225 if (sctx
->cs_copy_image
)
226 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image
);
227 if (sctx
->cs_copy_image_1d_array
)
228 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image_1d_array
);
229 if (sctx
->cs_clear_render_target
)
230 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target
);
231 if (sctx
->cs_clear_render_target_1d_array
)
232 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target_1d_array
);
233 if (sctx
->cs_dcc_retile
)
234 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_dcc_retile
);
236 for (unsigned i
= 0; i
< ARRAY_SIZE(sctx
->cs_fmask_expand
); i
++) {
237 for (unsigned j
= 0; j
< ARRAY_SIZE(sctx
->cs_fmask_expand
[i
]); j
++) {
238 if (sctx
->cs_fmask_expand
[i
][j
]) {
239 sctx
->b
.delete_compute_state(&sctx
->b
,
240 sctx
->cs_fmask_expand
[i
][j
]);
246 util_blitter_destroy(sctx
->blitter
);
248 /* Release DCC stats. */
249 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
250 assert(!sctx
->dcc_stats
[i
].query_active
);
252 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
253 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
254 sctx
->b
.destroy_query(&sctx
->b
,
255 sctx
->dcc_stats
[i
].ps_stats
[j
]);
257 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
260 if (sctx
->query_result_shader
)
261 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
262 if (sctx
->sh_query_result_shader
)
263 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->sh_query_result_shader
);
266 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
268 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
270 sctx
->ws
->ctx_destroy(sctx
->ctx
);
272 if (sctx
->b
.stream_uploader
)
273 u_upload_destroy(sctx
->b
.stream_uploader
);
274 if (sctx
->b
.const_uploader
)
275 u_upload_destroy(sctx
->b
.const_uploader
);
276 if (sctx
->cached_gtt_allocator
)
277 u_upload_destroy(sctx
->cached_gtt_allocator
);
279 slab_destroy_child(&sctx
->pool_transfers
);
280 slab_destroy_child(&sctx
->pool_transfers_unsync
);
282 if (sctx
->allocator_zeroed_memory
)
283 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
285 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
286 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
287 sctx
->ws
->fence_reference(&sctx
->last_ib_barrier_fence
, NULL
);
288 si_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
289 si_resource_reference(&sctx
->index_ring
, NULL
);
290 si_resource_reference(&sctx
->barrier_buf
, NULL
);
291 si_resource_reference(&sctx
->last_ib_barrier_buf
, NULL
);
292 pb_reference(&sctx
->gds
, NULL
);
293 pb_reference(&sctx
->gds_oa
, NULL
);
295 si_destroy_compiler(&sctx
->compiler
);
297 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
299 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
300 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
302 util_dynarray_fini(&sctx
->resident_tex_handles
);
303 util_dynarray_fini(&sctx
->resident_img_handles
);
304 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
305 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
306 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
307 si_unref_sdma_uploads(sctx
);
308 free(sctx
->sdma_uploads
);
312 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
314 struct si_context
*sctx
= (struct si_context
*)ctx
;
316 return sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
319 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
320 const struct pipe_device_reset_callback
*cb
)
322 struct si_context
*sctx
= (struct si_context
*)ctx
;
325 sctx
->device_reset_callback
= *cb
;
327 memset(&sctx
->device_reset_callback
, 0,
328 sizeof(sctx
->device_reset_callback
));
331 bool si_check_device_reset(struct si_context
*sctx
)
333 enum pipe_reset_status status
;
335 if (!sctx
->device_reset_callback
.reset
)
338 status
= sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
339 if (status
== PIPE_NO_RESET
)
342 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
346 /* Apitrace profiling:
347 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
348 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
349 * and remember its number.
350 * 3) In Mesa, enable queries and performance counters around that draw
351 * call and print the results.
352 * 4) glretrace --benchmark --markers ..
354 static void si_emit_string_marker(struct pipe_context
*ctx
,
355 const char *string
, int len
)
357 struct si_context
*sctx
= (struct si_context
*)ctx
;
359 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
362 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
365 static void si_set_debug_callback(struct pipe_context
*ctx
,
366 const struct pipe_debug_callback
*cb
)
368 struct si_context
*sctx
= (struct si_context
*)ctx
;
369 struct si_screen
*screen
= sctx
->screen
;
371 util_queue_finish(&screen
->shader_compiler_queue
);
372 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
377 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
380 static void si_set_log_context(struct pipe_context
*ctx
,
381 struct u_log_context
*log
)
383 struct si_context
*sctx
= (struct si_context
*)ctx
;
387 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
390 static void si_set_context_param(struct pipe_context
*ctx
,
391 enum pipe_context_param param
,
394 struct radeon_winsys
*ws
= ((struct si_context
*)ctx
)->ws
;
397 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
:
398 ws
->pin_threads_to_L3_cache(ws
, value
);
404 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
407 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
409 /* Don't create a context if it's not compute-only and hw is compute-only. */
410 if (!sscreen
->info
.has_graphics
&&
411 !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
414 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
415 struct radeon_winsys
*ws
= sscreen
->ws
;
417 bool stop_exec_on_failure
= (flags
& PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET
) != 0;
422 sctx
->has_graphics
= sscreen
->info
.chip_class
== GFX6
||
423 !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
);
425 if (flags
& PIPE_CONTEXT_DEBUG
)
426 sscreen
->record_llvm_ir
= true; /* racy but not critical */
428 sctx
->b
.screen
= screen
; /* this must be set first */
430 sctx
->b
.destroy
= si_destroy_context
;
431 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
432 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
434 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
435 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
437 sctx
->ws
= sscreen
->ws
;
438 sctx
->family
= sscreen
->info
.family
;
439 sctx
->chip_class
= sscreen
->info
.chip_class
;
441 if (sctx
->chip_class
== GFX7
||
442 sctx
->chip_class
== GFX8
||
443 sctx
->chip_class
== GFX9
) {
444 sctx
->eop_bug_scratch
= si_resource(
445 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
446 16 * sscreen
->info
.num_render_backends
));
447 if (!sctx
->eop_bug_scratch
)
451 /* Initialize context allocators. */
452 sctx
->allocator_zeroed_memory
=
453 u_suballocator_create(&sctx
->b
, 128 * 1024,
454 0, PIPE_USAGE_DEFAULT
,
455 SI_RESOURCE_FLAG_UNMAPPABLE
|
456 SI_RESOURCE_FLAG_CLEAR
, false);
457 if (!sctx
->allocator_zeroed_memory
)
460 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
461 0, PIPE_USAGE_STREAM
,
462 SI_RESOURCE_FLAG_READ_ONLY
);
463 if (!sctx
->b
.stream_uploader
)
466 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
467 0, PIPE_USAGE_STAGING
, 0);
468 if (!sctx
->cached_gtt_allocator
)
471 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
475 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
476 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
477 (void*)si_flush_dma_cs
,
478 sctx
, stop_exec_on_failure
);
481 bool use_sdma_upload
= sscreen
->info
.has_dedicated_vram
&& sctx
->dma_cs
;
482 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 256 * 1024,
483 0, PIPE_USAGE_DEFAULT
,
484 SI_RESOURCE_FLAG_32BIT
|
486 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA
: 0));
487 if (!sctx
->b
.const_uploader
)
491 u_upload_enable_flush_explicit(sctx
->b
.const_uploader
);
493 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
,
494 sctx
->has_graphics
? RING_GFX
: RING_COMPUTE
,
495 (void*)si_flush_gfx_cs
, sctx
, stop_exec_on_failure
);
498 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
499 sizeof(*sctx
->border_color_table
));
500 if (!sctx
->border_color_table
)
503 sctx
->border_color_buffer
= si_resource(
504 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
505 SI_MAX_BORDER_COLORS
*
506 sizeof(*sctx
->border_color_table
)));
507 if (!sctx
->border_color_buffer
)
510 sctx
->border_color_map
=
511 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
512 NULL
, PIPE_TRANSFER_WRITE
);
513 if (!sctx
->border_color_map
)
516 sctx
->ngg
= sscreen
->use_ngg
;
518 /* Initialize context functions used by graphics and compute. */
519 if (sctx
->chip_class
>= GFX10
)
520 sctx
->emit_cache_flush
= gfx10_emit_cache_flush
;
522 sctx
->emit_cache_flush
= si_emit_cache_flush
;
524 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
525 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
526 sctx
->b
.set_log_context
= si_set_log_context
;
527 sctx
->b
.set_context_param
= si_set_context_param
;
528 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
529 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
531 si_init_all_descriptors(sctx
);
532 si_init_buffer_functions(sctx
);
533 si_init_clear_functions(sctx
);
534 si_init_blit_functions(sctx
);
535 si_init_compute_functions(sctx
);
536 si_init_compute_blit_functions(sctx
);
537 si_init_debug_functions(sctx
);
538 si_init_fence_functions(sctx
);
539 si_init_query_functions(sctx
);
540 si_init_state_compute_functions(sctx
);
541 si_init_context_texture_functions(sctx
);
543 /* Initialize graphics-only context functions. */
544 if (sctx
->has_graphics
) {
545 if (sctx
->chip_class
>= GFX10
)
546 gfx10_init_query(sctx
);
547 si_init_msaa_functions(sctx
);
548 si_init_shader_functions(sctx
);
549 si_init_state_functions(sctx
);
550 si_init_streamout_functions(sctx
);
551 si_init_viewport_functions(sctx
);
553 sctx
->blitter
= util_blitter_create(&sctx
->b
);
554 if (sctx
->blitter
== NULL
)
556 sctx
->blitter
->skip_viewport_restore
= true;
558 /* Some states are expected to be always non-NULL. */
559 sctx
->noop_blend
= util_blitter_get_noop_blend_state(sctx
->blitter
);
560 sctx
->queued
.named
.blend
= sctx
->noop_blend
;
562 sctx
->noop_dsa
= util_blitter_get_noop_dsa_state(sctx
->blitter
);
563 sctx
->queued
.named
.dsa
= sctx
->noop_dsa
;
565 sctx
->discard_rasterizer_state
=
566 util_blitter_get_discard_rasterizer_state(sctx
->blitter
);
567 sctx
->queued
.named
.rasterizer
= sctx
->discard_rasterizer_state
;
569 si_init_draw_functions(sctx
);
570 si_initialize_prim_discard_tunables(sctx
);
573 /* Initialize SDMA functions. */
574 if (sctx
->chip_class
>= GFX7
)
575 cik_init_sdma_functions(sctx
);
577 si_init_dma_functions(sctx
);
579 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
580 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
582 sctx
->sample_mask
= 0xffff;
584 /* Initialize multimedia functions. */
585 if (sscreen
->info
.has_hw_decode
) {
586 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
587 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
589 sctx
->b
.create_video_codec
= vl_create_decoder
;
590 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
593 if (sctx
->chip_class
>= GFX9
) {
594 sctx
->wait_mem_scratch
= si_resource(
595 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 8));
596 if (!sctx
->wait_mem_scratch
)
599 /* Initialize the memory. */
600 si_cp_write_data(sctx
, sctx
->wait_mem_scratch
, 0, 4,
601 V_370_MEM
, V_370_ME
, &sctx
->wait_mem_number
);
604 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
605 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
606 if (sctx
->chip_class
== GFX7
) {
607 sctx
->null_const_buf
.buffer
=
608 pipe_aligned_buffer_create(screen
,
609 SI_RESOURCE_FLAG_32BIT
,
610 PIPE_USAGE_DEFAULT
, 16,
611 sctx
->screen
->info
.tcc_cache_line_size
);
612 if (!sctx
->null_const_buf
.buffer
)
614 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
616 unsigned start_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
617 for (shader
= start_shader
; shader
< SI_NUM_SHADERS
; shader
++) {
618 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
619 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
620 &sctx
->null_const_buf
);
624 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
625 &sctx
->null_const_buf
);
626 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
627 &sctx
->null_const_buf
);
628 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
629 &sctx
->null_const_buf
);
630 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
631 &sctx
->null_const_buf
);
632 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
633 &sctx
->null_const_buf
);
636 uint64_t max_threads_per_block
;
637 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
638 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
639 &max_threads_per_block
);
641 /* The maximum number of scratch waves. Scratch space isn't divided
642 * evenly between CUs. The number is only a function of the number of CUs.
643 * We can decrease the constant to decrease the scratch buffer size.
645 * sctx->scratch_waves must be >= the maximum posible size of
646 * 1 threadgroup, so that the hw doesn't hang from being unable
649 * The recommended value is 4 per CU at most. Higher numbers don't
650 * bring much benefit, but they still occupy chip resources (think
651 * async compute). I've seen ~2% performance difference between 4 and 32.
653 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
654 max_threads_per_block
/ 64);
656 si_init_compiler(sscreen
, &sctx
->compiler
);
658 /* Bindless handles. */
659 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
660 _mesa_key_pointer_equal
);
661 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
662 _mesa_key_pointer_equal
);
664 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
665 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
666 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
667 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
668 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
670 sctx
->sample_pos_buffer
=
671 pipe_buffer_create(sctx
->b
.screen
, 0, PIPE_USAGE_DEFAULT
,
672 sizeof(sctx
->sample_positions
));
673 pipe_buffer_write(&sctx
->b
, sctx
->sample_pos_buffer
, 0,
674 sizeof(sctx
->sample_positions
), &sctx
->sample_positions
);
676 /* this must be last */
677 si_begin_new_gfx_cs(sctx
);
679 if (sctx
->chip_class
== GFX7
) {
680 /* Clear the NULL constant buffer, because loads should return zeros.
681 * Note that this forces CP DMA to be used, because clover deadlocks
682 * for some reason when the compute codepath is used.
684 uint32_t clear_value
= 0;
685 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
686 sctx
->null_const_buf
.buffer
->width0
,
687 &clear_value
, 4, SI_COHERENCY_SHADER
, true);
691 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
692 si_destroy_context(&sctx
->b
);
696 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
697 void *priv
, unsigned flags
)
699 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
700 struct pipe_context
*ctx
;
702 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
703 flags
|= PIPE_CONTEXT_DEBUG
;
705 ctx
= si_create_context(screen
, flags
);
707 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
710 /* Clover (compute-only) is unsupported. */
711 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
714 /* When shaders are logged to stderr, asynchronous compilation is
716 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
719 /* Use asynchronous flushes only on amdgpu, since the radeon
720 * implementation for fence_server_sync is incomplete. */
721 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
722 si_replace_buffer_storage
,
723 sscreen
->info
.is_amdgpu
? si_create_fence
: NULL
,
724 &((struct si_context
*)ctx
)->tc
);
730 static void si_destroy_screen(struct pipe_screen
* pscreen
)
732 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
733 struct si_shader_part
*parts
[] = {
735 sscreen
->tcs_epilogs
,
742 if (!sscreen
->ws
->unref(sscreen
->ws
))
745 simple_mtx_destroy(&sscreen
->aux_context_lock
);
747 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
749 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
750 u_log_context_destroy(aux_log
);
754 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
756 util_queue_destroy(&sscreen
->shader_compiler_queue
);
757 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
759 /* Release the reference on glsl types of the compiler threads. */
760 glsl_type_singleton_decref();
762 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
763 si_destroy_compiler(&sscreen
->compiler
[i
]);
765 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
766 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
768 /* Free shader parts. */
769 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
771 struct si_shader_part
*part
= parts
[i
];
773 parts
[i
] = part
->next
;
774 si_shader_binary_clean(&part
->binary
);
778 simple_mtx_destroy(&sscreen
->shader_parts_mutex
);
779 si_destroy_shader_cache(sscreen
);
781 si_destroy_perfcounters(sscreen
);
782 si_gpu_load_kill_thread(sscreen
);
784 simple_mtx_destroy(&sscreen
->gpu_load_mutex
);
786 slab_destroy_parent(&sscreen
->pool_transfers
);
788 disk_cache_destroy(sscreen
->disk_shader_cache
);
789 sscreen
->ws
->destroy(sscreen
->ws
);
793 static void si_init_gs_info(struct si_screen
*sscreen
)
795 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
796 sscreen
->info
.family
);
799 static void si_test_vmfault(struct si_screen
*sscreen
)
801 struct pipe_context
*ctx
= sscreen
->aux_context
;
802 struct si_context
*sctx
= (struct si_context
*)ctx
;
803 struct pipe_resource
*buf
=
804 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
807 puts("Buffer allocation failed.");
811 si_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
813 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
814 si_cp_dma_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0,
815 SI_COHERENCY_NONE
, L2_BYPASS
);
816 ctx
->flush(ctx
, NULL
, 0);
817 puts("VM fault test: CP - done.");
819 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
820 si_sdma_clear_buffer(sctx
, buf
, 0, 4, 0);
821 ctx
->flush(ctx
, NULL
, 0);
822 puts("VM fault test: SDMA - done.");
824 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
825 util_test_constant_buffer(ctx
, buf
);
826 puts("VM fault test: Shader - done.");
831 static void si_test_gds_memory_management(struct si_context
*sctx
,
832 unsigned alloc_size
, unsigned alignment
,
833 enum radeon_bo_domain domain
)
835 struct radeon_winsys
*ws
= sctx
->ws
;
836 struct radeon_cmdbuf
*cs
[8];
837 struct pb_buffer
*gds_bo
[ARRAY_SIZE(cs
)];
839 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
840 cs
[i
] = ws
->cs_create(sctx
->ctx
, RING_COMPUTE
,
842 gds_bo
[i
] = ws
->buffer_create(ws
, alloc_size
, alignment
, domain
, 0);
846 for (unsigned iterations
= 0; iterations
< 20000; iterations
++) {
847 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
848 /* This clears GDS with CP DMA.
850 * We don't care if GDS is present. Just add some packet
851 * to make the GPU busy for a moment.
853 si_cp_dma_clear_buffer(sctx
, cs
[i
], NULL
, 0, alloc_size
, 0,
854 SI_CPDMA_SKIP_BO_LIST_UPDATE
|
855 SI_CPDMA_SKIP_CHECK_CS_SPACE
|
856 SI_CPDMA_SKIP_GFX_SYNC
, 0, 0);
858 ws
->cs_add_buffer(cs
[i
], gds_bo
[i
], domain
,
859 RADEON_USAGE_READWRITE
, 0);
860 ws
->cs_flush(cs
[i
], PIPE_FLUSH_ASYNC
, NULL
);
866 static void si_disk_cache_create(struct si_screen
*sscreen
)
868 /* Don't use the cache if shader dumping is enabled. */
869 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
872 struct mesa_sha1 ctx
;
873 unsigned char sha1
[20];
874 char cache_id
[20 * 2 + 1];
876 _mesa_sha1_init(&ctx
);
878 if (!disk_cache_get_function_identifier(si_disk_cache_create
, &ctx
) ||
879 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
,
883 _mesa_sha1_final(&ctx
, sha1
);
884 disk_cache_format_hex_id(cache_id
, sha1
, 20 * 2);
886 /* These flags affect shader compilation. */
887 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
888 uint64_t shader_debug_flags
= sscreen
->debug_flags
& ALL_FLAGS
;
890 /* Add the high bits of 32-bit addresses, which affects
891 * how 32-bit addresses are expanded to 64 bits.
893 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
894 assert((int16_t)sscreen
->info
.address32_hi
== (int32_t)sscreen
->info
.address32_hi
);
895 shader_debug_flags
|= (uint64_t)(sscreen
->info
.address32_hi
& 0xffff) << 32;
897 sscreen
->disk_shader_cache
=
898 disk_cache_create(sscreen
->info
.name
,
903 static void si_set_max_shader_compiler_threads(struct pipe_screen
*screen
,
904 unsigned max_threads
)
906 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
908 /* This function doesn't allow a greater number of threads than
909 * the queue had at its creation. */
910 util_queue_adjust_num_threads(&sscreen
->shader_compiler_queue
,
912 /* Don't change the number of threads on the low priority queue. */
915 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen
*screen
,
917 enum pipe_shader_type shader_type
)
919 struct si_shader_selector
*sel
= (struct si_shader_selector
*)shader
;
921 return util_queue_fence_is_signalled(&sel
->ready
);
924 static struct pipe_screen
*
925 radeonsi_screen_create_impl(struct radeon_winsys
*ws
,
926 const struct pipe_screen_config
*config
)
928 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
929 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
, i
;
936 ws
->query_info(ws
, &sscreen
->info
);
938 if (sscreen
->info
.chip_class
== GFX10
&& LLVM_VERSION_MAJOR
< 9) {
939 fprintf(stderr
, "radeonsi: Navi family support requires LLVM 9 or higher\n");
944 if (sscreen
->info
.chip_class
>= GFX9
) {
945 sscreen
->se_tile_repeat
= 32 * sscreen
->info
.max_se
;
947 ac_get_raster_config(&sscreen
->info
,
948 &sscreen
->pa_sc_raster_config
,
949 &sscreen
->pa_sc_raster_config_1
,
950 &sscreen
->se_tile_repeat
);
953 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
955 sscreen
->debug_flags
|= debug_get_flags_option("AMD_DEBUG",
958 if (sscreen
->debug_flags
& DBG(NO_GFX
))
959 sscreen
->info
.has_graphics
= false;
961 /* Set functions first. */
962 sscreen
->b
.context_create
= si_pipe_create_context
;
963 sscreen
->b
.destroy
= si_destroy_screen
;
964 sscreen
->b
.set_max_shader_compiler_threads
=
965 si_set_max_shader_compiler_threads
;
966 sscreen
->b
.is_parallel_shader_compilation_finished
=
967 si_is_parallel_shader_compilation_finished
;
969 si_init_screen_get_functions(sscreen
);
970 si_init_screen_buffer_functions(sscreen
);
971 si_init_screen_fence_functions(sscreen
);
972 si_init_screen_state_functions(sscreen
);
973 si_init_screen_texture_functions(sscreen
);
974 si_init_screen_query_functions(sscreen
);
976 /* Set these flags in debug_flags early, so that the shader cache takes
979 if (driQueryOptionb(config
->options
,
980 "glsl_correct_derivatives_after_discard"))
981 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
982 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
983 sscreen
->debug_flags
|= DBG(SI_SCHED
);
985 if (sscreen
->debug_flags
& DBG(INFO
))
986 ac_print_gpu_info(&sscreen
->info
);
988 slab_create_parent(&sscreen
->pool_transfers
,
989 sizeof(struct si_transfer
), 64);
991 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
992 if (sscreen
->force_aniso
== -1) {
993 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
996 if (sscreen
->force_aniso
>= 0) {
997 printf("radeonsi: Forcing anisotropy filter to %ix\n",
998 /* round down to a power of two */
999 1 << util_logbase2(sscreen
->force_aniso
));
1002 (void) simple_mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
1003 (void) simple_mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
1005 si_init_gs_info(sscreen
);
1006 if (!si_init_shader_cache(sscreen
)) {
1011 si_disk_cache_create(sscreen
);
1013 /* Determine the number of shader compiler threads. */
1014 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
1016 if (hw_threads
>= 12) {
1017 num_comp_hi_threads
= hw_threads
* 3 / 4;
1018 num_comp_lo_threads
= hw_threads
/ 3;
1019 } else if (hw_threads
>= 6) {
1020 num_comp_hi_threads
= hw_threads
- 2;
1021 num_comp_lo_threads
= hw_threads
/ 2;
1022 } else if (hw_threads
>= 2) {
1023 num_comp_hi_threads
= hw_threads
- 1;
1024 num_comp_lo_threads
= hw_threads
/ 2;
1026 num_comp_hi_threads
= 1;
1027 num_comp_lo_threads
= 1;
1030 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
1031 ARRAY_SIZE(sscreen
->compiler
));
1032 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
1033 ARRAY_SIZE(sscreen
->compiler_lowp
));
1035 /* Take a reference on the glsl types for the compiler threads. */
1036 glsl_type_singleton_init_or_ref();
1038 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "sh",
1039 64, num_comp_hi_threads
,
1040 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1041 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
)) {
1042 si_destroy_shader_cache(sscreen
);
1044 glsl_type_singleton_decref();
1048 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
1050 64, num_comp_lo_threads
,
1051 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1052 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
|
1053 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
1054 si_destroy_shader_cache(sscreen
);
1056 glsl_type_singleton_decref();
1060 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1061 si_init_perfcounters(sscreen
);
1063 /* Determine tessellation ring info. */
1064 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= GFX7
&&
1065 sscreen
->info
.family
!= CHIP_CARRIZO
&&
1066 sscreen
->info
.family
!= CHIP_STONEY
;
1067 /* This must be one less than the maximum number due to a hw limitation.
1068 * Various hardware bugs need this.
1070 unsigned max_offchip_buffers_per_se
;
1072 if (sscreen
->info
.chip_class
>= GFX10
)
1073 max_offchip_buffers_per_se
= 256;
1074 /* Only certain chips can use the maximum value. */
1075 else if (sscreen
->info
.family
== CHIP_VEGA12
||
1076 sscreen
->info
.family
== CHIP_VEGA20
)
1077 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1079 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
1081 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1082 sscreen
->info
.max_se
;
1083 unsigned offchip_granularity
;
1085 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1086 * around by setting 4K granularity.
1088 if (sscreen
->info
.family
== CHIP_HAWAII
) {
1089 sscreen
->tess_offchip_block_dw_size
= 4096;
1090 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1092 sscreen
->tess_offchip_block_dw_size
= 8192;
1093 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1096 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
1097 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
1098 sscreen
->tess_offchip_block_dw_size
* 4;
1100 if (sscreen
->info
.chip_class
>= GFX7
) {
1101 if (sscreen
->info
.chip_class
>= GFX8
)
1102 --max_offchip_buffers
;
1103 sscreen
->vgt_hs_offchip_param
=
1104 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1105 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1107 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
1108 sscreen
->vgt_hs_offchip_param
=
1109 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1112 sscreen
->has_draw_indirect_multi
=
1113 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
1114 (sscreen
->info
.chip_class
== GFX8
&&
1115 sscreen
->info
.pfp_fw_version
>= 121 &&
1116 sscreen
->info
.me_fw_version
>= 87) ||
1117 (sscreen
->info
.chip_class
== GFX7
&&
1118 sscreen
->info
.pfp_fw_version
>= 211 &&
1119 sscreen
->info
.me_fw_version
>= 173) ||
1120 (sscreen
->info
.chip_class
== GFX6
&&
1121 sscreen
->info
.pfp_fw_version
>= 79 &&
1122 sscreen
->info
.me_fw_version
>= 142);
1124 sscreen
->has_out_of_order_rast
= sscreen
->info
.has_out_of_order_rast
&&
1125 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
1126 sscreen
->assume_no_z_fights
=
1127 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
1128 sscreen
->commutative_blend_add
=
1129 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
1132 #define OPT_BOOL(name, dflt, description) \
1133 sscreen->options.name = \
1134 driQueryOptionb(config->options, "radeonsi_"#name);
1135 #include "si_debug_options.h"
1138 sscreen
->use_ngg
= sscreen
->info
.chip_class
>= GFX10
&&
1139 sscreen
->info
.family
!= CHIP_NAVI14
&&
1140 !(sscreen
->debug_flags
& DBG(NO_NGG
));
1141 sscreen
->use_ngg_streamout
= false;
1143 /* Only enable primitive binning on APUs by default. */
1144 if (sscreen
->info
.chip_class
>= GFX10
) {
1145 sscreen
->dpbb_allowed
= true;
1146 sscreen
->dfsm_allowed
= !sscreen
->info
.has_dedicated_vram
;
1147 } else if (sscreen
->info
.chip_class
== GFX9
) {
1148 sscreen
->dpbb_allowed
= !sscreen
->info
.has_dedicated_vram
;
1149 sscreen
->dfsm_allowed
= !sscreen
->info
.has_dedicated_vram
;
1152 /* Process DPBB enable flags. */
1153 if (sscreen
->debug_flags
& DBG(DPBB
)) {
1154 sscreen
->dpbb_allowed
= true;
1155 if (sscreen
->debug_flags
& DBG(DFSM
))
1156 sscreen
->dfsm_allowed
= true;
1159 /* Process DPBB disable flags. */
1160 if (sscreen
->debug_flags
& DBG(NO_DPBB
)) {
1161 sscreen
->dpbb_allowed
= false;
1162 sscreen
->dfsm_allowed
= false;
1163 } else if (sscreen
->debug_flags
& DBG(NO_DFSM
)) {
1164 sscreen
->dfsm_allowed
= false;
1167 /* While it would be nice not to have this flag, we are constrained
1168 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1170 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
!= GFX9
;
1172 sscreen
->dcc_msaa_allowed
=
1173 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1175 (void) simple_mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1176 sscreen
->use_monolithic_shaders
=
1177 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1179 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SCACHE
|
1180 SI_CONTEXT_INV_VCACHE
;
1181 if (sscreen
->info
.chip_class
<= GFX8
) {
1182 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_L2
;
1183 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WB_L2
;
1186 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1187 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1194 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1196 * s >= z >= c (ignoring this only wastes memory)
1201 * Only MSAA color and depth buffers are overriden.
1203 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1204 const char *eqaa
= debug_get_option("EQAA", NULL
);
1207 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1208 sscreen
->eqaa_force_coverage_samples
= s
;
1209 sscreen
->eqaa_force_z_samples
= z
;
1210 sscreen
->eqaa_force_color_samples
= f
;
1214 for (i
= 0; i
< num_comp_hi_threads
; i
++)
1215 si_init_compiler(sscreen
, &sscreen
->compiler
[i
]);
1216 for (i
= 0; i
< num_comp_lo_threads
; i
++)
1217 si_init_compiler(sscreen
, &sscreen
->compiler_lowp
[i
]);
1219 sscreen
->ge_wave_size
= 64;
1220 sscreen
->ps_wave_size
= 64;
1221 sscreen
->compute_wave_size
= 64;
1223 if (sscreen
->info
.chip_class
>= GFX10
) {
1224 /* Pixels shaders: Wave64 is recommended.
1225 * Compute shaders: There are piglit failures with Wave32.
1227 sscreen
->ge_wave_size
= 32;
1229 if (sscreen
->debug_flags
& DBG(W32_GE
))
1230 sscreen
->ge_wave_size
= 32;
1231 if (sscreen
->debug_flags
& DBG(W32_PS
))
1232 sscreen
->ps_wave_size
= 32;
1233 if (sscreen
->debug_flags
& DBG(W32_CS
))
1234 sscreen
->compute_wave_size
= 32;
1236 if (sscreen
->debug_flags
& DBG(W64_GE
))
1237 sscreen
->ge_wave_size
= 64;
1238 if (sscreen
->debug_flags
& DBG(W64_PS
))
1239 sscreen
->ps_wave_size
= 64;
1240 if (sscreen
->debug_flags
& DBG(W64_CS
))
1241 sscreen
->compute_wave_size
= 64;
1244 /* Create the auxiliary context. This must be done last. */
1245 sscreen
->aux_context
= si_create_context(&sscreen
->b
,
1246 (sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0) |
1247 (sscreen
->info
.has_graphics
? 0 : PIPE_CONTEXT_COMPUTE_ONLY
));
1248 if (sscreen
->options
.aux_debug
) {
1249 struct u_log_context
*log
= CALLOC_STRUCT(u_log_context
);
1250 u_log_context_init(log
);
1251 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, log
);
1254 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1255 si_test_dma(sscreen
);
1257 if (sscreen
->debug_flags
& DBG(TEST_DMA_PERF
)) {
1258 si_test_dma_perf(sscreen
);
1261 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1262 DBG(TEST_VMFAULT_SDMA
) |
1263 DBG(TEST_VMFAULT_SHADER
)))
1264 si_test_vmfault(sscreen
);
1266 if (sscreen
->debug_flags
& DBG(TEST_GDS
))
1267 si_test_gds((struct si_context
*)sscreen
->aux_context
);
1269 if (sscreen
->debug_flags
& DBG(TEST_GDS_MM
)) {
1270 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1271 32 * 1024, 4, RADEON_DOMAIN_GDS
);
1273 if (sscreen
->debug_flags
& DBG(TEST_GDS_OA_MM
)) {
1274 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1275 4, 1, RADEON_DOMAIN_OA
);
1281 struct pipe_screen
*radeonsi_screen_create(int fd
, const struct pipe_screen_config
*config
)
1283 drmVersionPtr version
= drmGetVersion(fd
);
1284 struct radeon_winsys
*rw
= NULL
;
1286 switch (version
->version_major
) {
1288 rw
= radeon_drm_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1291 rw
= amdgpu_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1295 drmFreeVersion(version
);
1296 return rw
? rw
->screen
: NULL
;