src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39
  40         si_release_all_descriptors(sctx);
  41
  42         pipe_resource_reference(&sctx->esgs_ring, NULL);
  43         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  44         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  45         r600_resource_reference(&sctx->border_color_table, NULL);
  46         r600_resource_reference(&sctx->scratch_buffer, NULL);
  47         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  48
  49         si_pm4_free_state(sctx, sctx->init_config, ~0);
  50         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  51         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  52         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  53
  54         if (sctx->pstipple_sampler_state)
  55                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  56         if (sctx->dummy_pixel_shader) {
  57                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  58         }
  59         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  60         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  61         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  62         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  63         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  64
  65         util_blitter_destroy(sctx->blitter);
  66
  67         si_pm4_cleanup(sctx);
  68
  69         r600_common_context_cleanup(&sctx->b);
  70
  71 #if HAVE_LLVM >= 0x0306
  72         LLVMDisposeTargetMachine(sctx->tm);
  73 #endif
  74
  75         FREE(sctx);
  76 }
  77
  78 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  79 {
  80         struct si_context *sctx = CALLOC_STRUCT(si_context);
  81         struct si_screen* sscreen = (struct si_screen *)screen;
  82         struct radeon_winsys *ws = sscreen->b.ws;
  83         LLVMTargetRef r600_target;
  84 #if HAVE_LLVM >= 0x0306
  85         const char *triple = "amdgcn--";
  86 #endif
  87         int shader, i;
  88
  89         if (sctx == NULL)
  90                 return NULL;
  91
  92         sctx->b.b.screen = screen; /* this must be set first */
  93         sctx->b.b.priv = priv;
  94         sctx->b.b.destroy = si_destroy_context;
  95         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
  96
  97         if (!r600_common_context_init(&sctx->b, &sscreen->b))
  98                 goto fail;
  99
 100         si_init_blit_functions(sctx);
 101         si_init_compute_functions(sctx);
 102
 103         if (sscreen->b.info.has_uvd) {
 104                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 105                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 106         } else {
 107                 sctx->b.b.create_video_codec = vl_create_decoder;
 108                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 109         }
 110
 111         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
 112                                              sctx, sscreen->b.trace_bo ?
 113                                                 sscreen->b.trace_bo->cs_buf : NULL);
 114         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 115
 116         si_init_all_descriptors(sctx);
 117
 118         /* Initialize cache_flush. */
 119         sctx->cache_flush = si_atom_cache_flush;
 120         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 121
 122         sctx->msaa_sample_locs = si_atom_msaa_sample_locs;
 123         sctx->atoms.s.msaa_sample_locs = &sctx->msaa_sample_locs;
 124
 125         sctx->msaa_config = si_atom_msaa_config;
 126         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 127
 128         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 129         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 130
 131         si_init_state_functions(sctx);
 132         si_init_shader_functions(sctx);
 133
 134         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 135                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 136
 137         sctx->blitter = util_blitter_create(&sctx->b.b);
 138         if (sctx->blitter == NULL)
 139                 goto fail;
 140         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 141
 142         /* these must be last */
 143         si_begin_new_cs(sctx);
 144         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 145
 146         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 147          * with a NULL buffer). We need to use a dummy buffer instead. */
 148         if (sctx->b.chip_class == CIK) {
 149                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 150                                                                  PIPE_USAGE_DEFAULT, 16);
 151                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 152
 153                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 154                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 155                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 156                                                               &sctx->null_const_buf);
 157                         }
 158                 }
 159
 160                 /* Clear the NULL constant buffer, because loads should return zeros. */
 161                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 162                                      sctx->null_const_buf.buffer->width0, 0, false);
 163         }
 164
 165         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 166          * this for non-cs shaders.  Using the wrong value here can result in
 167          * GPU lockups, but the maximum value seems to always work.
 168          */
 169         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 170
 171 #if HAVE_LLVM >= 0x0306
 172         /* Initialize LLVM TargetMachine */
 173         r600_target = radeon_llvm_get_r600_target(triple);
 174         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 175                                            r600_get_llvm_processor_name(sscreen->b.family),
 176                                            "+DumpCode,+vgpr-spilling",
 177                                            LLVMCodeGenLevelDefault,
 178                                            LLVMRelocDefault,
 179                                            LLVMCodeModelDefault);
 180 #endif
 181
 182         return &sctx->b.b;
 183 fail:
 184         si_destroy_context(&sctx->b.b);
 185         return NULL;
 186 }
 187
 188 /*
 189  * pipe_screen
 190  */
 191
 192 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 193 {
 194         struct si_screen *sscreen = (struct si_screen *)pscreen;
 195
 196         switch (param) {
 197         /* Supported features (boolean caps). */
 198         case PIPE_CAP_TWO_SIDED_STENCIL:
 199         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 200         case PIPE_CAP_ANISOTROPIC_FILTER:
 201         case PIPE_CAP_POINT_SPRITE:
 202         case PIPE_CAP_OCCLUSION_QUERY:
 203         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 204         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 205         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 206         case PIPE_CAP_TEXTURE_SWIZZLE:
 207         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 208         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 209         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 210         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 211         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 212         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 213         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 214         case PIPE_CAP_SM3:
 215         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 216         case PIPE_CAP_PRIMITIVE_RESTART:
 217         case PIPE_CAP_CONDITIONAL_RENDER:
 218         case PIPE_CAP_TEXTURE_BARRIER:
 219         case PIPE_CAP_INDEP_BLEND_ENABLE:
 220         case PIPE_CAP_INDEP_BLEND_FUNC:
 221         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 222         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 223         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 224         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 225         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 226         case PIPE_CAP_USER_INDEX_BUFFERS:
 227         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 228         case PIPE_CAP_START_INSTANCE:
 229         case PIPE_CAP_NPOT_TEXTURES:
 230         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 231         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 232         case PIPE_CAP_TGSI_INSTANCEID:
 233         case PIPE_CAP_COMPUTE:
 234         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 235         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 236         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 237         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 238         case PIPE_CAP_CUBE_MAP_ARRAY:
 239         case PIPE_CAP_SAMPLE_SHADING:
 240         case PIPE_CAP_DRAW_INDIRECT:
 241         case PIPE_CAP_CLIP_HALFZ:
 242         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 243         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 244         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 245         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 246         case PIPE_CAP_TGSI_TEXCOORD:
 247                 return 1;
 248
 249         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 250                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 251
 252         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 253                 return sscreen->b.info.drm_major == 2 && sscreen->b.info.drm_minor >= 43;
 254
 255         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 256                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 257                 return sscreen->b.chip_class < CIK ||
 258                        sscreen->b.info.drm_minor >= 35;
 259
 260         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 261                 return R600_MAP_BUFFER_ALIGNMENT;
 262
 263         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 264         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 265                 return 4;
 266
 267         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 268                 return 330;
 269
 270         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 271                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 272
 273         case PIPE_CAP_TEXTURE_QUERY_LOD:
 274         case PIPE_CAP_TEXTURE_GATHER_SM5:
 275                 return HAVE_LLVM >= 0x0305;
 276         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 277                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 278
 279         /* Unsupported features. */
 280         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 281         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 282         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 283         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 284         case PIPE_CAP_USER_VERTEX_BUFFERS:
 285         case PIPE_CAP_FAKE_SW_MSAA:
 286         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 287         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 288         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 289         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 290         case PIPE_CAP_VERTEXID_NOBASE:
 291         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 292                 return 0;
 293
 294         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 295                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 296
 297         /* Stream output. */
 298         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 299                 return sscreen->b.has_streamout ? 4 : 0;
 300         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 301                 return sscreen->b.has_streamout ? 1 : 0;
 302         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 303         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 304                 return sscreen->b.has_streamout ? 32*4 : 0;
 305
 306         /* Geometry shader output. */
 307         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 308                 return 1024;
 309         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 310                 return 4095;
 311         case PIPE_CAP_MAX_VERTEX_STREAMS:
 312                 return 1;
 313
 314         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 315                 return 2048;
 316
 317         /* Texturing. */
 318         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 319         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 320                 return 15; /* 16384 */
 321         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 322                 /* textures support 8192, but layered rendering supports 2048 */
 323                 return 12;
 324         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 325                 /* textures support 8192, but layered rendering supports 2048 */
 326                 return 2048;
 327
 328         /* Render targets. */
 329         case PIPE_CAP_MAX_RENDER_TARGETS:
 330                 return 8;
 331
 332         case PIPE_CAP_MAX_VIEWPORTS:
 333                 return 16;
 334
 335         /* Timer queries, present when the clock frequency is non zero. */
 336         case PIPE_CAP_QUERY_TIMESTAMP:
 337         case PIPE_CAP_QUERY_TIME_ELAPSED:
 338                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 339
 340         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 341         case PIPE_CAP_MIN_TEXEL_OFFSET:
 342                 return -32;
 343
 344         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 345         case PIPE_CAP_MAX_TEXEL_OFFSET:
 346                 return 31;
 347
 348         case PIPE_CAP_ENDIANNESS:
 349                 return PIPE_ENDIAN_LITTLE;
 350
 351         case PIPE_CAP_VENDOR_ID:
 352                 return 0x1002;
 353         case PIPE_CAP_DEVICE_ID:
 354                 return sscreen->b.info.pci_id;
 355         case PIPE_CAP_ACCELERATED:
 356                 return 1;
 357         case PIPE_CAP_VIDEO_MEMORY:
 358                 return sscreen->b.info.vram_size >> 20;
 359         case PIPE_CAP_UMA:
 360                 return 0;
 361         }
 362         return 0;
 363 }
 364
 365 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 366 {
 367         switch(shader)
 368         {
 369         case PIPE_SHADER_FRAGMENT:
 370         case PIPE_SHADER_VERTEX:
 371         case PIPE_SHADER_GEOMETRY:
 372                 break;
 373         case PIPE_SHADER_COMPUTE:
 374                 switch (param) {
 375                 case PIPE_SHADER_CAP_PREFERRED_IR:
 376 #if HAVE_LLVM < 0x0306
 377                         return PIPE_SHADER_IR_LLVM;
 378 #else
 379                         return PIPE_SHADER_IR_NATIVE;
 380 #endif
 381                 case PIPE_SHADER_CAP_DOUBLES:
 382                         return HAVE_LLVM >= 0x0307;
 383
 384                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 385                         uint64_t max_const_buffer_size;
 386                         pscreen->get_compute_param(pscreen,
 387                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 388                                 &max_const_buffer_size);
 389                         return max_const_buffer_size;
 390                 }
 391                 default:
 392                         /* If compute shaders don't require a special value
 393                          * for this cap, we can return the same value we
 394                          * do for other shader types. */
 395                         break;
 396                 }
 397                 break;
 398         default:
 399                 /* TODO: support tessellation */
 400                 return 0;
 401         }
 402
 403         switch (param) {
 404         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 405         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 406         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 407         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 408                 return 16384;
 409         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 410                 return 32;
 411         case PIPE_SHADER_CAP_MAX_INPUTS:
 412                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 413         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 414                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 415         case PIPE_SHADER_CAP_MAX_TEMPS:
 416                 return 256; /* Max native temporaries. */
 417         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 418                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 419         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 420                 return SI_NUM_USER_CONST_BUFFERS;
 421         case PIPE_SHADER_CAP_MAX_PREDS:
 422                 return 0; /* FIXME */
 423         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 424                 return 1;
 425         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 426                 return 1;
 427         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 428                 /* Indirection of geometry shader input dimension is not
 429                  * handled yet
 430                  */
 431                 return shader < PIPE_SHADER_GEOMETRY;
 432         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 433         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 434         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 435                 return 1;
 436         case PIPE_SHADER_CAP_INTEGERS:
 437                 return 1;
 438         case PIPE_SHADER_CAP_SUBROUTINES:
 439                 return 0;
 440         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 441         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 442                 return 16;
 443         case PIPE_SHADER_CAP_PREFERRED_IR:
 444                 return PIPE_SHADER_IR_TGSI;
 445         case PIPE_SHADER_CAP_DOUBLES:
 446                 return HAVE_LLVM >= 0x0307;
 447         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 448         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 449                 return 0;
 450         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 451         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 452                 return 1;
 453         }
 454         return 0;
 455 }
 456
 457 static void si_destroy_screen(struct pipe_screen* pscreen)
 458 {
 459         struct si_screen *sscreen = (struct si_screen *)pscreen;
 460
 461         if (sscreen == NULL)
 462                 return;
 463
 464         if (!sscreen->b.ws->unref(sscreen->b.ws))
 465                 return;
 466
 467         r600_destroy_common_screen(&sscreen->b);
 468 }
 469
 470 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 471
 472 /* Initialize pipe config. This is especially important for GPUs
 473  * with 16 pipes and more where it's initialized incorrectly by
 474  * the TILING_CONFIG ioctl. */
 475 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 476 {
 477         unsigned mode2d;
 478
 479         /* This is okay, because there can be no 2D tiling without
 480          * the tile mode array, so we won't need the pipe config.
 481          * Return "success".
 482          */
 483         if (!sscreen->b.info.si_tile_mode_array_valid)
 484                 return true;
 485
 486         /* The same index is used for the 2D mode on CIK too. */
 487         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 488
 489         switch (G_009910_PIPE_CONFIG(mode2d)) {
 490         case V_02803C_ADDR_SURF_P2:
 491                 sscreen->b.tiling_info.num_channels = 2;
 492                 break;
 493         case V_02803C_X_ADDR_SURF_P4_8X16:
 494         case V_02803C_X_ADDR_SURF_P4_16X16:
 495         case V_02803C_X_ADDR_SURF_P4_16X32:
 496         case V_02803C_X_ADDR_SURF_P4_32X32:
 497                 sscreen->b.tiling_info.num_channels = 4;
 498                 break;
 499         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 500         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 501         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 502         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 503         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 504         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 505         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 506                 sscreen->b.tiling_info.num_channels = 8;
 507                 break;
 508         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 509         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 510                 sscreen->b.tiling_info.num_channels = 16;
 511                 break;
 512         default:
 513                 assert(0);
 514                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 515                         G_009910_PIPE_CONFIG(mode2d));
 516                 return false;
 517         }
 518         return true;
 519 }
 520
 521 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 522 {
 523         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 524
 525         if (sscreen == NULL) {
 526                 return NULL;
 527         }
 528
 529         /* Set functions first. */
 530         sscreen->b.b.context_create = si_create_context;
 531         sscreen->b.b.destroy = si_destroy_screen;
 532         sscreen->b.b.get_param = si_get_param;
 533         sscreen->b.b.get_shader_param = si_get_shader_param;
 534         sscreen->b.b.is_format_supported = si_is_format_supported;
 535         sscreen->b.b.resource_create = r600_resource_create_common;
 536
 537         if (!r600_common_screen_init(&sscreen->b, ws) ||
 538             !si_initialize_pipe_config(sscreen)) {
 539                 FREE(sscreen);
 540                 return NULL;
 541         }
 542
 543         sscreen->b.has_cp_dma = true;
 544         sscreen->b.has_streamout = true;
 545
 546         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 547                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 548
 549         /* Create the auxiliary context. This must be done last. */
 550         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 551
 552         return &sscreen->b.b;
 553 }