2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
28 #include "radeon/radeon_llvm_emit.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/u_memory.h"
31 #include "vl/vl_decoder.h"
36 static void si_destroy_context(struct pipe_context
*context
)
38 struct si_context
*sctx
= (struct si_context
*)context
;
41 si_release_all_descriptors(sctx
);
43 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
44 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
45 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
46 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
47 r600_resource_reference(&sctx
->border_color_table
, NULL
);
48 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
49 sctx
->b
.ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
51 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
52 si_pm4_delete_state(sctx
, gs_rings
, sctx
->gs_rings
);
53 si_pm4_delete_state(sctx
, tf_ring
, sctx
->tf_state
);
54 for (i
= 0; i
< Elements(sctx
->vgt_shader_config
); i
++)
55 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
57 if (sctx
->pstipple_sampler_state
)
58 sctx
->b
.b
.delete_sampler_state(&sctx
->b
.b
, sctx
->pstipple_sampler_state
);
59 if (sctx
->dummy_pixel_shader
)
60 sctx
->b
.b
.delete_fs_state(&sctx
->b
.b
, sctx
->dummy_pixel_shader
);
61 if (sctx
->fixed_func_tcs_shader
)
62 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
);
63 if (sctx
->custom_dsa_flush
)
64 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
65 if (sctx
->custom_blend_resolve
)
66 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
67 if (sctx
->custom_blend_decompress
)
68 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
69 if (sctx
->custom_blend_fastclear
)
70 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fastclear
);
71 util_unreference_framebuffer_state(&sctx
->framebuffer
.state
);
74 util_blitter_destroy(sctx
->blitter
);
78 r600_common_context_cleanup(&sctx
->b
);
80 #if HAVE_LLVM >= 0x0306
81 LLVMDisposeTargetMachine(sctx
->tm
);
87 static enum pipe_reset_status
88 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
90 struct si_context
*sctx
= (struct si_context
*)ctx
;
92 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
95 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
96 void *priv
, unsigned flags
)
98 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
99 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
100 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
101 LLVMTargetRef r600_target
;
102 #if HAVE_LLVM >= 0x0306
103 const char *triple
= "amdgcn--";
110 sctx
->b
.b
.screen
= screen
; /* this must be set first */
111 sctx
->b
.b
.priv
= priv
;
112 sctx
->b
.b
.destroy
= si_destroy_context
;
113 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
114 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
116 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
))
119 if (sscreen
->b
.info
.drm_major
== 3)
120 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
122 si_init_blit_functions(sctx
);
123 si_init_compute_functions(sctx
);
124 si_init_cp_dma_functions(sctx
);
126 if (sscreen
->b
.info
.has_uvd
) {
127 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
128 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
130 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
131 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
134 sctx
->b
.rings
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
, si_context_gfx_flush
,
135 sctx
, sscreen
->b
.trace_bo
?
136 sscreen
->b
.trace_bo
->cs_buf
: NULL
);
137 sctx
->b
.rings
.gfx
.flush
= si_context_gfx_flush
;
139 si_init_all_descriptors(sctx
);
141 /* Initialize cache_flush. */
142 sctx
->cache_flush
= si_atom_cache_flush
;
143 sctx
->atoms
.s
.cache_flush
= &sctx
->cache_flush
;
145 sctx
->msaa_sample_locs
= si_atom_msaa_sample_locs
;
146 sctx
->atoms
.s
.msaa_sample_locs
= &sctx
->msaa_sample_locs
;
148 sctx
->msaa_config
= si_atom_msaa_config
;
149 sctx
->atoms
.s
.msaa_config
= &sctx
->msaa_config
;
151 sctx
->atoms
.s
.streamout_begin
= &sctx
->b
.streamout
.begin_atom
;
152 sctx
->atoms
.s
.streamout_enable
= &sctx
->b
.streamout
.enable_atom
;
154 si_init_state_functions(sctx
);
155 si_init_shader_functions(sctx
);
157 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
158 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
160 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
161 if (sctx
->blitter
== NULL
)
163 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
165 /* these must be last */
166 si_begin_new_cs(sctx
);
167 r600_query_init_backend_mask(&sctx
->b
); /* this emits commands and must be last */
169 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
170 * with a NULL buffer). We need to use a dummy buffer instead. */
171 if (sctx
->b
.chip_class
== CIK
) {
172 sctx
->null_const_buf
.buffer
= pipe_buffer_create(screen
, PIPE_BIND_CONSTANT_BUFFER
,
173 PIPE_USAGE_DEFAULT
, 16);
174 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
176 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
177 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
178 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
179 &sctx
->null_const_buf
);
183 /* Clear the NULL constant buffer, because loads should return zeros. */
184 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
185 sctx
->null_const_buf
.buffer
->width0
, 0, false);
188 /* XXX: This is the maximum value allowed. I'm not sure how to compute
189 * this for non-cs shaders. Using the wrong value here can result in
190 * GPU lockups, but the maximum value seems to always work.
192 sctx
->scratch_waves
= 32 * sscreen
->b
.info
.max_compute_units
;
194 #if HAVE_LLVM >= 0x0306
195 /* Initialize LLVM TargetMachine */
196 r600_target
= radeon_llvm_get_r600_target(triple
);
197 sctx
->tm
= LLVMCreateTargetMachine(r600_target
, triple
,
198 r600_get_llvm_processor_name(sscreen
->b
.family
),
199 sctx
->b
.chip_class
>= VI
?
201 "+DumpCode,+vgpr-spilling",
202 LLVMCodeGenLevelDefault
,
204 LLVMCodeModelDefault
);
209 si_destroy_context(&sctx
->b
.b
);
217 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
219 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
222 /* Supported features (boolean caps). */
223 case PIPE_CAP_TWO_SIDED_STENCIL
:
224 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
225 case PIPE_CAP_ANISOTROPIC_FILTER
:
226 case PIPE_CAP_POINT_SPRITE
:
227 case PIPE_CAP_OCCLUSION_QUERY
:
228 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
229 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
230 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
231 case PIPE_CAP_TEXTURE_SWIZZLE
:
232 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
233 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
234 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
235 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
236 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
237 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
238 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
240 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
241 case PIPE_CAP_PRIMITIVE_RESTART
:
242 case PIPE_CAP_CONDITIONAL_RENDER
:
243 case PIPE_CAP_TEXTURE_BARRIER
:
244 case PIPE_CAP_INDEP_BLEND_ENABLE
:
245 case PIPE_CAP_INDEP_BLEND_FUNC
:
246 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
247 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
248 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
249 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
250 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
251 case PIPE_CAP_USER_INDEX_BUFFERS
:
252 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
253 case PIPE_CAP_START_INSTANCE
:
254 case PIPE_CAP_NPOT_TEXTURES
:
255 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
256 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
257 case PIPE_CAP_TGSI_INSTANCEID
:
258 case PIPE_CAP_COMPUTE
:
259 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
260 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
261 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
262 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
263 case PIPE_CAP_CUBE_MAP_ARRAY
:
264 case PIPE_CAP_SAMPLE_SHADING
:
265 case PIPE_CAP_DRAW_INDIRECT
:
266 case PIPE_CAP_CLIP_HALFZ
:
267 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
268 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
269 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
270 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
271 case PIPE_CAP_TGSI_TEXCOORD
:
272 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
273 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
274 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
275 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
276 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
279 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
280 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
282 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
283 return (sscreen
->b
.info
.drm_major
== 2 &&
284 sscreen
->b
.info
.drm_minor
>= 43) ||
285 sscreen
->b
.info
.drm_major
== 3;
287 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
288 /* 2D tiling on CIK is supported since DRM 2.35.0 */
289 return sscreen
->b
.chip_class
< CIK
||
290 (sscreen
->b
.info
.drm_major
== 2 &&
291 sscreen
->b
.info
.drm_minor
>= 35) ||
292 sscreen
->b
.info
.drm_major
== 3;
294 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
295 return R600_MAP_BUFFER_ALIGNMENT
;
297 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
298 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
301 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
302 return HAVE_LLVM
>= 0x0307 ? 410 : 330;
304 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
305 return MIN2(sscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
307 case PIPE_CAP_TEXTURE_QUERY_LOD
:
308 case PIPE_CAP_TEXTURE_GATHER_SM5
:
309 return HAVE_LLVM
>= 0x0305;
310 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
311 return HAVE_LLVM
>= 0x0305 ? 4 : 0;
313 /* Unsupported features. */
314 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
315 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
316 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
317 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
318 case PIPE_CAP_USER_VERTEX_BUFFERS
:
319 case PIPE_CAP_FAKE_SW_MSAA
:
320 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
321 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
322 case PIPE_CAP_VERTEXID_NOBASE
:
325 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
328 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
329 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
332 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
333 return sscreen
->b
.has_streamout
? 4 : 0;
334 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
335 return sscreen
->b
.has_streamout
? 1 : 0;
336 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
337 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
338 return sscreen
->b
.has_streamout
? 32*4 : 0;
340 /* Geometry shader output. */
341 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
343 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
345 case PIPE_CAP_MAX_VERTEX_STREAMS
:
348 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
352 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
353 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
354 return 15; /* 16384 */
355 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
356 /* textures support 8192, but layered rendering supports 2048 */
358 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
359 /* textures support 8192, but layered rendering supports 2048 */
362 /* Render targets. */
363 case PIPE_CAP_MAX_RENDER_TARGETS
:
366 case PIPE_CAP_MAX_VIEWPORTS
:
369 /* Timer queries, present when the clock frequency is non zero. */
370 case PIPE_CAP_QUERY_TIMESTAMP
:
371 case PIPE_CAP_QUERY_TIME_ELAPSED
:
372 return sscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
374 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
375 case PIPE_CAP_MIN_TEXEL_OFFSET
:
378 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
379 case PIPE_CAP_MAX_TEXEL_OFFSET
:
382 case PIPE_CAP_ENDIANNESS
:
383 return PIPE_ENDIAN_LITTLE
;
385 case PIPE_CAP_VENDOR_ID
:
387 case PIPE_CAP_DEVICE_ID
:
388 return sscreen
->b
.info
.pci_id
;
389 case PIPE_CAP_ACCELERATED
:
391 case PIPE_CAP_VIDEO_MEMORY
:
392 return sscreen
->b
.info
.vram_size
>> 20;
399 static int si_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
403 case PIPE_SHADER_FRAGMENT
:
404 case PIPE_SHADER_VERTEX
:
405 case PIPE_SHADER_GEOMETRY
:
407 case PIPE_SHADER_TESS_CTRL
:
408 case PIPE_SHADER_TESS_EVAL
:
409 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
410 if (HAVE_LLVM
< 0x0306 ||
411 (HAVE_LLVM
== 0x0306 && MESA_LLVM_VERSION_PATCH
< 2))
414 case PIPE_SHADER_COMPUTE
:
416 case PIPE_SHADER_CAP_PREFERRED_IR
:
417 #if HAVE_LLVM < 0x0306
418 return PIPE_SHADER_IR_LLVM
;
420 return PIPE_SHADER_IR_NATIVE
;
422 case PIPE_SHADER_CAP_DOUBLES
:
423 return HAVE_LLVM
>= 0x0307;
425 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
426 uint64_t max_const_buffer_size
;
427 pscreen
->get_compute_param(pscreen
,
428 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
429 &max_const_buffer_size
);
430 return max_const_buffer_size
;
433 /* If compute shaders don't require a special value
434 * for this cap, we can return the same value we
435 * do for other shader types. */
444 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
445 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
446 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
447 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
449 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
451 case PIPE_SHADER_CAP_MAX_INPUTS
:
452 return shader
== PIPE_SHADER_VERTEX
? SI_NUM_VERTEX_BUFFERS
: 32;
453 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
454 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
455 case PIPE_SHADER_CAP_MAX_TEMPS
:
456 return 256; /* Max native temporaries. */
457 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
458 return 4096 * sizeof(float[4]); /* actually only memory limits this */
459 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
460 return SI_NUM_USER_CONST_BUFFERS
;
461 case PIPE_SHADER_CAP_MAX_PREDS
:
462 return 0; /* FIXME */
463 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
465 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
467 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
468 /* Indirection of geometry shader input dimension is not
471 return shader
!= PIPE_SHADER_GEOMETRY
;
472 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
473 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
474 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
476 case PIPE_SHADER_CAP_INTEGERS
:
478 case PIPE_SHADER_CAP_SUBROUTINES
:
480 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
481 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
483 case PIPE_SHADER_CAP_PREFERRED_IR
:
484 return PIPE_SHADER_IR_TGSI
;
485 case PIPE_SHADER_CAP_DOUBLES
:
486 return HAVE_LLVM
>= 0x0307;
487 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
488 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
490 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
491 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
497 static void si_destroy_screen(struct pipe_screen
* pscreen
)
499 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
504 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
507 r600_destroy_common_screen(&sscreen
->b
);
510 #define SI_TILE_MODE_COLOR_2D_8BPP 14
512 /* Initialize pipe config. This is especially important for GPUs
513 * with 16 pipes and more where it's initialized incorrectly by
514 * the TILING_CONFIG ioctl. */
515 static bool si_initialize_pipe_config(struct si_screen
*sscreen
)
519 /* This is okay, because there can be no 2D tiling without
520 * the tile mode array, so we won't need the pipe config.
523 if (!sscreen
->b
.info
.si_tile_mode_array_valid
)
526 /* The same index is used for the 2D mode on CIK too. */
527 mode2d
= sscreen
->b
.info
.si_tile_mode_array
[SI_TILE_MODE_COLOR_2D_8BPP
];
529 switch (G_009910_PIPE_CONFIG(mode2d
)) {
530 case V_02803C_ADDR_SURF_P2
:
531 sscreen
->b
.tiling_info
.num_channels
= 2;
533 case V_02803C_X_ADDR_SURF_P4_8X16
:
534 case V_02803C_X_ADDR_SURF_P4_16X16
:
535 case V_02803C_X_ADDR_SURF_P4_16X32
:
536 case V_02803C_X_ADDR_SURF_P4_32X32
:
537 sscreen
->b
.tiling_info
.num_channels
= 4;
539 case V_02803C_X_ADDR_SURF_P8_16X16_8X16
:
540 case V_02803C_X_ADDR_SURF_P8_16X32_8X16
:
541 case V_02803C_X_ADDR_SURF_P8_32X32_8X16
:
542 case V_02803C_X_ADDR_SURF_P8_16X32_16X16
:
543 case V_02803C_X_ADDR_SURF_P8_32X32_16X16
:
544 case V_02803C_X_ADDR_SURF_P8_32X32_16X32
:
545 case V_02803C_X_ADDR_SURF_P8_32X64_32X32
:
546 sscreen
->b
.tiling_info
.num_channels
= 8;
548 case V_02803C_X_ADDR_SURF_P16_32X32_8X16
:
549 case V_02803C_X_ADDR_SURF_P16_32X32_16X16
:
550 sscreen
->b
.tiling_info
.num_channels
= 16;
554 fprintf(stderr
, "radeonsi: Unknown pipe config %i.\n",
555 G_009910_PIPE_CONFIG(mode2d
));
561 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
563 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
565 if (sscreen
== NULL
) {
569 /* Set functions first. */
570 sscreen
->b
.b
.context_create
= si_create_context
;
571 sscreen
->b
.b
.destroy
= si_destroy_screen
;
572 sscreen
->b
.b
.get_param
= si_get_param
;
573 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
574 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
575 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
577 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
578 !si_initialize_pipe_config(sscreen
)) {
583 sscreen
->b
.has_cp_dma
= true;
584 sscreen
->b
.has_streamout
= true;
586 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE
))
587 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
589 /* Create the auxiliary context. This must be done last. */
590 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
, 0);
592 return &sscreen
->b
.b
;