2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
31 #include "ac_llvm_util.h"
32 #include "radeon/radeon_uvd.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
44 static const struct debug_named_value debug_options
[] = {
45 /* Shader logging options: */
46 { "vs", DBG(VS
), "Print vertex shaders" },
47 { "ps", DBG(PS
), "Print pixel shaders" },
48 { "gs", DBG(GS
), "Print geometry shaders" },
49 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
50 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
51 { "cs", DBG(CS
), "Print compute shaders" },
52 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
53 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
54 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
55 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
57 /* Shader compiler options the shader cache should be aware of: */
58 { "unsafemath", DBG(UNSAFE_MATH
), "Enable unsafe math shader optimizations" },
59 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
60 { "gisel", DBG(GISEL
), "Enable LLVM global instruction selector." },
62 /* Shader compiler options (with no effect on the shader cache): */
63 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
64 { "nir", DBG(NIR
), "Enable experimental NIR shaders" },
65 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
66 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
68 /* Information logging options: */
69 { "info", DBG(INFO
), "Print driver information" },
70 { "tex", DBG(TEX
), "Print texture info" },
71 { "compute", DBG(COMPUTE
), "Print compute info" },
72 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
75 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
76 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
77 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
78 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
79 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
80 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
82 /* 3D engine options: */
83 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
84 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
85 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
86 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
87 { "dpbb", DBG(DPBB
), "Enable DPBB." },
88 { "dfsm", DBG(DFSM
), "Enable DFSM." },
89 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
90 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
91 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
92 { "notiling", DBG(NO_TILING
), "Disable tiling" },
93 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
94 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
95 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
96 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
97 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
100 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
101 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
102 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
103 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
104 { "testdmaperf", DBG(TEST_DMA_PERF
), "Test DMA performance" },
106 DEBUG_NAMED_VALUE_END
/* must be last */
109 static void si_init_compiler(struct si_screen
*sscreen
,
110 struct ac_llvm_compiler
*compiler
)
112 /* Only create the less-optimizing version of the compiler on APUs
113 * predating Ryzen (Raven). */
114 bool create_low_opt_compiler
= !sscreen
->info
.has_dedicated_vram
&&
115 sscreen
->info
.chip_class
<= VI
;
117 enum ac_target_machine_options tm_options
=
118 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
119 (sscreen
->debug_flags
& DBG(GISEL
) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
120 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
121 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
122 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
123 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0) |
124 (create_low_opt_compiler
? AC_TM_CREATE_LOW_OPT
: 0);
127 ac_init_llvm_compiler(compiler
, true, sscreen
->info
.family
, tm_options
);
128 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
130 if (compiler
->low_opt_tm
)
131 compiler
->low_opt_passes
= ac_create_llvm_passes(compiler
->low_opt_tm
);
134 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
136 ac_destroy_llvm_passes(compiler
->passes
);
137 ac_destroy_llvm_passes(compiler
->low_opt_passes
);
138 ac_destroy_llvm_compiler(compiler
);
144 static void si_destroy_context(struct pipe_context
*context
)
146 struct si_context
*sctx
= (struct si_context
*)context
;
149 /* Unreference the framebuffer normally to disable related logic
152 struct pipe_framebuffer_state fb
= {};
153 if (context
->set_framebuffer_state
)
154 context
->set_framebuffer_state(context
, &fb
);
156 si_release_all_descriptors(sctx
);
158 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
159 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
160 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
161 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
162 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
163 free(sctx
->border_color_table
);
164 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
165 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
166 r600_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
168 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
169 if (sctx
->init_config_gs_rings
)
170 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
171 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
172 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
174 if (sctx
->fixed_func_tcs_shader
.cso
)
175 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
176 if (sctx
->custom_dsa_flush
)
177 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
178 if (sctx
->custom_blend_resolve
)
179 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
180 if (sctx
->custom_blend_fmask_decompress
)
181 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
182 if (sctx
->custom_blend_eliminate_fastclear
)
183 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
184 if (sctx
->custom_blend_dcc_decompress
)
185 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
186 if (sctx
->vs_blit_pos
)
187 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
188 if (sctx
->vs_blit_pos_layered
)
189 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
190 if (sctx
->vs_blit_color
)
191 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
192 if (sctx
->vs_blit_color_layered
)
193 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
194 if (sctx
->vs_blit_texcoord
)
195 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
198 util_blitter_destroy(sctx
->blitter
);
200 /* Release DCC stats. */
201 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
202 assert(!sctx
->dcc_stats
[i
].query_active
);
204 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
205 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
206 sctx
->b
.destroy_query(&sctx
->b
,
207 sctx
->dcc_stats
[i
].ps_stats
[j
]);
209 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
212 if (sctx
->query_result_shader
)
213 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
216 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
218 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
220 sctx
->ws
->ctx_destroy(sctx
->ctx
);
222 if (sctx
->b
.stream_uploader
)
223 u_upload_destroy(sctx
->b
.stream_uploader
);
224 if (sctx
->b
.const_uploader
)
225 u_upload_destroy(sctx
->b
.const_uploader
);
226 if (sctx
->cached_gtt_allocator
)
227 u_upload_destroy(sctx
->cached_gtt_allocator
);
229 slab_destroy_child(&sctx
->pool_transfers
);
230 slab_destroy_child(&sctx
->pool_transfers_unsync
);
232 if (sctx
->allocator_zeroed_memory
)
233 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
235 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
236 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
237 r600_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
239 si_destroy_compiler(&sctx
->compiler
);
241 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
243 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
244 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
246 util_dynarray_fini(&sctx
->resident_tex_handles
);
247 util_dynarray_fini(&sctx
->resident_img_handles
);
248 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
249 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
250 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
254 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
256 struct si_context
*sctx
= (struct si_context
*)ctx
;
258 if (sctx
->screen
->info
.has_gpu_reset_status_query
)
259 return sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
261 if (sctx
->screen
->info
.has_gpu_reset_counter_query
) {
262 unsigned latest
= sctx
->ws
->query_value(sctx
->ws
,
263 RADEON_GPU_RESET_COUNTER
);
265 if (sctx
->gpu_reset_counter
== latest
)
266 return PIPE_NO_RESET
;
268 sctx
->gpu_reset_counter
= latest
;
269 return PIPE_UNKNOWN_CONTEXT_RESET
;
272 return PIPE_NO_RESET
;
275 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
276 const struct pipe_device_reset_callback
*cb
)
278 struct si_context
*sctx
= (struct si_context
*)ctx
;
281 sctx
->device_reset_callback
= *cb
;
283 memset(&sctx
->device_reset_callback
, 0,
284 sizeof(sctx
->device_reset_callback
));
287 bool si_check_device_reset(struct si_context
*sctx
)
289 enum pipe_reset_status status
;
291 if (!sctx
->device_reset_callback
.reset
)
294 if (!sctx
->b
.get_device_reset_status
)
297 status
= sctx
->b
.get_device_reset_status(&sctx
->b
);
298 if (status
== PIPE_NO_RESET
)
301 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
305 /* Apitrace profiling:
306 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
307 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
308 * and remember its number.
309 * 3) In Mesa, enable queries and performance counters around that draw
310 * call and print the results.
311 * 4) glretrace --benchmark --markers ..
313 static void si_emit_string_marker(struct pipe_context
*ctx
,
314 const char *string
, int len
)
316 struct si_context
*sctx
= (struct si_context
*)ctx
;
318 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
321 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
324 static void si_set_debug_callback(struct pipe_context
*ctx
,
325 const struct pipe_debug_callback
*cb
)
327 struct si_context
*sctx
= (struct si_context
*)ctx
;
328 struct si_screen
*screen
= sctx
->screen
;
330 util_queue_finish(&screen
->shader_compiler_queue
);
331 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
336 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
339 static void si_set_log_context(struct pipe_context
*ctx
,
340 struct u_log_context
*log
)
342 struct si_context
*sctx
= (struct si_context
*)ctx
;
346 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
349 static void si_set_context_param(struct pipe_context
*ctx
,
350 enum pipe_context_param param
,
353 struct radeon_winsys
*ws
= ((struct si_context
*)ctx
)->ws
;
356 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
:
357 ws
->pin_threads_to_L3_cache(ws
, value
);
363 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
366 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
367 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
368 struct radeon_winsys
*ws
= sscreen
->ws
;
374 if (flags
& PIPE_CONTEXT_DEBUG
)
375 sscreen
->record_llvm_ir
= true; /* racy but not critical */
377 sctx
->b
.screen
= screen
; /* this must be set first */
379 sctx
->b
.destroy
= si_destroy_context
;
380 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
381 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
382 sctx
->b
.set_log_context
= si_set_log_context
;
383 sctx
->b
.set_context_param
= si_set_context_param
;
384 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
385 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
387 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
388 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
390 sctx
->ws
= sscreen
->ws
;
391 sctx
->family
= sscreen
->info
.family
;
392 sctx
->chip_class
= sscreen
->info
.chip_class
;
394 if (sscreen
->info
.has_gpu_reset_counter_query
) {
395 sctx
->gpu_reset_counter
=
396 sctx
->ws
->query_value(sctx
->ws
, RADEON_GPU_RESET_COUNTER
);
399 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
400 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
402 si_init_context_texture_functions(sctx
);
403 si_init_query_functions(sctx
);
405 if (sctx
->chip_class
== CIK
||
406 sctx
->chip_class
== VI
||
407 sctx
->chip_class
== GFX9
) {
408 sctx
->eop_bug_scratch
= r600_resource(
409 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
410 16 * sscreen
->info
.num_render_backends
));
411 if (!sctx
->eop_bug_scratch
)
415 sctx
->allocator_zeroed_memory
=
416 u_suballocator_create(&sctx
->b
, sscreen
->info
.gart_page_size
,
417 0, PIPE_USAGE_DEFAULT
, 0, true);
418 if (!sctx
->allocator_zeroed_memory
)
421 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
422 0, PIPE_USAGE_STREAM
,
423 SI_RESOURCE_FLAG_READ_ONLY
);
424 if (!sctx
->b
.stream_uploader
)
427 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 128 * 1024,
428 0, PIPE_USAGE_DEFAULT
,
429 SI_RESOURCE_FLAG_32BIT
|
430 (sscreen
->cpdma_prefetch_writes_memory
?
431 0 : SI_RESOURCE_FLAG_READ_ONLY
));
432 if (!sctx
->b
.const_uploader
)
435 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
436 0, PIPE_USAGE_STAGING
, 0);
437 if (!sctx
->cached_gtt_allocator
)
440 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
444 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
445 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
446 (void*)si_flush_dma_cs
,
450 si_init_buffer_functions(sctx
);
451 si_init_clear_functions(sctx
);
452 si_init_blit_functions(sctx
);
453 si_init_compute_functions(sctx
);
454 si_init_cp_dma_functions(sctx
);
455 si_init_debug_functions(sctx
);
456 si_init_msaa_functions(sctx
);
457 si_init_streamout_functions(sctx
);
459 if (sscreen
->info
.has_hw_decode
) {
460 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
461 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
463 sctx
->b
.create_video_codec
= vl_create_decoder
;
464 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
467 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
, RING_GFX
,
468 (void*)si_flush_gfx_cs
, sctx
);
471 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
472 sizeof(*sctx
->border_color_table
));
473 if (!sctx
->border_color_table
)
476 sctx
->border_color_buffer
= r600_resource(
477 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
478 SI_MAX_BORDER_COLORS
*
479 sizeof(*sctx
->border_color_table
)));
480 if (!sctx
->border_color_buffer
)
483 sctx
->border_color_map
=
484 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
485 NULL
, PIPE_TRANSFER_WRITE
);
486 if (!sctx
->border_color_map
)
489 si_init_all_descriptors(sctx
);
490 si_init_fence_functions(sctx
);
491 si_init_state_functions(sctx
);
492 si_init_shader_functions(sctx
);
493 si_init_viewport_functions(sctx
);
494 si_init_ia_multi_vgt_param_table(sctx
);
496 if (sctx
->chip_class
>= CIK
)
497 cik_init_sdma_functions(sctx
);
499 si_init_dma_functions(sctx
);
501 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
502 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
504 sctx
->blitter
= util_blitter_create(&sctx
->b
);
505 if (sctx
->blitter
== NULL
)
507 sctx
->blitter
->draw_rectangle
= si_draw_rectangle
;
508 sctx
->blitter
->skip_viewport_restore
= true;
510 sctx
->sample_mask
= 0xffff;
512 if (sctx
->chip_class
>= GFX9
) {
513 sctx
->wait_mem_scratch
= r600_resource(
514 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 4));
515 if (!sctx
->wait_mem_scratch
)
518 /* Initialize the memory. */
519 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
520 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
521 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
522 S_370_WR_CONFIRM(1) |
523 S_370_ENGINE_SEL(V_370_ME
));
524 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
);
525 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
>> 32);
526 radeon_emit(cs
, sctx
->wait_mem_number
);
527 radeon_add_to_buffer_list(sctx
, cs
, sctx
->wait_mem_scratch
,
528 RADEON_USAGE_WRITE
, RADEON_PRIO_FENCE
);
531 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
532 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
533 if (sctx
->chip_class
== CIK
) {
534 sctx
->null_const_buf
.buffer
=
535 pipe_aligned_buffer_create(screen
,
536 SI_RESOURCE_FLAG_32BIT
,
537 PIPE_USAGE_DEFAULT
, 16,
538 sctx
->screen
->info
.tcc_cache_line_size
);
539 if (!sctx
->null_const_buf
.buffer
)
541 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
543 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
544 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
545 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
546 &sctx
->null_const_buf
);
550 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
551 &sctx
->null_const_buf
);
552 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
553 &sctx
->null_const_buf
);
554 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
555 &sctx
->null_const_buf
);
556 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
557 &sctx
->null_const_buf
);
558 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
559 &sctx
->null_const_buf
);
561 /* Clear the NULL constant buffer, because loads should return zeros. */
562 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
563 sctx
->null_const_buf
.buffer
->width0
, 0,
564 SI_COHERENCY_SHADER
);
567 uint64_t max_threads_per_block
;
568 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
569 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
570 &max_threads_per_block
);
572 /* The maximum number of scratch waves. Scratch space isn't divided
573 * evenly between CUs. The number is only a function of the number of CUs.
574 * We can decrease the constant to decrease the scratch buffer size.
576 * sctx->scratch_waves must be >= the maximum posible size of
577 * 1 threadgroup, so that the hw doesn't hang from being unable
580 * The recommended value is 4 per CU at most. Higher numbers don't
581 * bring much benefit, but they still occupy chip resources (think
582 * async compute). I've seen ~2% performance difference between 4 and 32.
584 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
585 max_threads_per_block
/ 64);
587 si_init_compiler(sscreen
, &sctx
->compiler
);
589 /* Bindless handles. */
590 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
591 _mesa_key_pointer_equal
);
592 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
593 _mesa_key_pointer_equal
);
595 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
596 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
597 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
598 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
599 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
601 /* this must be last */
602 si_begin_new_gfx_cs(sctx
);
605 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
606 si_destroy_context(&sctx
->b
);
610 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
611 void *priv
, unsigned flags
)
613 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
614 struct pipe_context
*ctx
;
616 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
617 flags
|= PIPE_CONTEXT_DEBUG
;
619 ctx
= si_create_context(screen
, flags
);
621 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
624 /* Clover (compute-only) is unsupported. */
625 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
628 /* When shaders are logged to stderr, asynchronous compilation is
630 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
633 /* Use asynchronous flushes only on amdgpu, since the radeon
634 * implementation for fence_server_sync is incomplete. */
635 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
636 si_replace_buffer_storage
,
637 sscreen
->info
.drm_major
>= 3 ? si_create_fence
: NULL
,
638 &((struct si_context
*)ctx
)->tc
);
644 static void si_destroy_screen(struct pipe_screen
* pscreen
)
646 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
647 struct si_shader_part
*parts
[] = {
649 sscreen
->tcs_epilogs
,
656 if (!sscreen
->ws
->unref(sscreen
->ws
))
659 util_queue_destroy(&sscreen
->shader_compiler_queue
);
660 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
662 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
663 si_destroy_compiler(&sscreen
->compiler
[i
]);
665 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
666 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
668 /* Free shader parts. */
669 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
671 struct si_shader_part
*part
= parts
[i
];
673 parts
[i
] = part
->next
;
674 ac_shader_binary_clean(&part
->binary
);
678 mtx_destroy(&sscreen
->shader_parts_mutex
);
679 si_destroy_shader_cache(sscreen
);
681 si_perfcounters_destroy(sscreen
);
682 si_gpu_load_kill_thread(sscreen
);
684 mtx_destroy(&sscreen
->gpu_load_mutex
);
685 mtx_destroy(&sscreen
->aux_context_lock
);
686 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
688 slab_destroy_parent(&sscreen
->pool_transfers
);
690 disk_cache_destroy(sscreen
->disk_shader_cache
);
691 sscreen
->ws
->destroy(sscreen
->ws
);
695 static void si_init_gs_info(struct si_screen
*sscreen
)
697 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
698 sscreen
->info
.family
);
701 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
703 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
709 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
710 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
711 /* Override family and chip_class. */
712 sscreen
->info
.family
= i
;
714 if (i
>= CHIP_VEGA10
)
715 sscreen
->info
.chip_class
= GFX9
;
716 else if (i
>= CHIP_TONGA
)
717 sscreen
->info
.chip_class
= VI
;
718 else if (i
>= CHIP_BONAIRE
)
719 sscreen
->info
.chip_class
= CIK
;
721 sscreen
->info
.chip_class
= SI
;
723 /* Don't submit any IBs. */
724 setenv("RADEON_NOOP", "1", 1);
729 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
733 static void si_test_vmfault(struct si_screen
*sscreen
)
735 struct pipe_context
*ctx
= sscreen
->aux_context
;
736 struct si_context
*sctx
= (struct si_context
*)ctx
;
737 struct pipe_resource
*buf
=
738 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
741 puts("Buffer allocation failed.");
745 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
747 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
748 si_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0, -1);
749 ctx
->flush(ctx
, NULL
, 0);
750 puts("VM fault test: CP - done.");
752 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
753 si_sdma_clear_buffer(sctx
, buf
, 0, 4, 0);
754 ctx
->flush(ctx
, NULL
, 0);
755 puts("VM fault test: SDMA - done.");
757 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
758 util_test_constant_buffer(ctx
, buf
);
759 puts("VM fault test: Shader - done.");
764 static void si_disk_cache_create(struct si_screen
*sscreen
)
766 /* Don't use the cache if shader dumping is enabled. */
767 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
770 uint32_t mesa_timestamp
;
771 if (disk_cache_get_function_timestamp(si_disk_cache_create
,
775 uint32_t llvm_timestamp
;
777 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
,
779 res
= asprintf(×tamp_str
, "%u_%u",
780 mesa_timestamp
, llvm_timestamp
);
784 /* These flags affect shader compilation. */
785 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
790 uint64_t shader_debug_flags
= sscreen
->debug_flags
&
793 /* Add the high bits of 32-bit addresses, which affects
794 * how 32-bit addresses are expanded to 64 bits.
796 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
797 shader_debug_flags
|= (uint64_t)sscreen
->info
.address32_hi
<< 32;
799 sscreen
->disk_shader_cache
=
800 disk_cache_create(sscreen
->info
.name
,
808 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
,
809 const struct pipe_screen_config
*config
)
811 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
812 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
, i
;
819 ws
->query_info(ws
, &sscreen
->info
);
820 si_handle_env_var_force_family(sscreen
);
822 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
825 /* Set functions first. */
826 sscreen
->b
.context_create
= si_pipe_create_context
;
827 sscreen
->b
.destroy
= si_destroy_screen
;
829 si_init_screen_get_functions(sscreen
);
830 si_init_screen_buffer_functions(sscreen
);
831 si_init_screen_fence_functions(sscreen
);
832 si_init_screen_state_functions(sscreen
);
833 si_init_screen_texture_functions(sscreen
);
834 si_init_screen_query_functions(sscreen
);
836 /* Set these flags in debug_flags early, so that the shader cache takes
839 if (driQueryOptionb(config
->options
,
840 "glsl_correct_derivatives_after_discard"))
841 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
842 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
843 sscreen
->debug_flags
|= DBG(SI_SCHED
);
846 if (sscreen
->debug_flags
& DBG(INFO
))
847 ac_print_gpu_info(&sscreen
->info
);
849 slab_create_parent(&sscreen
->pool_transfers
,
850 sizeof(struct si_transfer
), 64);
852 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
853 if (sscreen
->force_aniso
>= 0) {
854 printf("radeonsi: Forcing anisotropy filter to %ix\n",
855 /* round down to a power of two */
856 1 << util_logbase2(sscreen
->force_aniso
));
859 (void) mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
860 (void) mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
862 si_init_gs_info(sscreen
);
863 if (!si_init_shader_cache(sscreen
)) {
868 si_disk_cache_create(sscreen
);
870 /* Determine the number of shader compiler threads. */
871 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
873 if (hw_threads
>= 12) {
874 num_comp_hi_threads
= hw_threads
* 3 / 4;
875 num_comp_lo_threads
= hw_threads
/ 3;
876 } else if (hw_threads
>= 6) {
877 num_comp_hi_threads
= hw_threads
- 2;
878 num_comp_lo_threads
= hw_threads
/ 2;
879 } else if (hw_threads
>= 2) {
880 num_comp_hi_threads
= hw_threads
- 1;
881 num_comp_lo_threads
= hw_threads
/ 2;
883 num_comp_hi_threads
= 1;
884 num_comp_lo_threads
= 1;
887 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
888 ARRAY_SIZE(sscreen
->compiler
));
889 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
890 ARRAY_SIZE(sscreen
->compiler_lowp
));
892 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "sh",
893 64, num_comp_hi_threads
,
894 UTIL_QUEUE_INIT_RESIZE_IF_FULL
)) {
895 si_destroy_shader_cache(sscreen
);
900 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
902 64, num_comp_lo_threads
,
903 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
904 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
905 si_destroy_shader_cache(sscreen
);
910 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
911 si_init_perfcounters(sscreen
);
913 /* Determine tessellation ring info. */
914 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= CIK
&&
915 sscreen
->info
.family
!= CHIP_CARRIZO
&&
916 sscreen
->info
.family
!= CHIP_STONEY
;
917 /* This must be one less than the maximum number due to a hw limitation.
918 * Various hardware bugs in SI, CIK, and GFX9 need this.
920 unsigned max_offchip_buffers_per_se
;
922 /* Only certain chips can use the maximum value. */
923 if (sscreen
->info
.family
== CHIP_VEGA12
||
924 sscreen
->info
.family
== CHIP_VEGA20
)
925 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
927 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
929 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
930 sscreen
->info
.max_se
;
931 unsigned offchip_granularity
;
933 /* Hawaii has a bug with offchip buffers > 256 that can be worked
934 * around by setting 4K granularity.
936 if (sscreen
->info
.family
== CHIP_HAWAII
) {
937 sscreen
->tess_offchip_block_dw_size
= 4096;
938 offchip_granularity
= V_03093C_X_4K_DWORDS
;
940 sscreen
->tess_offchip_block_dw_size
= 8192;
941 offchip_granularity
= V_03093C_X_8K_DWORDS
;
944 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
945 assert(((sscreen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
946 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
947 sscreen
->tess_offchip_block_dw_size
* 4;
949 if (sscreen
->info
.chip_class
>= CIK
) {
950 if (sscreen
->info
.chip_class
>= VI
)
951 --max_offchip_buffers
;
952 sscreen
->vgt_hs_offchip_param
=
953 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
954 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
956 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
957 sscreen
->vgt_hs_offchip_param
=
958 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
961 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
963 sscreen
->has_clear_state
= sscreen
->info
.chip_class
>= CIK
;
965 sscreen
->has_distributed_tess
=
966 sscreen
->info
.chip_class
>= VI
&&
967 sscreen
->info
.max_se
>= 2;
969 sscreen
->has_draw_indirect_multi
=
970 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
971 (sscreen
->info
.chip_class
== VI
&&
972 sscreen
->info
.pfp_fw_version
>= 121 &&
973 sscreen
->info
.me_fw_version
>= 87) ||
974 (sscreen
->info
.chip_class
== CIK
&&
975 sscreen
->info
.pfp_fw_version
>= 211 &&
976 sscreen
->info
.me_fw_version
>= 173) ||
977 (sscreen
->info
.chip_class
== SI
&&
978 sscreen
->info
.pfp_fw_version
>= 79 &&
979 sscreen
->info
.me_fw_version
>= 142);
981 sscreen
->has_out_of_order_rast
= sscreen
->info
.chip_class
>= VI
&&
982 sscreen
->info
.max_se
>= 2 &&
983 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
984 sscreen
->assume_no_z_fights
=
985 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
986 sscreen
->commutative_blend_add
=
987 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
988 sscreen
->clear_db_cache_before_clear
=
989 driQueryOptionb(config
->options
, "radeonsi_clear_db_cache_before_clear");
990 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->info
.family
>= CHIP_POLARIS10
&&
991 sscreen
->info
.family
<= CHIP_POLARIS12
) ||
992 sscreen
->info
.family
== CHIP_VEGA10
||
993 sscreen
->info
.family
== CHIP_RAVEN
;
994 sscreen
->has_ls_vgpr_init_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
995 sscreen
->info
.family
== CHIP_RAVEN
;
997 if (sscreen
->debug_flags
& DBG(DPBB
)) {
998 sscreen
->dpbb_allowed
= true;
1000 /* Only enable primitive binning on Raven by default. */
1001 /* TODO: Investigate if binning is profitable on Vega12. */
1002 sscreen
->dpbb_allowed
= sscreen
->info
.family
== CHIP_RAVEN
&&
1003 !(sscreen
->debug_flags
& DBG(NO_DPBB
));
1006 if (sscreen
->debug_flags
& DBG(DFSM
)) {
1007 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
;
1009 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
&&
1010 !(sscreen
->debug_flags
& DBG(NO_DFSM
));
1013 /* While it would be nice not to have this flag, we are constrained
1014 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1017 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
<= VI
;
1019 /* Some chips have RB+ registers, but don't support RB+. Those must
1020 * always disable it.
1022 if (sscreen
->info
.family
== CHIP_STONEY
||
1023 sscreen
->info
.chip_class
>= GFX9
) {
1024 sscreen
->has_rbplus
= true;
1026 sscreen
->rbplus_allowed
=
1027 !(sscreen
->debug_flags
& DBG(NO_RB_PLUS
)) &&
1028 (sscreen
->info
.family
== CHIP_STONEY
||
1029 sscreen
->info
.family
== CHIP_VEGA12
||
1030 sscreen
->info
.family
== CHIP_RAVEN
);
1033 sscreen
->dcc_msaa_allowed
=
1034 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1036 sscreen
->cpdma_prefetch_writes_memory
= sscreen
->info
.chip_class
<= VI
;
1038 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1039 sscreen
->use_monolithic_shaders
=
1040 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1042 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
1043 SI_CONTEXT_INV_VMEM_L1
;
1044 if (sscreen
->info
.chip_class
<= VI
) {
1045 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_GLOBAL_L2
;
1046 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1049 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1050 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1057 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1059 * s >= z >= c (ignoring this only wastes memory)
1064 * Only MSAA color and depth buffers are overriden.
1066 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1067 const char *eqaa
= debug_get_option("EQAA", NULL
);
1070 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1071 sscreen
->eqaa_force_coverage_samples
= s
;
1072 sscreen
->eqaa_force_z_samples
= z
;
1073 sscreen
->eqaa_force_color_samples
= f
;
1077 for (i
= 0; i
< num_comp_hi_threads
; i
++)
1078 si_init_compiler(sscreen
, &sscreen
->compiler
[i
]);
1079 for (i
= 0; i
< num_comp_lo_threads
; i
++)
1080 si_init_compiler(sscreen
, &sscreen
->compiler_lowp
[i
]);
1082 /* Create the auxiliary context. This must be done last. */
1083 sscreen
->aux_context
= si_create_context(&sscreen
->b
, 0);
1085 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1086 si_test_dma(sscreen
);
1088 if (sscreen
->debug_flags
& DBG(TEST_DMA_PERF
)) {
1089 si_test_dma_perf(sscreen
);
1092 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1093 DBG(TEST_VMFAULT_SDMA
) |
1094 DBG(TEST_VMFAULT_SHADER
)))
1095 si_test_vmfault(sscreen
);