src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_buffer, NULL);
  48         free(sctx->border_color_table);
  49         r600_resource_reference(&sctx->scratch_buffer, NULL);
  50         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  51
  52         si_pm4_free_state(sctx, sctx->init_config, ~0);
  53         if (sctx->init_config_gs_rings)
  54                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  55         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  56                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  57
  58         if (sctx->pstipple_sampler_state)
  59                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  60         if (sctx->fixed_func_tcs_shader.cso)
  61                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  62         if (sctx->custom_dsa_flush)
  63                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  64         if (sctx->custom_blend_resolve)
  65                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  66         if (sctx->custom_blend_decompress)
  67                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  68         if (sctx->custom_blend_fastclear)
  69                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  70         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  71
  72         if (sctx->blitter)
  73                 util_blitter_destroy(sctx->blitter);
  74
  75         r600_common_context_cleanup(&sctx->b);
  76
  77         LLVMDisposeTargetMachine(sctx->tm);
  78
  79         r600_resource_reference(&sctx->trace_buf, NULL);
  80         r600_resource_reference(&sctx->last_trace_buf, NULL);
  81         free(sctx->last_ib);
  82         if (sctx->last_bo_list) {
  83                 for (i = 0; i < sctx->last_bo_count; i++)
  84                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  85                 free(sctx->last_bo_list);
  86         }
  87         FREE(sctx);
  88 }
  89
  90 static enum pipe_reset_status
  91 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  92 {
  93         struct si_context *sctx = (struct si_context *)ctx;
  94
  95         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  96 }
  97
  98 static struct pipe_context *si_create_context(struct pipe_screen *screen,
  99                                               void *priv, unsigned flags)
 100 {
 101         struct si_context *sctx = CALLOC_STRUCT(si_context);
 102         struct si_screen* sscreen = (struct si_screen *)screen;
 103         struct radeon_winsys *ws = sscreen->b.ws;
 104         LLVMTargetRef r600_target;
 105         const char *triple = "amdgcn--";
 106         int shader, i;
 107
 108         if (!sctx)
 109                 return NULL;
 110
 111         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 112                 flags |= PIPE_CONTEXT_DEBUG;
 113
 114         sctx->b.b.screen = screen; /* this must be set first */
 115         sctx->b.b.priv = priv;
 116         sctx->b.b.destroy = si_destroy_context;
 117         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 118         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 119         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 120
 121         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 122                 goto fail;
 123
 124         if (sscreen->b.info.drm_major == 3)
 125                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 126
 127         si_init_blit_functions(sctx);
 128         si_init_compute_functions(sctx);
 129         si_init_cp_dma_functions(sctx);
 130         si_init_debug_functions(sctx);
 131
 132         if (sscreen->b.info.has_uvd) {
 133                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 134                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 135         } else {
 136                 sctx->b.b.create_video_codec = vl_create_decoder;
 137                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 138         }
 139
 140         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 141                                        sctx, sscreen->b.trace_bo ?
 142                                                sscreen->b.trace_bo->buf : NULL);
 143         sctx->b.gfx.flush = si_context_gfx_flush;
 144
 145         /* Border colors. */
 146         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 147                                           sizeof(*sctx->border_color_table));
 148         if (!sctx->border_color_table)
 149                 goto fail;
 150
 151         sctx->border_color_buffer = (struct r600_resource*)
 152                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 153                                    SI_MAX_BORDER_COLORS *
 154                                    sizeof(*sctx->border_color_table));
 155         if (!sctx->border_color_buffer)
 156                 goto fail;
 157
 158         sctx->border_color_map =
 159                 ws->buffer_map(sctx->border_color_buffer->buf,
 160                                NULL, PIPE_TRANSFER_WRITE);
 161         if (!sctx->border_color_map)
 162                 goto fail;
 163
 164         si_init_all_descriptors(sctx);
 165         si_init_state_functions(sctx);
 166         si_init_shader_functions(sctx);
 167
 168         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 169                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 170
 171         sctx->blitter = util_blitter_create(&sctx->b.b);
 172         if (sctx->blitter == NULL)
 173                 goto fail;
 174         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 175
 176         sctx->sample_mask.sample_mask = 0xffff;
 177
 178         /* these must be last */
 179         si_begin_new_cs(sctx);
 180         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 181
 182         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 183          * with a NULL buffer). We need to use a dummy buffer instead. */
 184         if (sctx->b.chip_class == CIK) {
 185                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 186                                                                  PIPE_USAGE_DEFAULT, 16);
 187                 if (!sctx->null_const_buf.buffer)
 188                         goto fail;
 189                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 190
 191                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 192                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 193                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 194                                                               &sctx->null_const_buf);
 195                         }
 196                 }
 197
 198                 /* Clear the NULL constant buffer, because loads should return zeros. */
 199                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 200                                      sctx->null_const_buf.buffer->width0, 0, false);
 201         }
 202
 203         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 204          * this for non-cs shaders.  Using the wrong value here can result in
 205          * GPU lockups, but the maximum value seems to always work.
 206          */
 207         sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
 208
 209         /* Initialize LLVM TargetMachine */
 210         r600_target = radeon_llvm_get_r600_target(triple);
 211         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 212                                            r600_get_llvm_processor_name(sscreen->b.family),
 213 #if HAVE_LLVM >= 0x0308
 214                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 215                                                 "+DumpCode,+vgpr-spilling,+si-scheduler" :
 216 #endif
 217                                                 "+DumpCode,+vgpr-spilling",
 218                                            LLVMCodeGenLevelDefault,
 219                                            LLVMRelocDefault,
 220                                            LLVMCodeModelDefault);
 221
 222         return &sctx->b.b;
 223 fail:
 224         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 225         si_destroy_context(&sctx->b.b);
 226         return NULL;
 227 }
 228
 229 /*
 230  * pipe_screen
 231  */
 232
 233 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 234 {
 235         struct si_screen *sscreen = (struct si_screen *)pscreen;
 236
 237         switch (param) {
 238         /* Supported features (boolean caps). */
 239         case PIPE_CAP_TWO_SIDED_STENCIL:
 240         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 241         case PIPE_CAP_ANISOTROPIC_FILTER:
 242         case PIPE_CAP_POINT_SPRITE:
 243         case PIPE_CAP_OCCLUSION_QUERY:
 244         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 245         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 246         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 247         case PIPE_CAP_TEXTURE_SWIZZLE:
 248         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 249         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 250         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 251         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 252         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 253         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 254         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 255         case PIPE_CAP_SM3:
 256         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 257         case PIPE_CAP_PRIMITIVE_RESTART:
 258         case PIPE_CAP_CONDITIONAL_RENDER:
 259         case PIPE_CAP_TEXTURE_BARRIER:
 260         case PIPE_CAP_INDEP_BLEND_ENABLE:
 261         case PIPE_CAP_INDEP_BLEND_FUNC:
 262         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 263         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 264         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 265         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 266         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 267         case PIPE_CAP_USER_INDEX_BUFFERS:
 268         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 269         case PIPE_CAP_START_INSTANCE:
 270         case PIPE_CAP_NPOT_TEXTURES:
 271         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 272         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 273         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 274         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 275         case PIPE_CAP_TGSI_INSTANCEID:
 276         case PIPE_CAP_COMPUTE:
 277         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 278         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 279         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 280         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 281         case PIPE_CAP_CUBE_MAP_ARRAY:
 282         case PIPE_CAP_SAMPLE_SHADING:
 283         case PIPE_CAP_DRAW_INDIRECT:
 284         case PIPE_CAP_CLIP_HALFZ:
 285         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 286         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 287         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 288         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 289         case PIPE_CAP_TGSI_TEXCOORD:
 290         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 291         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 292         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 293         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 294         case PIPE_CAP_SHAREABLE_SHADERS:
 295         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 296         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 297         case PIPE_CAP_TEXTURE_QUERY_LOD:
 298         case PIPE_CAP_TEXTURE_GATHER_SM5:
 299         case PIPE_CAP_TGSI_TXQS:
 300         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 301         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 302         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 303         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 304         case PIPE_CAP_INVALIDATE_BUFFER:
 305         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 306         case PIPE_CAP_QUERY_MEMORY_INFO:
 307         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 308                 return 1;
 309
 310         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 311                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 312
 313         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 314                 return (sscreen->b.info.drm_major == 2 &&
 315                         sscreen->b.info.drm_minor >= 43) ||
 316                        sscreen->b.info.drm_major == 3;
 317
 318         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 319                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 320                 return sscreen->b.chip_class < CIK ||
 321                        (sscreen->b.info.drm_major == 2 &&
 322                         sscreen->b.info.drm_minor >= 35) ||
 323                        sscreen->b.info.drm_major == 3;
 324
 325         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 326                 return R600_MAP_BUFFER_ALIGNMENT;
 327
 328         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 329         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 330         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 331                 return 4;
 332
 333         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 334                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 335
 336         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 337                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 338
 339         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 340                 return 0;
 341
 342         /* Unsupported features. */
 343         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 344         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 345         case PIPE_CAP_USER_VERTEX_BUFFERS:
 346         case PIPE_CAP_FAKE_SW_MSAA:
 347         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 348         case PIPE_CAP_VERTEXID_NOBASE:
 349         case PIPE_CAP_CLEAR_TEXTURE:
 350         case PIPE_CAP_DRAW_PARAMETERS:
 351         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 352         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 353         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 354         case PIPE_CAP_GENERATE_MIPMAP:
 355         case PIPE_CAP_STRING_MARKER:
 356         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 357                 return 0;
 358
 359         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 360                 return 30;
 361
 362         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 363                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 364
 365         /* Stream output. */
 366         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 367                 return sscreen->b.has_streamout ? 4 : 0;
 368         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 369                 return sscreen->b.has_streamout ? 1 : 0;
 370         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 371         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 372                 return sscreen->b.has_streamout ? 32*4 : 0;
 373
 374         /* Geometry shader output. */
 375         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 376                 return 1024;
 377         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 378                 return 4095;
 379         case PIPE_CAP_MAX_VERTEX_STREAMS:
 380                 return 4;
 381
 382         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 383                 return 2048;
 384
 385         /* Texturing. */
 386         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 387         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 388                 return 15; /* 16384 */
 389         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 390                 /* textures support 8192, but layered rendering supports 2048 */
 391                 return 12;
 392         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 393                 /* textures support 8192, but layered rendering supports 2048 */
 394                 return 2048;
 395
 396         /* Render targets. */
 397         case PIPE_CAP_MAX_RENDER_TARGETS:
 398                 return 8;
 399
 400         case PIPE_CAP_MAX_VIEWPORTS:
 401                 return SI_MAX_VIEWPORTS;
 402
 403         /* Timer queries, present when the clock frequency is non zero. */
 404         case PIPE_CAP_QUERY_TIMESTAMP:
 405         case PIPE_CAP_QUERY_TIME_ELAPSED:
 406                 return sscreen->b.info.clock_crystal_freq != 0;
 407
 408         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 409         case PIPE_CAP_MIN_TEXEL_OFFSET:
 410                 return -32;
 411
 412         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 413         case PIPE_CAP_MAX_TEXEL_OFFSET:
 414                 return 31;
 415
 416         case PIPE_CAP_ENDIANNESS:
 417                 return PIPE_ENDIAN_LITTLE;
 418
 419         case PIPE_CAP_VENDOR_ID:
 420                 return 0x1002;
 421         case PIPE_CAP_DEVICE_ID:
 422                 return sscreen->b.info.pci_id;
 423         case PIPE_CAP_ACCELERATED:
 424                 return 1;
 425         case PIPE_CAP_VIDEO_MEMORY:
 426                 return sscreen->b.info.vram_size >> 20;
 427         case PIPE_CAP_UMA:
 428                 return 0;
 429         }
 430         return 0;
 431 }
 432
 433 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 434 {
 435         switch(shader)
 436         {
 437         case PIPE_SHADER_FRAGMENT:
 438         case PIPE_SHADER_VERTEX:
 439         case PIPE_SHADER_GEOMETRY:
 440                 break;
 441         case PIPE_SHADER_TESS_CTRL:
 442         case PIPE_SHADER_TESS_EVAL:
 443                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 444                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 445                         return 0;
 446                 break;
 447         case PIPE_SHADER_COMPUTE:
 448                 switch (param) {
 449                 case PIPE_SHADER_CAP_PREFERRED_IR:
 450                         return PIPE_SHADER_IR_NATIVE;
 451
 452                 case PIPE_SHADER_CAP_SUPPORTED_IRS:
 453                         return 0;
 454
 455                 case PIPE_SHADER_CAP_DOUBLES:
 456                         return HAVE_LLVM >= 0x0307;
 457
 458                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 459                         uint64_t max_const_buffer_size;
 460                         pscreen->get_compute_param(pscreen,
 461                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 462                                 &max_const_buffer_size);
 463                         return max_const_buffer_size;
 464                 }
 465                 default:
 466                         /* If compute shaders don't require a special value
 467                          * for this cap, we can return the same value we
 468                          * do for other shader types. */
 469                         break;
 470                 }
 471                 break;
 472         default:
 473                 return 0;
 474         }
 475
 476         switch (param) {
 477         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 478         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 479         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 480         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 481                 return 16384;
 482         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 483                 return 32;
 484         case PIPE_SHADER_CAP_MAX_INPUTS:
 485                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 486         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 487                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 488         case PIPE_SHADER_CAP_MAX_TEMPS:
 489                 return 256; /* Max native temporaries. */
 490         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 491                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 492         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 493                 return SI_NUM_USER_CONST_BUFFERS;
 494         case PIPE_SHADER_CAP_MAX_PREDS:
 495                 return 0; /* FIXME */
 496         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 497                 return 1;
 498         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 499                 return 1;
 500         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 501                 /* Indirection of geometry shader input dimension is not
 502                  * handled yet
 503                  */
 504                 return shader != PIPE_SHADER_GEOMETRY;
 505         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 506         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 507         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 508                 return 1;
 509         case PIPE_SHADER_CAP_INTEGERS:
 510                 return 1;
 511         case PIPE_SHADER_CAP_SUBROUTINES:
 512                 return 0;
 513         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 514         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 515                 return 16;
 516         case PIPE_SHADER_CAP_PREFERRED_IR:
 517                 return PIPE_SHADER_IR_TGSI;
 518         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 519                 return 0;
 520         case PIPE_SHADER_CAP_DOUBLES:
 521                 return HAVE_LLVM >= 0x0307;
 522         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 523         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 524                 return 0;
 525         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 526         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 527                 return 1;
 528         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 529                 return 32;
 530         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 531         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 532                 return 0;
 533         }
 534         return 0;
 535 }
 536
 537 static void si_destroy_screen(struct pipe_screen* pscreen)
 538 {
 539         struct si_screen *sscreen = (struct si_screen *)pscreen;
 540
 541         if (!sscreen)
 542                 return;
 543
 544         if (!sscreen->b.ws->unref(sscreen->b.ws))
 545                 return;
 546
 547         r600_destroy_common_screen(&sscreen->b);
 548 }
 549
 550 static bool si_init_gs_info(struct si_screen *sscreen)
 551 {
 552         switch (sscreen->b.family) {
 553         case CHIP_OLAND:
 554         case CHIP_HAINAN:
 555         case CHIP_KAVERI:
 556         case CHIP_KABINI:
 557         case CHIP_MULLINS:
 558         case CHIP_ICELAND:
 559         case CHIP_CARRIZO:
 560         case CHIP_STONEY:
 561                 sscreen->gs_table_depth = 16;
 562                 return true;
 563         case CHIP_TAHITI:
 564         case CHIP_PITCAIRN:
 565         case CHIP_VERDE:
 566         case CHIP_BONAIRE:
 567         case CHIP_HAWAII:
 568         case CHIP_TONGA:
 569         case CHIP_FIJI:
 570                 sscreen->gs_table_depth = 32;
 571                 return true;
 572         default:
 573                 return false;
 574         }
 575 }
 576
 577 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 578 {
 579         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 580
 581         if (!sscreen) {
 582                 return NULL;
 583         }
 584
 585         /* Set functions first. */
 586         sscreen->b.b.context_create = si_create_context;
 587         sscreen->b.b.destroy = si_destroy_screen;
 588         sscreen->b.b.get_param = si_get_param;
 589         sscreen->b.b.get_shader_param = si_get_shader_param;
 590         sscreen->b.b.is_format_supported = si_is_format_supported;
 591         sscreen->b.b.resource_create = r600_resource_create_common;
 592
 593         if (!r600_common_screen_init(&sscreen->b, ws) ||
 594             !si_init_gs_info(sscreen)) {
 595                 FREE(sscreen);
 596                 return NULL;
 597         }
 598
 599         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 600                 si_init_perfcounters(sscreen);
 601
 602         sscreen->b.has_cp_dma = true;
 603         sscreen->b.has_streamout = true;
 604         sscreen->use_monolithic_shaders = true;
 605
 606         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 607                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 608
 609         /* Create the auxiliary context. This must be done last. */
 610         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 611
 612         return &sscreen->b.b;
 613 }