src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "vl/vl_decoder.h"
  33
  34 /*
  35  * pipe_context
  36  */
  37 static void si_destroy_context(struct pipe_context *context)
  38 {
  39         struct si_context *sctx = (struct si_context *)context;
  40         int i;
  41
  42         si_release_all_descriptors(sctx);
  43
  44         pipe_resource_reference(&sctx->esgs_ring, NULL);
  45         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  46         pipe_resource_reference(&sctx->tf_ring, NULL);
  47         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  48         r600_resource_reference(&sctx->border_color_buffer, NULL);
  49         free(sctx->border_color_table);
  50         r600_resource_reference(&sctx->scratch_buffer, NULL);
  51         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  52
  53         si_pm4_free_state(sctx, sctx->init_config, ~0);
  54         if (sctx->init_config_gs_rings)
  55                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  56         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  57                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  58
  59         if (sctx->pstipple_sampler_state)
  60                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  61         if (sctx->fixed_func_tcs_shader.cso)
  62                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  63         if (sctx->custom_dsa_flush)
  64                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  65         if (sctx->custom_blend_resolve)
  66                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  67         if (sctx->custom_blend_decompress)
  68                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  69         if (sctx->custom_blend_fastclear)
  70                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  71         if (sctx->custom_blend_dcc_decompress)
  72                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  73         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  74
  75         if (sctx->blitter)
  76                 util_blitter_destroy(sctx->blitter);
  77
  78         r600_common_context_cleanup(&sctx->b);
  79
  80         LLVMDisposeTargetMachine(sctx->tm);
  81
  82         r600_resource_reference(&sctx->trace_buf, NULL);
  83         r600_resource_reference(&sctx->last_trace_buf, NULL);
  84         free(sctx->last_ib);
  85         if (sctx->last_bo_list) {
  86                 for (i = 0; i < sctx->last_bo_count; i++)
  87                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  88                 free(sctx->last_bo_list);
  89         }
  90         FREE(sctx);
  91 }
  92
  93 static enum pipe_reset_status
  94 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  95 {
  96         struct si_context *sctx = (struct si_context *)ctx;
  97
  98         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  99 }
 100
 101 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 102                                               void *priv, unsigned flags)
 103 {
 104         struct si_context *sctx = CALLOC_STRUCT(si_context);
 105         struct si_screen* sscreen = (struct si_screen *)screen;
 106         struct radeon_winsys *ws = sscreen->b.ws;
 107         LLVMTargetRef r600_target;
 108         const char *triple = "amdgcn--";
 109         int shader, i;
 110
 111         if (!sctx)
 112                 return NULL;
 113
 114         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 115                 flags |= PIPE_CONTEXT_DEBUG;
 116
 117         sctx->b.b.screen = screen; /* this must be set first */
 118         sctx->b.b.priv = priv;
 119         sctx->b.b.destroy = si_destroy_context;
 120         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 121         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 122         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 123
 124         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 125                 goto fail;
 126
 127         if (sscreen->b.info.drm_major == 3)
 128                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 129
 130         si_init_blit_functions(sctx);
 131         si_init_compute_functions(sctx);
 132         si_init_cp_dma_functions(sctx);
 133         si_init_debug_functions(sctx);
 134
 135         if (sscreen->b.info.has_uvd) {
 136                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 137                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 138         } else {
 139                 sctx->b.b.create_video_codec = vl_create_decoder;
 140                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 141         }
 142
 143         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 144                                        si_context_gfx_flush, sctx);
 145         sctx->b.gfx.flush = si_context_gfx_flush;
 146
 147         /* Border colors. */
 148         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 149                                           sizeof(*sctx->border_color_table));
 150         if (!sctx->border_color_table)
 151                 goto fail;
 152
 153         sctx->border_color_buffer = (struct r600_resource*)
 154                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 155                                    SI_MAX_BORDER_COLORS *
 156                                    sizeof(*sctx->border_color_table));
 157         if (!sctx->border_color_buffer)
 158                 goto fail;
 159
 160         sctx->border_color_map =
 161                 ws->buffer_map(sctx->border_color_buffer->buf,
 162                                NULL, PIPE_TRANSFER_WRITE);
 163         if (!sctx->border_color_map)
 164                 goto fail;
 165
 166         si_init_all_descriptors(sctx);
 167         si_init_state_functions(sctx);
 168         si_init_shader_functions(sctx);
 169
 170         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 171                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 172
 173         sctx->blitter = util_blitter_create(&sctx->b.b);
 174         if (sctx->blitter == NULL)
 175                 goto fail;
 176         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 177
 178         sctx->sample_mask.sample_mask = 0xffff;
 179
 180         /* these must be last */
 181         si_begin_new_cs(sctx);
 182         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 183
 184         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 185          * with a NULL buffer). We need to use a dummy buffer instead. */
 186         if (sctx->b.chip_class == CIK) {
 187                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 188                                                                  PIPE_USAGE_DEFAULT, 16);
 189                 if (!sctx->null_const_buf.buffer)
 190                         goto fail;
 191                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 192
 193                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 194                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 195                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 196                                                               &sctx->null_const_buf);
 197                         }
 198                 }
 199
 200                 /* Clear the NULL constant buffer, because loads should return zeros. */
 201                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 202                                      sctx->null_const_buf.buffer->width0, 0, false);
 203         }
 204
 205         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 206          * this for non-cs shaders.  Using the wrong value here can result in
 207          * GPU lockups, but the maximum value seems to always work.
 208          */
 209         sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
 210
 211         /* Initialize LLVM TargetMachine */
 212         r600_target = radeon_llvm_get_r600_target(triple);
 213         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 214                                            r600_get_llvm_processor_name(sscreen->b.family),
 215 #if HAVE_LLVM >= 0x0308
 216                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 217                                                 "+DumpCode,+vgpr-spilling,+si-scheduler" :
 218 #endif
 219                                                 "+DumpCode,+vgpr-spilling",
 220                                            LLVMCodeGenLevelDefault,
 221                                            LLVMRelocDefault,
 222                                            LLVMCodeModelDefault);
 223
 224         return &sctx->b.b;
 225 fail:
 226         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 227         si_destroy_context(&sctx->b.b);
 228         return NULL;
 229 }
 230
 231 /*
 232  * pipe_screen
 233  */
 234
 235 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 236 {
 237         struct si_screen *sscreen = (struct si_screen *)pscreen;
 238
 239         switch (param) {
 240         /* Supported features (boolean caps). */
 241         case PIPE_CAP_TWO_SIDED_STENCIL:
 242         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 243         case PIPE_CAP_ANISOTROPIC_FILTER:
 244         case PIPE_CAP_POINT_SPRITE:
 245         case PIPE_CAP_OCCLUSION_QUERY:
 246         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 247         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 248         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 249         case PIPE_CAP_TEXTURE_SWIZZLE:
 250         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 251         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 252         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 253         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 254         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 255         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 256         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 257         case PIPE_CAP_SM3:
 258         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 259         case PIPE_CAP_PRIMITIVE_RESTART:
 260         case PIPE_CAP_CONDITIONAL_RENDER:
 261         case PIPE_CAP_TEXTURE_BARRIER:
 262         case PIPE_CAP_INDEP_BLEND_ENABLE:
 263         case PIPE_CAP_INDEP_BLEND_FUNC:
 264         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 265         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 266         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 267         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 268         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 269         case PIPE_CAP_USER_INDEX_BUFFERS:
 270         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 271         case PIPE_CAP_START_INSTANCE:
 272         case PIPE_CAP_NPOT_TEXTURES:
 273         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 274         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 275         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 276         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 277         case PIPE_CAP_TGSI_INSTANCEID:
 278         case PIPE_CAP_COMPUTE:
 279         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 280         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 281         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 282         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 283         case PIPE_CAP_CUBE_MAP_ARRAY:
 284         case PIPE_CAP_SAMPLE_SHADING:
 285         case PIPE_CAP_DRAW_INDIRECT:
 286         case PIPE_CAP_CLIP_HALFZ:
 287         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 288         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 289         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 290         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 291         case PIPE_CAP_TGSI_TEXCOORD:
 292         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 293         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 294         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 295         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 296         case PIPE_CAP_SHAREABLE_SHADERS:
 297         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 298         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 299         case PIPE_CAP_TEXTURE_QUERY_LOD:
 300         case PIPE_CAP_TEXTURE_GATHER_SM5:
 301         case PIPE_CAP_TGSI_TXQS:
 302         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 303         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 304         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 305         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 306         case PIPE_CAP_INVALIDATE_BUFFER:
 307         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 308         case PIPE_CAP_QUERY_MEMORY_INFO:
 309         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 310                 return 1;
 311
 312         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 313                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 314
 315         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 316                 return (sscreen->b.info.drm_major == 2 &&
 317                         sscreen->b.info.drm_minor >= 43) ||
 318                        sscreen->b.info.drm_major == 3;
 319
 320         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 321                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 322                 return sscreen->b.chip_class < CIK ||
 323                        (sscreen->b.info.drm_major == 2 &&
 324                         sscreen->b.info.drm_minor >= 35) ||
 325                        sscreen->b.info.drm_major == 3;
 326
 327         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 328                 return R600_MAP_BUFFER_ALIGNMENT;
 329
 330         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 331         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 332         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 333                 return 4;
 334
 335         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 336                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 337
 338         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 339                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 340
 341         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 342                 return 0;
 343
 344         /* Unsupported features. */
 345         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 346         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 347         case PIPE_CAP_USER_VERTEX_BUFFERS:
 348         case PIPE_CAP_FAKE_SW_MSAA:
 349         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 350         case PIPE_CAP_VERTEXID_NOBASE:
 351         case PIPE_CAP_CLEAR_TEXTURE:
 352         case PIPE_CAP_DRAW_PARAMETERS:
 353         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 354         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 355         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 356         case PIPE_CAP_GENERATE_MIPMAP:
 357         case PIPE_CAP_STRING_MARKER:
 358         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 359                 return 0;
 360
 361         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 362                 return 30;
 363
 364         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 365                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 366
 367         /* Stream output. */
 368         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 369                 return sscreen->b.has_streamout ? 4 : 0;
 370         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 371                 return sscreen->b.has_streamout ? 1 : 0;
 372         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 373         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 374                 return sscreen->b.has_streamout ? 32*4 : 0;
 375
 376         /* Geometry shader output. */
 377         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 378                 return 1024;
 379         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 380                 return 4095;
 381         case PIPE_CAP_MAX_VERTEX_STREAMS:
 382                 return 4;
 383
 384         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 385                 return 2048;
 386
 387         /* Texturing. */
 388         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 389         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 390                 return 15; /* 16384 */
 391         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 392                 /* textures support 8192, but layered rendering supports 2048 */
 393                 return 12;
 394         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 395                 /* textures support 8192, but layered rendering supports 2048 */
 396                 return 2048;
 397
 398         /* Render targets. */
 399         case PIPE_CAP_MAX_RENDER_TARGETS:
 400                 return 8;
 401
 402         case PIPE_CAP_MAX_VIEWPORTS:
 403                 return SI_MAX_VIEWPORTS;
 404
 405         /* Timer queries, present when the clock frequency is non zero. */
 406         case PIPE_CAP_QUERY_TIMESTAMP:
 407         case PIPE_CAP_QUERY_TIME_ELAPSED:
 408                 return sscreen->b.info.clock_crystal_freq != 0;
 409
 410         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 411         case PIPE_CAP_MIN_TEXEL_OFFSET:
 412                 return -32;
 413
 414         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 415         case PIPE_CAP_MAX_TEXEL_OFFSET:
 416                 return 31;
 417
 418         case PIPE_CAP_ENDIANNESS:
 419                 return PIPE_ENDIAN_LITTLE;
 420
 421         case PIPE_CAP_VENDOR_ID:
 422                 return ATI_VENDOR_ID;
 423         case PIPE_CAP_DEVICE_ID:
 424                 return sscreen->b.info.pci_id;
 425         case PIPE_CAP_ACCELERATED:
 426                 return 1;
 427         case PIPE_CAP_VIDEO_MEMORY:
 428                 return sscreen->b.info.vram_size >> 20;
 429         case PIPE_CAP_UMA:
 430                 return 0;
 431         case PIPE_CAP_PCI_GROUP:
 432                 return sscreen->b.info.pci_domain;
 433         case PIPE_CAP_PCI_BUS:
 434                 return sscreen->b.info.pci_bus;
 435         case PIPE_CAP_PCI_DEVICE:
 436                 return sscreen->b.info.pci_dev;
 437         case PIPE_CAP_PCI_FUNCTION:
 438                 return sscreen->b.info.pci_func;
 439         }
 440         return 0;
 441 }
 442
 443 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 444 {
 445         switch(shader)
 446         {
 447         case PIPE_SHADER_FRAGMENT:
 448         case PIPE_SHADER_VERTEX:
 449         case PIPE_SHADER_GEOMETRY:
 450                 break;
 451         case PIPE_SHADER_TESS_CTRL:
 452         case PIPE_SHADER_TESS_EVAL:
 453                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 454                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 455                         return 0;
 456                 break;
 457         case PIPE_SHADER_COMPUTE:
 458                 switch (param) {
 459                 case PIPE_SHADER_CAP_PREFERRED_IR:
 460                         return PIPE_SHADER_IR_NATIVE;
 461
 462                 case PIPE_SHADER_CAP_SUPPORTED_IRS:
 463                         return 0;
 464
 465                 case PIPE_SHADER_CAP_DOUBLES:
 466                         return HAVE_LLVM >= 0x0307;
 467
 468                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 469                         uint64_t max_const_buffer_size;
 470                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 471                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 472                                 &max_const_buffer_size);
 473                         return max_const_buffer_size;
 474                 }
 475                 default:
 476                         /* If compute shaders don't require a special value
 477                          * for this cap, we can return the same value we
 478                          * do for other shader types. */
 479                         break;
 480                 }
 481                 break;
 482         default:
 483                 return 0;
 484         }
 485
 486         switch (param) {
 487         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 488         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 489         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 490         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 491                 return 16384;
 492         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 493                 return 32;
 494         case PIPE_SHADER_CAP_MAX_INPUTS:
 495                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 496         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 497                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 498         case PIPE_SHADER_CAP_MAX_TEMPS:
 499                 return 256; /* Max native temporaries. */
 500         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 501                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 502         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 503                 return SI_NUM_USER_CONST_BUFFERS;
 504         case PIPE_SHADER_CAP_MAX_PREDS:
 505                 return 0; /* FIXME */
 506         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 507                 return 1;
 508         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 509                 return 1;
 510         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 511                 /* Indirection of geometry shader input dimension is not
 512                  * handled yet
 513                  */
 514                 return shader != PIPE_SHADER_GEOMETRY;
 515         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 516         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 517         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 518                 return 1;
 519         case PIPE_SHADER_CAP_INTEGERS:
 520                 return 1;
 521         case PIPE_SHADER_CAP_SUBROUTINES:
 522                 return 0;
 523         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 524         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 525                 return 16;
 526         case PIPE_SHADER_CAP_PREFERRED_IR:
 527                 return PIPE_SHADER_IR_TGSI;
 528         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 529                 return 0;
 530         case PIPE_SHADER_CAP_DOUBLES:
 531                 return HAVE_LLVM >= 0x0307;
 532         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 533         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 534                 return 0;
 535         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 536         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 537                 return 1;
 538         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 539                 return 32;
 540         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 541                 return 0;
 542         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 543                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 544         }
 545         return 0;
 546 }
 547
 548 static void si_destroy_screen(struct pipe_screen* pscreen)
 549 {
 550         struct si_screen *sscreen = (struct si_screen *)pscreen;
 551         struct si_shader_part *parts[] = {
 552                 sscreen->vs_prologs,
 553                 sscreen->vs_epilogs,
 554                 sscreen->tcs_epilogs,
 555                 sscreen->ps_prologs,
 556                 sscreen->ps_epilogs
 557         };
 558         unsigned i;
 559
 560         if (!sscreen)
 561                 return;
 562
 563         if (!sscreen->b.ws->unref(sscreen->b.ws))
 564                 return;
 565
 566         /* Free shader parts. */
 567         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 568                 while (parts[i]) {
 569                         struct si_shader_part *part = parts[i];
 570
 571                         parts[i] = part->next;
 572                         radeon_shader_binary_clean(&part->binary);
 573                         FREE(part);
 574                 }
 575         }
 576         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 577         si_destroy_shader_cache(sscreen);
 578         r600_destroy_common_screen(&sscreen->b);
 579 }
 580
 581 static bool si_init_gs_info(struct si_screen *sscreen)
 582 {
 583         switch (sscreen->b.family) {
 584         case CHIP_OLAND:
 585         case CHIP_HAINAN:
 586         case CHIP_KAVERI:
 587         case CHIP_KABINI:
 588         case CHIP_MULLINS:
 589         case CHIP_ICELAND:
 590         case CHIP_CARRIZO:
 591         case CHIP_STONEY:
 592                 sscreen->gs_table_depth = 16;
 593                 return true;
 594         case CHIP_TAHITI:
 595         case CHIP_PITCAIRN:
 596         case CHIP_VERDE:
 597         case CHIP_BONAIRE:
 598         case CHIP_HAWAII:
 599         case CHIP_TONGA:
 600         case CHIP_FIJI:
 601         case CHIP_POLARIS10:
 602         case CHIP_POLARIS11:
 603                 sscreen->gs_table_depth = 32;
 604                 return true;
 605         default:
 606                 return false;
 607         }
 608 }
 609
 610 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 611 {
 612         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 613
 614         if (!sscreen) {
 615                 return NULL;
 616         }
 617
 618         /* Set functions first. */
 619         sscreen->b.b.context_create = si_create_context;
 620         sscreen->b.b.destroy = si_destroy_screen;
 621         sscreen->b.b.get_param = si_get_param;
 622         sscreen->b.b.get_shader_param = si_get_shader_param;
 623         sscreen->b.b.is_format_supported = si_is_format_supported;
 624         sscreen->b.b.resource_create = r600_resource_create_common;
 625
 626         si_init_screen_state_functions(sscreen);
 627
 628         if (!r600_common_screen_init(&sscreen->b, ws) ||
 629             !si_init_gs_info(sscreen) ||
 630             !si_init_shader_cache(sscreen)) {
 631                 FREE(sscreen);
 632                 return NULL;
 633         }
 634
 635         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 636                 si_init_perfcounters(sscreen);
 637
 638         sscreen->b.has_cp_dma = true;
 639         sscreen->b.has_streamout = true;
 640         pipe_mutex_init(sscreen->shader_parts_mutex);
 641         sscreen->use_monolithic_shaders =
 642                 HAVE_LLVM < 0x0308 ||
 643                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 644
 645         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 646                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 647
 648         /* Create the auxiliary context. This must be done last. */
 649         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 650
 651         return &sscreen->b.b;
 652 }