src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_transfer.h"
  35 #include "util/u_surface.h"
  36 #include "util/u_pack_color.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_inlines.h"
  39 #include "util/u_simple_shaders.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "si_pipe.h"
  46 #include "radeon/radeon_uvd.h"
  47 #include "si.h"
  48 #include "sid.h"
  49 #include "si_resource.h"
  50 #include "si_pipe.h"
  51 #include "si_state.h"
  52 #include "../radeon/r600_cs.h"
  53
  54 /*
  55  * pipe_context
  56  */
  57 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
  58                     unsigned flags)
  59 {
  60         struct si_context *rctx = (struct si_context *)ctx;
  61         struct pipe_query *render_cond = NULL;
  62         boolean render_cond_cond = FALSE;
  63         unsigned render_cond_mode = 0;
  64
  65         if (fence) {
  66                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
  67         }
  68
  69         /* Disable render condition. */
  70         if (rctx->current_render_cond) {
  71                 render_cond = rctx->current_render_cond;
  72                 render_cond_cond = rctx->current_render_cond_cond;
  73                 render_cond_mode = rctx->current_render_cond_mode;
  74                 ctx->render_condition(ctx, NULL, FALSE, 0);
  75         }
  76
  77         si_context_flush(rctx, flags);
  78
  79         /* Re-enable render condition. */
  80         if (render_cond) {
  81                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  82         }
  83 }
  84
  85 static void r600_flush_from_st(struct pipe_context *ctx,
  86                                struct pipe_fence_handle **fence,
  87                                unsigned flags)
  88 {
  89         radeonsi_flush(ctx, fence,
  90                        flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
  91 }
  92
  93 static void r600_flush_from_winsys(void *ctx, unsigned flags)
  94 {
  95         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
  96 }
  97
  98 static void r600_destroy_context(struct pipe_context *context)
  99 {
 100         struct si_context *rctx = (struct si_context *)context;
 101
 102         si_release_all_descriptors(rctx);
 103
 104         pipe_resource_reference(&rctx->null_const_buf.buffer, NULL);
 105         r600_resource_reference(&rctx->border_color_table, NULL);
 106
 107         if (rctx->dummy_pixel_shader) {
 108                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 109         }
 110         for (int i = 0; i < 8; i++) {
 111                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_depth_stencil[i]);
 112                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_depth[i]);
 113                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_stencil[i]);
 114         }
 115         rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_inplace);
 116         rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 117         rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 118         util_unreference_framebuffer_state(&rctx->framebuffer);
 119
 120         util_blitter_destroy(rctx->blitter);
 121
 122         r600_common_context_cleanup(&rctx->b);
 123         FREE(rctx);
 124 }
 125
 126 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 127 {
 128         struct si_context *rctx = CALLOC_STRUCT(si_context);
 129         struct si_screen* rscreen = (struct si_screen *)screen;
 130         int shader, i;
 131
 132         if (rctx == NULL)
 133                 return NULL;
 134
 135         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 136                 goto fail;
 137
 138         rctx->b.b.screen = screen;
 139         rctx->b.b.priv = priv;
 140         rctx->b.b.destroy = r600_destroy_context;
 141         rctx->b.b.flush = r600_flush_from_st;
 142
 143         /* Easy accessing of screen/winsys. */
 144         rctx->screen = rscreen;
 145
 146         si_init_blit_functions(rctx);
 147         r600_init_query_functions(rctx);
 148         r600_init_context_resource_functions(rctx);
 149         si_init_compute_functions(rctx);
 150
 151         if (rscreen->b.info.has_uvd) {
 152                 rctx->b.b.create_video_codec = radeonsi_uvd_create_decoder;
 153                 rctx->b.b.create_video_buffer = radeonsi_video_buffer_create;
 154         } else {
 155                 rctx->b.b.create_video_codec = vl_create_decoder;
 156                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 157         }
 158
 159         rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
 160         rctx->b.rings.gfx.flush = r600_flush_from_winsys;
 161
 162         si_init_all_descriptors(rctx);
 163
 164         /* Initialize cache_flush. */
 165         rctx->cache_flush = si_atom_cache_flush;
 166         rctx->atoms.cache_flush = &rctx->cache_flush;
 167
 168         rctx->atoms.streamout_begin = &rctx->b.streamout.begin_atom;
 169
 170         switch (rctx->b.chip_class) {
 171         case SI:
 172         case CIK:
 173                 si_init_state_functions(rctx);
 174                 LIST_INITHEAD(&rctx->active_nontimer_query_list);
 175                 rctx->max_db = 8;
 176                 si_init_config(rctx);
 177                 break;
 178         default:
 179                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 180                 goto fail;
 181         }
 182
 183         rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
 184
 185         rctx->blitter = util_blitter_create(&rctx->b.b);
 186         if (rctx->blitter == NULL)
 187                 goto fail;
 188
 189         rctx->dummy_pixel_shader =
 190                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 191                                                      TGSI_SEMANTIC_GENERIC,
 192                                                      TGSI_INTERPOLATE_CONSTANT);
 193         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 194
 195         /* these must be last */
 196         si_begin_new_cs(rctx);
 197         si_get_backend_mask(rctx);
 198
 199         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 200          * with a NULL buffer). We need to use a dummy buffer instead. */
 201         if (rctx->b.chip_class == CIK) {
 202                 rctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 203                                                                  PIPE_USAGE_STATIC, 16);
 204                 rctx->null_const_buf.buffer_size = rctx->null_const_buf.buffer->width0;
 205
 206                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 207                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 208                                 rctx->b.b.set_constant_buffer(&rctx->b.b, shader, i,
 209                                                               &rctx->null_const_buf);
 210                         }
 211                 }
 212
 213                 /* Clear the NULL constant buffer, because loads should return zeros. */
 214                 rctx->b.clear_buffer(&rctx->b.b, rctx->null_const_buf.buffer, 0,
 215                                      rctx->null_const_buf.buffer->width0, 0);
 216         }
 217
 218         return &rctx->b.b;
 219 fail:
 220         r600_destroy_context(&rctx->b.b);
 221         return NULL;
 222 }
 223
 224 /*
 225  * pipe_screen
 226  */
 227 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 228 {
 229         return "X.Org";
 230 }
 231
 232 const char *r600_get_llvm_processor_name(enum radeon_family family)
 233 {
 234         switch (family) {
 235                 case CHIP_TAHITI: return "tahiti";
 236                 case CHIP_PITCAIRN: return "pitcairn";
 237                 case CHIP_VERDE: return "verde";
 238                 case CHIP_OLAND: return "oland";
 239 #if HAVE_LLVM <= 0x0303
 240                 default: return "SI";
 241 #else
 242                 case CHIP_HAINAN: return "hainan";
 243                 case CHIP_BONAIRE: return "bonaire";
 244                 case CHIP_KABINI: return "kabini";
 245                 case CHIP_KAVERI: return "kaveri";
 246                 case CHIP_HAWAII: return "hawaii";
 247                 default: return "";
 248 #endif
 249         }
 250 }
 251
 252 static const char *r600_get_family_name(enum radeon_family family)
 253 {
 254         switch(family) {
 255         case CHIP_TAHITI: return "AMD TAHITI";
 256         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 257         case CHIP_VERDE: return "AMD CAPE VERDE";
 258         case CHIP_OLAND: return "AMD OLAND";
 259         case CHIP_HAINAN: return "AMD HAINAN";
 260         case CHIP_BONAIRE: return "AMD BONAIRE";
 261         case CHIP_KAVERI: return "AMD KAVERI";
 262         case CHIP_KABINI: return "AMD KABINI";
 263         case CHIP_HAWAII: return "AMD HAWAII";
 264         default: return "AMD unknown";
 265         }
 266 }
 267
 268 static const char* r600_get_name(struct pipe_screen* pscreen)
 269 {
 270         struct si_screen *rscreen = (struct si_screen *)pscreen;
 271
 272         return r600_get_family_name(rscreen->b.family);
 273 }
 274
 275 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 276 {
 277         struct si_screen *rscreen = (struct si_screen *)pscreen;
 278
 279         switch (param) {
 280         /* Supported features (boolean caps). */
 281         case PIPE_CAP_TWO_SIDED_STENCIL:
 282         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 283         case PIPE_CAP_ANISOTROPIC_FILTER:
 284         case PIPE_CAP_POINT_SPRITE:
 285         case PIPE_CAP_OCCLUSION_QUERY:
 286         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 287         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 288         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 289         case PIPE_CAP_TEXTURE_SWIZZLE:
 290         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 291         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 292         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 293         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 294         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 295         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 296         case PIPE_CAP_SM3:
 297         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 298         case PIPE_CAP_PRIMITIVE_RESTART:
 299         case PIPE_CAP_CONDITIONAL_RENDER:
 300         case PIPE_CAP_TEXTURE_BARRIER:
 301         case PIPE_CAP_INDEP_BLEND_ENABLE:
 302         case PIPE_CAP_INDEP_BLEND_FUNC:
 303         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 304         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 305         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 306         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 307         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 308         case PIPE_CAP_USER_INDEX_BUFFERS:
 309         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 310         case PIPE_CAP_START_INSTANCE:
 311         case PIPE_CAP_NPOT_TEXTURES:
 312         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 313         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 314         case PIPE_CAP_TGSI_INSTANCEID:
 315         case PIPE_CAP_COMPUTE:
 316         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 317         case PIPE_CAP_TGSI_VS_LAYER:
 318                 return 1;
 319
 320         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 321                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 322                 return HAVE_LLVM >= 0x0304 && (rscreen->b.chip_class < CIK ||
 323                                                rscreen->b.info.drm_minor >= 35);
 324
 325         case PIPE_CAP_TGSI_TEXCOORD:
 326                 return 0;
 327
 328         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 329                 return 64;
 330
 331         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 332                 return 256;
 333
 334         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 335                 return 140;
 336
 337         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 338                 return 1;
 339         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 340                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 341
 342         /* Unsupported features. */
 343         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 344         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 345         case PIPE_CAP_SCALED_RESOLVE:
 346         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 347         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 348         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 349         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 350         case PIPE_CAP_USER_VERTEX_BUFFERS:
 351         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 352         case PIPE_CAP_CUBE_MAP_ARRAY:
 353                 return 0;
 354
 355         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 356                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 357
 358         /* Stream output. */
 359         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 360                 return rscreen->b.has_streamout ? 4 : 0;
 361         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 362                 return rscreen->b.has_streamout ? 1 : 0;
 363         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 364         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 365                 return rscreen->b.has_streamout ? 32*4 : 0;
 366
 367         /* Texturing. */
 368         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 369         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 370         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 371                         return 15;
 372         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 373                 return 16384;
 374         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 375                 return 32;
 376
 377         /* Render targets. */
 378         case PIPE_CAP_MAX_RENDER_TARGETS:
 379                 return 8;
 380
 381         case PIPE_CAP_MAX_VIEWPORTS:
 382                 return 1;
 383
 384         /* Timer queries, present when the clock frequency is non zero. */
 385         case PIPE_CAP_QUERY_TIMESTAMP:
 386         case PIPE_CAP_QUERY_TIME_ELAPSED:
 387                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 388
 389         case PIPE_CAP_MIN_TEXEL_OFFSET:
 390                 return -8;
 391
 392         case PIPE_CAP_MAX_TEXEL_OFFSET:
 393                 return 7;
 394         case PIPE_CAP_ENDIANNESS:
 395                 return PIPE_ENDIAN_LITTLE;
 396         }
 397         return 0;
 398 }
 399
 400 static float r600_get_paramf(struct pipe_screen* pscreen,
 401                              enum pipe_capf param)
 402 {
 403         switch (param) {
 404         case PIPE_CAPF_MAX_LINE_WIDTH:
 405         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 406         case PIPE_CAPF_MAX_POINT_WIDTH:
 407         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 408                 return 16384.0f;
 409         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 410                 return 16.0f;
 411         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 412                 return 16.0f;
 413         case PIPE_CAPF_GUARD_BAND_LEFT:
 414         case PIPE_CAPF_GUARD_BAND_TOP:
 415         case PIPE_CAPF_GUARD_BAND_RIGHT:
 416         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 417                 return 0.0f;
 418         }
 419         return 0.0f;
 420 }
 421
 422 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 423 {
 424         switch(shader)
 425         {
 426         case PIPE_SHADER_FRAGMENT:
 427         case PIPE_SHADER_VERTEX:
 428                 break;
 429         case PIPE_SHADER_GEOMETRY:
 430                 /* TODO: support and enable geometry programs */
 431                 return 0;
 432         case PIPE_SHADER_COMPUTE:
 433                 switch (param) {
 434                 case PIPE_SHADER_CAP_PREFERRED_IR:
 435                         return PIPE_SHADER_IR_LLVM;
 436                 default:
 437                         return 0;
 438                 }
 439         default:
 440                 /* TODO: support tessellation */
 441                 return 0;
 442         }
 443
 444         switch (param) {
 445         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 446         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 447         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 448         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 449                 return 16384;
 450         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 451                 return 32;
 452         case PIPE_SHADER_CAP_MAX_INPUTS:
 453                 return 32;
 454         case PIPE_SHADER_CAP_MAX_TEMPS:
 455                 return 256; /* Max native temporaries. */
 456         case PIPE_SHADER_CAP_MAX_ADDRS:
 457                 /* FIXME Isn't this equal to TEMPS? */
 458                 return 1; /* Max native address registers */
 459         case PIPE_SHADER_CAP_MAX_CONSTS:
 460                 return 4096; /* actually only memory limits this */
 461         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 462                 return NUM_PIPE_CONST_BUFFERS;
 463         case PIPE_SHADER_CAP_MAX_PREDS:
 464                 return 0; /* FIXME */
 465         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 466                 return 1;
 467         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 468                 return 0;
 469         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 470         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 471         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 472         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 473                 return 1;
 474         case PIPE_SHADER_CAP_INTEGERS:
 475                 return 1;
 476         case PIPE_SHADER_CAP_SUBROUTINES:
 477                 return 0;
 478         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 479         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 480                 return 16;
 481         case PIPE_SHADER_CAP_PREFERRED_IR:
 482                 return PIPE_SHADER_IR_TGSI;
 483         }
 484         return 0;
 485 }
 486
 487 static int r600_get_video_param(struct pipe_screen *screen,
 488                                 enum pipe_video_profile profile,
 489                                 enum pipe_video_entrypoint entrypoint,
 490                                 enum pipe_video_cap param)
 491 {
 492         switch (param) {
 493         case PIPE_VIDEO_CAP_SUPPORTED:
 494                 return vl_profile_supported(screen, profile, entrypoint);
 495         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 496                 return 1;
 497         case PIPE_VIDEO_CAP_MAX_WIDTH:
 498         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 499                 return vl_video_buffer_max_size(screen);
 500         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 501                 return PIPE_FORMAT_NV12;
 502         case PIPE_VIDEO_CAP_MAX_LEVEL:
 503                 return vl_level_supported(screen, profile);
 504         default:
 505                 return 0;
 506         }
 507 }
 508
 509 static int r600_get_compute_param(struct pipe_screen *screen,
 510         enum pipe_compute_cap param,
 511         void *ret)
 512 {
 513         struct si_screen *rscreen = (struct si_screen *)screen;
 514         //TODO: select these params by asic
 515         switch (param) {
 516         case PIPE_COMPUTE_CAP_IR_TARGET: {
 517                 const char *gpu = r600_get_llvm_processor_name(rscreen->b.family);
 518                 if (ret) {
 519                         sprintf(ret, "%s-r600--", gpu);
 520                 }
 521                 return (8 + strlen(gpu)) * sizeof(char);
 522         }
 523         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 524                 if (ret) {
 525                         uint64_t * grid_dimension = ret;
 526                         grid_dimension[0] = 3;
 527                 }
 528                 return 1 * sizeof(uint64_t);
 529         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 530                 if (ret) {
 531                         uint64_t * grid_size = ret;
 532                         grid_size[0] = 65535;
 533                         grid_size[1] = 65535;
 534                         grid_size[2] = 1;
 535                 }
 536                 return 3 * sizeof(uint64_t) ;
 537
 538         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 539                 if (ret) {
 540                         uint64_t * block_size = ret;
 541                         block_size[0] = 256;
 542                         block_size[1] = 256;
 543                         block_size[2] = 256;
 544                 }
 545                 return 3 * sizeof(uint64_t);
 546         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 547                 if (ret) {
 548                         uint64_t * max_threads_per_block = ret;
 549                         *max_threads_per_block = 256;
 550                 }
 551                 return sizeof(uint64_t);
 552
 553         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 554                 if (ret) {
 555                         uint64_t *max_global_size = ret;
 556                         /* XXX: Not sure what to put here. */
 557                         *max_global_size = 2000000000;
 558                 }
 559                 return sizeof(uint64_t);
 560         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 561                 if (ret) {
 562                         uint64_t *max_local_size = ret;
 563                         /* Value reported by the closed source driver. */
 564                         *max_local_size = 32768;
 565                 }
 566                 return sizeof(uint64_t);
 567         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 568                 if (ret) {
 569                         uint64_t *max_input_size = ret;
 570                         /* Value reported by the closed source driver. */
 571                         *max_input_size = 1024;
 572                 }
 573                 return sizeof(uint64_t);
 574         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 575                 if (ret) {
 576                         uint64_t max_global_size;
 577                         uint64_t *max_mem_alloc_size = ret;
 578                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 579                         *max_mem_alloc_size = max_global_size / 4;
 580                 }
 581                 return sizeof(uint64_t);
 582         default:
 583                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 584                 return 0;
 585         }
 586 }
 587
 588 static void r600_destroy_screen(struct pipe_screen* pscreen)
 589 {
 590         struct si_screen *rscreen = (struct si_screen *)pscreen;
 591
 592         if (rscreen == NULL)
 593                 return;
 594
 595         if (!radeon_winsys_unref(rscreen->b.ws))
 596                 return;
 597
 598         r600_common_screen_cleanup(&rscreen->b);
 599
 600 #if R600_TRACE_CS
 601         if (rscreen->trace_bo) {
 602                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 603                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 604         }
 605 #endif
 606
 607         rscreen->b.ws->destroy(rscreen->b.ws);
 608         FREE(rscreen);
 609 }
 610
 611 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 612 {
 613         struct si_screen *rscreen = (struct si_screen*)screen;
 614
 615         return 1000000 * rscreen->b.ws->query_value(rscreen->b.ws, RADEON_TIMESTAMP) /
 616                 rscreen->b.info.r600_clock_crystal_freq;
 617 }
 618
 619 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 620 {
 621         struct si_screen *rscreen = CALLOC_STRUCT(si_screen);
 622         if (rscreen == NULL) {
 623                 return NULL;
 624         }
 625
 626         ws->query_info(ws, &rscreen->b.info);
 627
 628         /* Set functions first. */
 629         rscreen->b.b.context_create = r600_create_context;
 630         rscreen->b.b.destroy = r600_destroy_screen;
 631         rscreen->b.b.get_name = r600_get_name;
 632         rscreen->b.b.get_vendor = r600_get_vendor;
 633         rscreen->b.b.get_param = r600_get_param;
 634         rscreen->b.b.get_shader_param = r600_get_shader_param;
 635         rscreen->b.b.get_paramf = r600_get_paramf;
 636         rscreen->b.b.get_compute_param = r600_get_compute_param;
 637         rscreen->b.b.get_timestamp = r600_get_timestamp;
 638         rscreen->b.b.is_format_supported = si_is_format_supported;
 639         if (rscreen->b.info.has_uvd) {
 640                 rscreen->b.b.get_video_param = ruvd_get_video_param;
 641                 rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
 642         } else {
 643                 rscreen->b.b.get_video_param = r600_get_video_param;
 644                 rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
 645         }
 646         r600_init_screen_resource_functions(&rscreen->b.b);
 647
 648         if (!r600_common_screen_init(&rscreen->b, ws)) {
 649                 FREE(rscreen);
 650                 return NULL;
 651         }
 652
 653         rscreen->b.has_cp_dma = true;
 654         rscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 655
 656         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 657                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 658
 659 #if R600_TRACE_CS
 660         rscreen->cs_count = 0;
 661         if (rscreen->info.drm_minor >= 28) {
 662                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
 663                                                                                 PIPE_BIND_CUSTOM,
 664                                                                                 PIPE_USAGE_STAGING,
 665                                                                                 4096);
 666                 if (rscreen->trace_bo) {
 667                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 668                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 669                 }
 670         }
 671 #endif
 672
 673         /* Create the auxiliary context. This must be done last. */
 674         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 675
 676         return &rscreen->b.b;
 677 }