src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_log.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_suballoc.h"
  34 #include "util/u_tests.h"
  35 #include "util/xmlconfig.h"
  36 #include "vl/vl_decoder.h"
  37 #include "../ddebug/dd_util.h"
  38
  39 #include "compiler/nir/nir.h"
  40
  41 /*
  42  * pipe_context
  43  */
  44 static void si_destroy_context(struct pipe_context *context)
  45 {
  46         struct si_context *sctx = (struct si_context *)context;
  47         int i;
  48
  49         /* Unreference the framebuffer normally to disable related logic
  50          * properly.
  51          */
  52         struct pipe_framebuffer_state fb = {};
  53         if (context->set_framebuffer_state)
  54                 context->set_framebuffer_state(context, &fb);
  55
  56         si_release_all_descriptors(sctx);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_fmask_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  83         if (sctx->custom_blend_eliminate_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87         if (sctx->vs_blit_pos)
  88                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos);
  89         if (sctx->vs_blit_pos_layered)
  90                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos_layered);
  91         if (sctx->vs_blit_color)
  92                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color);
  93         if (sctx->vs_blit_color_layered)
  94                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color_layered);
  95         if (sctx->vs_blit_texcoord)
  96                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_texcoord);
  97
  98         if (sctx->blitter)
  99                 util_blitter_destroy(sctx->blitter);
 100
 101         si_common_context_cleanup(&sctx->b);
 102
 103         LLVMDisposeTargetMachine(sctx->tm);
 104
 105         si_saved_cs_reference(&sctx->current_saved_cs, NULL);
 106
 107         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 108         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 109
 110         util_dynarray_fini(&sctx->resident_tex_handles);
 111         util_dynarray_fini(&sctx->resident_img_handles);
 112         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 113         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 114         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 115         FREE(sctx);
 116 }
 117
 118 static enum pipe_reset_status
 119 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 120 {
 121         struct si_context *sctx = (struct si_context *)ctx;
 122
 123         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 124 }
 125
 126 /* Apitrace profiling:
 127  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 128  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 129  *      and remember its number.
 130  *   3) In Mesa, enable queries and performance counters around that draw
 131  *      call and print the results.
 132  *   4) glretrace --benchmark --markers ..
 133  */
 134 static void si_emit_string_marker(struct pipe_context *ctx,
 135                                   const char *string, int len)
 136 {
 137         struct si_context *sctx = (struct si_context *)ctx;
 138
 139         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 140
 141         if (sctx->b.log)
 142                 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
 143 }
 144
 145 static LLVMTargetMachineRef
 146 si_create_llvm_target_machine(struct si_screen *sscreen)
 147 {
 148         enum ac_target_machine_options tm_options =
 149                 (sscreen->b.debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
 150                 (sscreen->b.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
 151                 (sscreen->b.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
 152                 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
 153
 154         return ac_create_target_machine(sscreen->b.family, tm_options);
 155 }
 156
 157 static void si_set_debug_callback(struct pipe_context *ctx,
 158                                   const struct pipe_debug_callback *cb)
 159 {
 160         struct si_context *sctx = (struct si_context *)ctx;
 161         struct si_screen *screen = sctx->screen;
 162
 163         util_queue_finish(&screen->shader_compiler_queue);
 164         util_queue_finish(&screen->shader_compiler_queue_low_priority);
 165
 166         if (cb)
 167                 sctx->debug = *cb;
 168         else
 169                 memset(&sctx->debug, 0, sizeof(sctx->debug));
 170 }
 171
 172 static void si_set_log_context(struct pipe_context *ctx,
 173                                struct u_log_context *log)
 174 {
 175         struct si_context *sctx = (struct si_context *)ctx;
 176         sctx->b.log = log;
 177
 178         if (log)
 179                 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
 180 }
 181
 182 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 183                                               unsigned flags)
 184 {
 185         struct si_context *sctx = CALLOC_STRUCT(si_context);
 186         struct si_screen* sscreen = (struct si_screen *)screen;
 187         struct radeon_winsys *ws = sscreen->b.ws;
 188         int shader, i;
 189
 190         if (!sctx)
 191                 return NULL;
 192
 193         if (flags & PIPE_CONTEXT_DEBUG)
 194                 sscreen->record_llvm_ir = true; /* racy but not critical */
 195
 196         sctx->b.b.screen = screen; /* this must be set first */
 197         sctx->b.b.priv = NULL;
 198         sctx->b.b.destroy = si_destroy_context;
 199         sctx->b.b.emit_string_marker = si_emit_string_marker;
 200         sctx->b.b.set_debug_callback = si_set_debug_callback;
 201         sctx->b.b.set_log_context = si_set_log_context;
 202         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 203         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 204         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 205
 206         if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
 207                 goto fail;
 208
 209         if (sscreen->b.info.drm_major == 3)
 210                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 211
 212         si_init_blit_functions(sctx);
 213         si_init_compute_functions(sctx);
 214         si_init_cp_dma_functions(sctx);
 215         si_init_debug_functions(sctx);
 216         si_init_msaa_functions(sctx);
 217         si_init_streamout_functions(sctx);
 218
 219         if (sscreen->b.info.has_hw_decode) {
 220                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 221                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 222         } else {
 223                 sctx->b.b.create_video_codec = vl_create_decoder;
 224                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 225         }
 226
 227         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 228                                        si_context_gfx_flush, sctx);
 229         sctx->b.gfx.flush = si_context_gfx_flush;
 230
 231         /* Border colors. */
 232         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 233                                           sizeof(*sctx->border_color_table));
 234         if (!sctx->border_color_table)
 235                 goto fail;
 236
 237         sctx->border_color_buffer = (struct r600_resource*)
 238                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 239                                    SI_MAX_BORDER_COLORS *
 240                                    sizeof(*sctx->border_color_table));
 241         if (!sctx->border_color_buffer)
 242                 goto fail;
 243
 244         sctx->border_color_map =
 245                 ws->buffer_map(sctx->border_color_buffer->buf,
 246                                NULL, PIPE_TRANSFER_WRITE);
 247         if (!sctx->border_color_map)
 248                 goto fail;
 249
 250         si_init_all_descriptors(sctx);
 251         si_init_fence_functions(sctx);
 252         si_init_state_functions(sctx);
 253         si_init_shader_functions(sctx);
 254         si_init_viewport_functions(sctx);
 255         si_init_ia_multi_vgt_param_table(sctx);
 256
 257         if (sctx->b.chip_class >= CIK)
 258                 cik_init_sdma_functions(sctx);
 259         else
 260                 si_init_dma_functions(sctx);
 261
 262         if (sscreen->b.debug_flags & DBG(FORCE_DMA))
 263                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 264
 265         sctx->blitter = util_blitter_create(&sctx->b.b);
 266         if (sctx->blitter == NULL)
 267                 goto fail;
 268         sctx->blitter->draw_rectangle = si_draw_rectangle;
 269         sctx->blitter->skip_viewport_restore = true;
 270
 271         sctx->sample_mask.sample_mask = 0xffff;
 272
 273         /* these must be last */
 274         si_begin_new_cs(sctx);
 275
 276         if (sctx->b.chip_class >= GFX9) {
 277                 sctx->wait_mem_scratch = (struct r600_resource*)
 278                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 279                 if (!sctx->wait_mem_scratch)
 280                         goto fail;
 281
 282                 /* Initialize the memory. */
 283                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 284                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 285                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 286                             S_370_WR_CONFIRM(1) |
 287                             S_370_ENGINE_SEL(V_370_ME));
 288                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 289                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 290                 radeon_emit(cs, sctx->wait_mem_number);
 291         }
 292
 293         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 294          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 295         if (sctx->b.chip_class == CIK) {
 296                 sctx->null_const_buf.buffer =
 297                         si_aligned_buffer_create(screen,
 298                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 299                                                    PIPE_USAGE_DEFAULT, 16,
 300                                                    sctx->screen->b.info.tcc_cache_line_size);
 301                 if (!sctx->null_const_buf.buffer)
 302                         goto fail;
 303                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 304
 305                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 306                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 307                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 308                                                               &sctx->null_const_buf);
 309                         }
 310                 }
 311
 312                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 313                                  &sctx->null_const_buf);
 314                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 315                                  &sctx->null_const_buf);
 316                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 317                                  &sctx->null_const_buf);
 318                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 319                                  &sctx->null_const_buf);
 320                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 321                                  &sctx->null_const_buf);
 322
 323                 /* Clear the NULL constant buffer, because loads should return zeros. */
 324                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 325                                      sctx->null_const_buf.buffer->width0, 0,
 326                                      R600_COHERENCY_SHADER);
 327         }
 328
 329         uint64_t max_threads_per_block;
 330         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 331                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 332                                   &max_threads_per_block);
 333
 334         /* The maximum number of scratch waves. Scratch space isn't divided
 335          * evenly between CUs. The number is only a function of the number of CUs.
 336          * We can decrease the constant to decrease the scratch buffer size.
 337          *
 338          * sctx->scratch_waves must be >= the maximum posible size of
 339          * 1 threadgroup, so that the hw doesn't hang from being unable
 340          * to start any.
 341          *
 342          * The recommended value is 4 per CU at most. Higher numbers don't
 343          * bring much benefit, but they still occupy chip resources (think
 344          * async compute). I've seen ~2% performance difference between 4 and 32.
 345          */
 346         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 347                                    max_threads_per_block / 64);
 348
 349         sctx->tm = si_create_llvm_target_machine(sscreen);
 350
 351         /* Bindless handles. */
 352         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 353                                                     _mesa_key_pointer_equal);
 354         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 355                                                     _mesa_key_pointer_equal);
 356
 357         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 358         util_dynarray_init(&sctx->resident_img_handles, NULL);
 359         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 360         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 361         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 362
 363         return &sctx->b.b;
 364 fail:
 365         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 366         si_destroy_context(&sctx->b.b);
 367         return NULL;
 368 }
 369
 370 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 371                                                    void *priv, unsigned flags)
 372 {
 373         struct si_screen *sscreen = (struct si_screen *)screen;
 374         struct pipe_context *ctx;
 375
 376         if (sscreen->b.debug_flags & DBG(CHECK_VM))
 377                 flags |= PIPE_CONTEXT_DEBUG;
 378
 379         ctx = si_create_context(screen, flags);
 380
 381         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 382                 return ctx;
 383
 384         /* Clover (compute-only) is unsupported. */
 385         if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
 386                 return ctx;
 387
 388         /* When shaders are logged to stderr, asynchronous compilation is
 389          * disabled too. */
 390         if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
 391                 return ctx;
 392
 393         /* Use asynchronous flushes only on amdgpu, since the radeon
 394          * implementation for fence_server_sync is incomplete. */
 395         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 396                                        si_replace_buffer_storage,
 397                                        sscreen->b.info.drm_major >= 3 ? si_create_fence : NULL,
 398                                        &((struct si_context*)ctx)->b.tc);
 399 }
 400
 401 /*
 402  * pipe_screen
 403  */
 404 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 405 {
 406         /* Old kernels disallowed some register writes for SI
 407          * that are used for indirect dispatches. */
 408         return (sscreen->b.chip_class >= CIK ||
 409                 sscreen->b.info.drm_major == 3 ||
 410                 (sscreen->b.info.drm_major == 2 &&
 411                  sscreen->b.info.drm_minor >= 45));
 412 }
 413
 414 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 415 {
 416         struct si_screen *sscreen = (struct si_screen *)pscreen;
 417
 418         switch (param) {
 419         /* Supported features (boolean caps). */
 420         case PIPE_CAP_ACCELERATED:
 421         case PIPE_CAP_TWO_SIDED_STENCIL:
 422         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 423         case PIPE_CAP_ANISOTROPIC_FILTER:
 424         case PIPE_CAP_POINT_SPRITE:
 425         case PIPE_CAP_OCCLUSION_QUERY:
 426         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 427         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 428         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 429         case PIPE_CAP_TEXTURE_SWIZZLE:
 430         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 431         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 432         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 433         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 434         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 435         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 436         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 437         case PIPE_CAP_SM3:
 438         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 439         case PIPE_CAP_PRIMITIVE_RESTART:
 440         case PIPE_CAP_CONDITIONAL_RENDER:
 441         case PIPE_CAP_TEXTURE_BARRIER:
 442         case PIPE_CAP_INDEP_BLEND_ENABLE:
 443         case PIPE_CAP_INDEP_BLEND_FUNC:
 444         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 445         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 446         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 447         case PIPE_CAP_START_INSTANCE:
 448         case PIPE_CAP_NPOT_TEXTURES:
 449         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 450         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 451         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 452         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 453         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 454         case PIPE_CAP_TGSI_INSTANCEID:
 455         case PIPE_CAP_COMPUTE:
 456         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 457         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 458         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 459         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 460         case PIPE_CAP_CUBE_MAP_ARRAY:
 461         case PIPE_CAP_SAMPLE_SHADING:
 462         case PIPE_CAP_DRAW_INDIRECT:
 463         case PIPE_CAP_CLIP_HALFZ:
 464         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 465         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 466         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 467         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 468         case PIPE_CAP_TGSI_TEXCOORD:
 469         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 470         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 471         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 472         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 473         case PIPE_CAP_SHAREABLE_SHADERS:
 474         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 475         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 476         case PIPE_CAP_TEXTURE_QUERY_LOD:
 477         case PIPE_CAP_TEXTURE_GATHER_SM5:
 478         case PIPE_CAP_TGSI_TXQS:
 479         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 480         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 481         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 482         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 483         case PIPE_CAP_INVALIDATE_BUFFER:
 484         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 485         case PIPE_CAP_QUERY_MEMORY_INFO:
 486         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 487         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 488         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 489         case PIPE_CAP_GENERATE_MIPMAP:
 490         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 491         case PIPE_CAP_STRING_MARKER:
 492         case PIPE_CAP_CLEAR_TEXTURE:
 493         case PIPE_CAP_CULL_DISTANCE:
 494         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 495         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 496         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 497         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 498         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 499         case PIPE_CAP_DOUBLES:
 500         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 501         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 502         case PIPE_CAP_BINDLESS_TEXTURE:
 503         case PIPE_CAP_QUERY_TIMESTAMP:
 504         case PIPE_CAP_QUERY_TIME_ELAPSED:
 505         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 506         case PIPE_CAP_QUERY_SO_OVERFLOW:
 507         case PIPE_CAP_MEMOBJ:
 508         case PIPE_CAP_LOAD_CONSTBUF:
 509         case PIPE_CAP_INT64:
 510         case PIPE_CAP_INT64_DIVMOD:
 511         case PIPE_CAP_TGSI_CLOCK:
 512         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 513         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 514         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 515         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 516                 return 1;
 517
 518         case PIPE_CAP_TGSI_VOTE:
 519                 return HAVE_LLVM >= 0x0400;
 520
 521         case PIPE_CAP_TGSI_BALLOT:
 522                 return HAVE_LLVM >= 0x0500;
 523
 524         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 525                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 526
 527         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 528                 return (sscreen->b.info.drm_major == 2 &&
 529                         sscreen->b.info.drm_minor >= 43) ||
 530                        sscreen->b.info.drm_major == 3;
 531
 532         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 533                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 534                 return sscreen->b.chip_class < CIK ||
 535                        (sscreen->b.info.drm_major == 2 &&
 536                         sscreen->b.info.drm_minor >= 35) ||
 537                        sscreen->b.info.drm_major == 3;
 538
 539         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 540                 return R600_MAP_BUFFER_ALIGNMENT;
 541
 542         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 543         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 544         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 545         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 546         case PIPE_CAP_MAX_VERTEX_STREAMS:
 547         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 548                 return 4;
 549
 550         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 551                 if (sscreen->b.debug_flags & DBG(NIR))
 552                         return 140; /* no geometry and tessellation shaders yet */
 553                 if (si_have_tgsi_compute(sscreen))
 554                         return 450;
 555                 return 420;
 556
 557         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 558                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 559
 560         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 561         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 562         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 563                 /* SI doesn't support unaligned loads.
 564                  * CIK needs DRM 2.50.0 on radeon. */
 565                 return sscreen->b.chip_class == SI ||
 566                        (sscreen->b.info.drm_major == 2 &&
 567                         sscreen->b.info.drm_minor < 50);
 568
 569         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 570                 /* TODO: GFX9 hangs. */
 571                 if (sscreen->b.chip_class >= GFX9)
 572                         return 0;
 573                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 574                  * faults are mitigated in software.
 575                  */
 576                 if (sscreen->b.chip_class >= CIK &&
 577                     sscreen->b.info.drm_major == 3 &&
 578                     sscreen->b.info.drm_minor >= 13)
 579                         return RADEON_SPARSE_PAGE_SIZE;
 580                 return 0;
 581
 582         /* Unsupported features. */
 583         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 584         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 585         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 586         case PIPE_CAP_USER_VERTEX_BUFFERS:
 587         case PIPE_CAP_FAKE_SW_MSAA:
 588         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 589         case PIPE_CAP_VERTEXID_NOBASE:
 590         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 591         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 592         case PIPE_CAP_TGSI_FS_FBFETCH:
 593         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 594         case PIPE_CAP_UMA:
 595         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 596         case PIPE_CAP_POST_DEPTH_COVERAGE:
 597         case PIPE_CAP_TILE_RASTER_ORDER:
 598         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 599                 return 0;
 600
 601         case PIPE_CAP_NATIVE_FENCE_FD:
 602                 return sscreen->b.info.has_sync_file;
 603
 604         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 605                 return si_have_tgsi_compute(sscreen);
 606
 607         case PIPE_CAP_DRAW_PARAMETERS:
 608         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 609         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 610                 return sscreen->has_draw_indirect_multi;
 611
 612         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 613                 return 30;
 614
 615         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 616                 return sscreen->b.chip_class <= VI ?
 617                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 618
 619         /* Stream output. */
 620         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 621         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 622                 return 32*4;
 623
 624         /* Geometry shader output. */
 625         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 626                 return 1024;
 627         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 628                 return 4095;
 629
 630         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 631                 return 2048;
 632
 633         /* Texturing. */
 634         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 635         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 636                 return 15; /* 16384 */
 637         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 638                 /* textures support 8192, but layered rendering supports 2048 */
 639                 return 12;
 640         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 641                 /* textures support 8192, but layered rendering supports 2048 */
 642                 return 2048;
 643
 644         /* Viewports and render targets. */
 645         case PIPE_CAP_MAX_VIEWPORTS:
 646                 return SI_MAX_VIEWPORTS;
 647         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 648         case PIPE_CAP_MAX_RENDER_TARGETS:
 649                 return 8;
 650
 651         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 652         case PIPE_CAP_MIN_TEXEL_OFFSET:
 653                 return -32;
 654
 655         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 656         case PIPE_CAP_MAX_TEXEL_OFFSET:
 657                 return 31;
 658
 659         case PIPE_CAP_ENDIANNESS:
 660                 return PIPE_ENDIAN_LITTLE;
 661
 662         case PIPE_CAP_VENDOR_ID:
 663                 return ATI_VENDOR_ID;
 664         case PIPE_CAP_DEVICE_ID:
 665                 return sscreen->b.info.pci_id;
 666         case PIPE_CAP_VIDEO_MEMORY:
 667                 return sscreen->b.info.vram_size >> 20;
 668         case PIPE_CAP_PCI_GROUP:
 669                 return sscreen->b.info.pci_domain;
 670         case PIPE_CAP_PCI_BUS:
 671                 return sscreen->b.info.pci_bus;
 672         case PIPE_CAP_PCI_DEVICE:
 673                 return sscreen->b.info.pci_dev;
 674         case PIPE_CAP_PCI_FUNCTION:
 675                 return sscreen->b.info.pci_func;
 676         }
 677         return 0;
 678 }
 679
 680 static int si_get_shader_param(struct pipe_screen* pscreen,
 681                                enum pipe_shader_type shader,
 682                                enum pipe_shader_cap param)
 683 {
 684         struct si_screen *sscreen = (struct si_screen *)pscreen;
 685
 686         switch(shader)
 687         {
 688         case PIPE_SHADER_FRAGMENT:
 689         case PIPE_SHADER_VERTEX:
 690         case PIPE_SHADER_GEOMETRY:
 691         case PIPE_SHADER_TESS_CTRL:
 692         case PIPE_SHADER_TESS_EVAL:
 693                 break;
 694         case PIPE_SHADER_COMPUTE:
 695                 switch (param) {
 696                 case PIPE_SHADER_CAP_PREFERRED_IR:
 697                         return PIPE_SHADER_IR_NATIVE;
 698
 699                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 700                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 701
 702                         if (si_have_tgsi_compute(sscreen))
 703                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 704
 705                         return ir;
 706                 }
 707
 708                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 709                         uint64_t max_const_buffer_size;
 710                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 711                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 712                                 &max_const_buffer_size);
 713                         return MIN2(max_const_buffer_size, INT_MAX);
 714                 }
 715                 default:
 716                         /* If compute shaders don't require a special value
 717                          * for this cap, we can return the same value we
 718                          * do for other shader types. */
 719                         break;
 720                 }
 721                 break;
 722         default:
 723                 return 0;
 724         }
 725
 726         switch (param) {
 727         /* Shader limits. */
 728         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 729         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 730         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 731         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 732         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 733                 return 16384;
 734         case PIPE_SHADER_CAP_MAX_INPUTS:
 735                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 736         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 737                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 738         case PIPE_SHADER_CAP_MAX_TEMPS:
 739                 return 256; /* Max native temporaries. */
 740         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 741                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 742         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 743                 return SI_NUM_CONST_BUFFERS;
 744         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 745         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 746                 return SI_NUM_SAMPLERS;
 747         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 748                 return SI_NUM_SHADER_BUFFERS;
 749         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 750                 return SI_NUM_IMAGES;
 751         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 752                 return 32;
 753         case PIPE_SHADER_CAP_PREFERRED_IR:
 754                 if (sscreen->b.debug_flags & DBG(NIR) &&
 755                     (shader == PIPE_SHADER_VERTEX ||
 756                      shader == PIPE_SHADER_FRAGMENT))
 757                         return PIPE_SHADER_IR_NIR;
 758                 return PIPE_SHADER_IR_TGSI;
 759         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 760                 return 4;
 761
 762         /* Supported boolean features. */
 763         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 764         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 765         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 766         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 767         case PIPE_SHADER_CAP_INTEGERS:
 768         case PIPE_SHADER_CAP_INT64_ATOMICS:
 769         case PIPE_SHADER_CAP_FP16:
 770         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 771         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 772         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 773         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 774         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 775         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 776                 return 1;
 777
 778         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 779                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 780                 return shader != PIPE_SHADER_GEOMETRY &&
 781                        (sscreen->llvm_has_working_vgpr_indexing ||
 782                         /* TCS and TES load inputs directly from LDS or
 783                          * offchip memory, so indirect indexing is trivial. */
 784                         shader == PIPE_SHADER_TESS_CTRL ||
 785                         shader == PIPE_SHADER_TESS_EVAL);
 786
 787         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 788                 return sscreen->llvm_has_working_vgpr_indexing ||
 789                        /* TCS stores outputs directly to memory. */
 790                        shader == PIPE_SHADER_TESS_CTRL;
 791
 792         /* Unsupported boolean features. */
 793         case PIPE_SHADER_CAP_SUBROUTINES:
 794         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 795         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 796         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 797                 return 0;
 798         }
 799         return 0;
 800 }
 801
 802 static const struct nir_shader_compiler_options nir_options = {
 803         .vertex_id_zero_based = true,
 804         .lower_scmp = true,
 805         .lower_flrp32 = true,
 806         .lower_fsat = true,
 807         .lower_fdiv = true,
 808         .lower_sub = true,
 809         .lower_ffma = true,
 810         .lower_pack_snorm_2x16 = true,
 811         .lower_pack_snorm_4x8 = true,
 812         .lower_pack_unorm_2x16 = true,
 813         .lower_pack_unorm_4x8 = true,
 814         .lower_unpack_snorm_2x16 = true,
 815         .lower_unpack_snorm_4x8 = true,
 816         .lower_unpack_unorm_2x16 = true,
 817         .lower_unpack_unorm_4x8 = true,
 818         .lower_extract_byte = true,
 819         .lower_extract_word = true,
 820         .max_unroll_iterations = 32,
 821         .native_integers = true,
 822 };
 823
 824 static const void *
 825 si_get_compiler_options(struct pipe_screen *screen,
 826                         enum pipe_shader_ir ir,
 827                         enum pipe_shader_type shader)
 828 {
 829         assert(ir == PIPE_SHADER_IR_NIR);
 830         return &nir_options;
 831 }
 832
 833 static void si_destroy_screen(struct pipe_screen* pscreen)
 834 {
 835         struct si_screen *sscreen = (struct si_screen *)pscreen;
 836         struct si_shader_part *parts[] = {
 837                 sscreen->vs_prologs,
 838                 sscreen->tcs_epilogs,
 839                 sscreen->gs_prologs,
 840                 sscreen->ps_prologs,
 841                 sscreen->ps_epilogs
 842         };
 843         unsigned i;
 844
 845         if (!sscreen->b.ws->unref(sscreen->b.ws))
 846                 return;
 847
 848         util_queue_destroy(&sscreen->shader_compiler_queue);
 849         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 850
 851         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 852                 if (sscreen->tm[i])
 853                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 854
 855         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 856                 if (sscreen->tm_low_priority[i])
 857                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 858
 859         /* Free shader parts. */
 860         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 861                 while (parts[i]) {
 862                         struct si_shader_part *part = parts[i];
 863
 864                         parts[i] = part->next;
 865                         si_radeon_shader_binary_clean(&part->binary);
 866                         FREE(part);
 867                 }
 868         }
 869         mtx_destroy(&sscreen->shader_parts_mutex);
 870         si_destroy_shader_cache(sscreen);
 871         si_destroy_common_screen(&sscreen->b);
 872 }
 873
 874 static bool si_init_gs_info(struct si_screen *sscreen)
 875 {
 876         /* gs_table_depth is not used by GFX9 */
 877         if (sscreen->b.chip_class >= GFX9)
 878                 return true;
 879
 880         switch (sscreen->b.family) {
 881         case CHIP_OLAND:
 882         case CHIP_HAINAN:
 883         case CHIP_KAVERI:
 884         case CHIP_KABINI:
 885         case CHIP_MULLINS:
 886         case CHIP_ICELAND:
 887         case CHIP_CARRIZO:
 888         case CHIP_STONEY:
 889                 sscreen->gs_table_depth = 16;
 890                 return true;
 891         case CHIP_TAHITI:
 892         case CHIP_PITCAIRN:
 893         case CHIP_VERDE:
 894         case CHIP_BONAIRE:
 895         case CHIP_HAWAII:
 896         case CHIP_TONGA:
 897         case CHIP_FIJI:
 898         case CHIP_POLARIS10:
 899         case CHIP_POLARIS11:
 900         case CHIP_POLARIS12:
 901                 sscreen->gs_table_depth = 32;
 902                 return true;
 903         default:
 904                 return false;
 905         }
 906 }
 907
 908 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 909 {
 910         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 911         unsigned i;
 912
 913         if (!family)
 914                 return;
 915
 916         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 917                 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
 918                         /* Override family and chip_class. */
 919                         sscreen->b.family = sscreen->b.info.family = i;
 920
 921                         if (i >= CHIP_VEGA10)
 922                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 923                         else if (i >= CHIP_TONGA)
 924                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 925                         else if (i >= CHIP_BONAIRE)
 926                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 927                         else
 928                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 929
 930                         /* Don't submit any IBs. */
 931                         setenv("RADEON_NOOP", "1", 1);
 932                         return;
 933                 }
 934         }
 935
 936         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 937         exit(1);
 938 }
 939
 940 static void si_test_vmfault(struct si_screen *sscreen)
 941 {
 942         struct pipe_context *ctx = sscreen->b.aux_context;
 943         struct si_context *sctx = (struct si_context *)ctx;
 944         struct pipe_resource *buf =
 945                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 946
 947         if (!buf) {
 948                 puts("Buffer allocation failed.");
 949                 exit(1);
 950         }
 951
 952         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 953
 954         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_CP)) {
 955                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 956                 ctx->flush(ctx, NULL, 0);
 957                 puts("VM fault test: CP - done.");
 958         }
 959         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SDMA)) {
 960                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 961                 ctx->flush(ctx, NULL, 0);
 962                 puts("VM fault test: SDMA - done.");
 963         }
 964         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SHADER)) {
 965                 util_test_constant_buffer(ctx, buf);
 966                 puts("VM fault test: Shader - done.");
 967         }
 968         exit(0);
 969 }
 970
 971 static void radeonsi_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 972 {
 973         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 974 }
 975
 976 static void radeonsi_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 977 {
 978         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 979
 980         ac_compute_device_uuid(&rscreen->info, uuid, PIPE_UUID_SIZE);
 981 }
 982
 983 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 984                                            const struct pipe_screen_config *config)
 985 {
 986         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 987         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 988
 989         if (!sscreen) {
 990                 return NULL;
 991         }
 992
 993         /* Set functions first. */
 994         sscreen->b.b.context_create = si_pipe_create_context;
 995         sscreen->b.b.destroy = si_destroy_screen;
 996         sscreen->b.b.get_param = si_get_param;
 997         sscreen->b.b.get_shader_param = si_get_shader_param;
 998         sscreen->b.b.get_compiler_options = si_get_compiler_options;
 999         sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
1000         sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
1001         sscreen->b.b.resource_create = si_resource_create_common;
1002
1003         si_init_screen_fence_functions(sscreen);
1004         si_init_screen_state_functions(sscreen);
1005
1006         /* Set these flags in debug_flags early, so that the shader cache takes
1007          * them into account.
1008          */
1009         if (driQueryOptionb(config->options,
1010                             "glsl_correct_derivatives_after_discard"))
1011                 sscreen->b.debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1012         if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
1013                 sscreen->b.debug_flags |= DBG(SI_SCHED);
1014
1015         if (!si_common_screen_init(&sscreen->b, ws) ||
1016             !si_init_gs_info(sscreen) ||
1017             !si_init_shader_cache(sscreen)) {
1018                 FREE(sscreen);
1019                 return NULL;
1020         }
1021
1022         /* Only enable as many threads as we have target machines, but at most
1023          * the number of CPUs - 1 if there is more than one.
1024          */
1025         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
1026         num_threads = MAX2(1, num_threads - 1);
1027         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1028         num_compiler_threads_lowprio =
1029                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1030
1031         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1032                              32, num_compiler_threads,
1033                              UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1034                 si_destroy_shader_cache(sscreen);
1035                 FREE(sscreen);
1036                 return NULL;
1037         }
1038
1039         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1040                              "si_shader_low",
1041                              32, num_compiler_threads_lowprio,
1042                              UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1043                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1044                si_destroy_shader_cache(sscreen);
1045                FREE(sscreen);
1046                return NULL;
1047         }
1048
1049         si_handle_env_var_force_family(sscreen);
1050
1051         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1052                 si_init_perfcounters(sscreen);
1053
1054         /* Hawaii has a bug with offchip buffers > 256 that can be worked
1055          * around by setting 4K granularity.
1056          */
1057         sscreen->tess_offchip_block_dw_size =
1058                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1059
1060         /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1061          * on SI. */
1062         sscreen->has_clear_state = sscreen->b.chip_class >= CIK;
1063
1064         sscreen->has_distributed_tess =
1065                 sscreen->b.chip_class >= VI &&
1066                 sscreen->b.info.max_se >= 2;
1067
1068         sscreen->has_draw_indirect_multi =
1069                 (sscreen->b.family >= CHIP_POLARIS10) ||
1070                 (sscreen->b.chip_class == VI &&
1071                  sscreen->b.info.pfp_fw_version >= 121 &&
1072                  sscreen->b.info.me_fw_version >= 87) ||
1073                 (sscreen->b.chip_class == CIK &&
1074                  sscreen->b.info.pfp_fw_version >= 211 &&
1075                  sscreen->b.info.me_fw_version >= 173) ||
1076                 (sscreen->b.chip_class == SI &&
1077                  sscreen->b.info.pfp_fw_version >= 79 &&
1078                  sscreen->b.info.me_fw_version >= 142);
1079
1080         sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
1081                                          sscreen->b.info.max_se >= 2 &&
1082                                          !(sscreen->b.debug_flags & DBG(NO_OUT_OF_ORDER));
1083         sscreen->assume_no_z_fights =
1084                 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1085         sscreen->commutative_blend_add =
1086                 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1087         sscreen->clear_db_cache_before_clear =
1088                 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1089         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1090                                             sscreen->b.family <= CHIP_POLARIS12) ||
1091                                            sscreen->b.family == CHIP_VEGA10 ||
1092                                            sscreen->b.family == CHIP_RAVEN;
1093         sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
1094                                         sscreen->b.family == CHIP_RAVEN;
1095
1096         if (sscreen->b.debug_flags & DBG(DPBB)) {
1097                 sscreen->dpbb_allowed = true;
1098         } else {
1099                 /* Only enable primitive binning on Raven by default. */
1100                 sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
1101                                         !(sscreen->b.debug_flags & DBG(NO_DPBB));
1102         }
1103
1104         if (sscreen->b.debug_flags & DBG(DFSM)) {
1105                 sscreen->dfsm_allowed = sscreen->dpbb_allowed;
1106         } else {
1107                 sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1108                                         !(sscreen->b.debug_flags & DBG(NO_DFSM));
1109         }
1110
1111         /* While it would be nice not to have this flag, we are constrained
1112          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1113          * on GFX9.
1114          */
1115         sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1116
1117         sscreen->b.has_cp_dma = true;
1118         sscreen->b.has_streamout = true;
1119
1120         /* Some chips have RB+ registers, but don't support RB+. Those must
1121          * always disable it.
1122          */
1123         if (sscreen->b.family == CHIP_STONEY ||
1124             sscreen->b.chip_class >= GFX9) {
1125                 sscreen->b.has_rbplus = true;
1126
1127                 sscreen->b.rbplus_allowed =
1128                         !(sscreen->b.debug_flags & DBG(NO_RB_PLUS)) &&
1129                         (sscreen->b.family == CHIP_STONEY ||
1130                          sscreen->b.family == CHIP_RAVEN);
1131         }
1132
1133         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1134         sscreen->use_monolithic_shaders =
1135                 (sscreen->b.debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1136
1137         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1138                                             SI_CONTEXT_INV_VMEM_L1;
1139         if (sscreen->b.chip_class <= VI) {
1140                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1141                 sscreen->b.barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1142         }
1143
1144         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1145
1146         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1147                 sscreen->b.debug_flags |= DBG_ALL_SHADERS;
1148
1149         for (i = 0; i < num_compiler_threads; i++)
1150                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1151         for (i = 0; i < num_compiler_threads_lowprio; i++)
1152                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1153
1154         /* Create the auxiliary context. This must be done last. */
1155         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1156
1157         if (sscreen->b.debug_flags & DBG(TEST_DMA))
1158                 si_test_dma(&sscreen->b);
1159
1160         if (sscreen->b.debug_flags & (DBG(TEST_VMFAULT_CP) |
1161                                       DBG(TEST_VMFAULT_SDMA) |
1162                                       DBG(TEST_VMFAULT_SHADER)))
1163                 si_test_vmfault(sscreen);
1164
1165         return &sscreen->b.b;
1166 }