src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_log.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_suballoc.h"
  34 #include "util/u_tests.h"
  35 #include "util/xmlconfig.h"
  36 #include "vl/vl_decoder.h"
  37 #include "../ddebug/dd_util.h"
  38
  39 #include "compiler/nir/nir.h"
  40
  41 /*
  42  * pipe_context
  43  */
  44 static void si_destroy_context(struct pipe_context *context)
  45 {
  46         struct si_context *sctx = (struct si_context *)context;
  47         int i;
  48
  49         /* Unreference the framebuffer normally to disable related logic
  50          * properly.
  51          */
  52         struct pipe_framebuffer_state fb = {};
  53         if (context->set_framebuffer_state)
  54                 context->set_framebuffer_state(context, &fb);
  55
  56         si_release_all_descriptors(sctx);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_fmask_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  83         if (sctx->custom_blend_eliminate_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87         if (sctx->vs_blit_pos)
  88                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos);
  89         if (sctx->vs_blit_pos_layered)
  90                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos_layered);
  91         if (sctx->vs_blit_color)
  92                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color);
  93         if (sctx->vs_blit_color_layered)
  94                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color_layered);
  95         if (sctx->vs_blit_texcoord)
  96                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_texcoord);
  97
  98         if (sctx->blitter)
  99                 util_blitter_destroy(sctx->blitter);
 100
 101         si_common_context_cleanup(&sctx->b);
 102
 103         LLVMDisposeTargetMachine(sctx->tm);
 104
 105         si_saved_cs_reference(&sctx->current_saved_cs, NULL);
 106
 107         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 108         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 109
 110         util_dynarray_fini(&sctx->resident_tex_handles);
 111         util_dynarray_fini(&sctx->resident_img_handles);
 112         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 113         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 114         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 115         FREE(sctx);
 116 }
 117
 118 static enum pipe_reset_status
 119 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 120 {
 121         struct si_context *sctx = (struct si_context *)ctx;
 122
 123         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 124 }
 125
 126 /* Apitrace profiling:
 127  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 128  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 129  *      and remember its number.
 130  *   3) In Mesa, enable queries and performance counters around that draw
 131  *      call and print the results.
 132  *   4) glretrace --benchmark --markers ..
 133  */
 134 static void si_emit_string_marker(struct pipe_context *ctx,
 135                                   const char *string, int len)
 136 {
 137         struct si_context *sctx = (struct si_context *)ctx;
 138
 139         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 140
 141         if (sctx->b.log)
 142                 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
 143 }
 144
 145 static LLVMTargetMachineRef
 146 si_create_llvm_target_machine(struct si_screen *sscreen)
 147 {
 148         enum ac_target_machine_options tm_options =
 149                 (sscreen->b.debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
 150                 (sscreen->b.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
 151                 (sscreen->b.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
 152                 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
 153
 154         return ac_create_target_machine(sscreen->b.family, tm_options);
 155 }
 156
 157 static void si_set_log_context(struct pipe_context *ctx,
 158                                struct u_log_context *log)
 159 {
 160         struct si_context *sctx = (struct si_context *)ctx;
 161         sctx->b.log = log;
 162
 163         if (log)
 164                 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
 165 }
 166
 167 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 168                                               unsigned flags)
 169 {
 170         struct si_context *sctx = CALLOC_STRUCT(si_context);
 171         struct si_screen* sscreen = (struct si_screen *)screen;
 172         struct radeon_winsys *ws = sscreen->b.ws;
 173         int shader, i;
 174
 175         if (!sctx)
 176                 return NULL;
 177
 178         if (flags & PIPE_CONTEXT_DEBUG)
 179                 sscreen->record_llvm_ir = true; /* racy but not critical */
 180
 181         sctx->b.b.screen = screen; /* this must be set first */
 182         sctx->b.b.priv = NULL;
 183         sctx->b.b.destroy = si_destroy_context;
 184         sctx->b.b.emit_string_marker = si_emit_string_marker;
 185         sctx->b.b.set_log_context = si_set_log_context;
 186         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 187         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 188         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 189
 190         if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
 191                 goto fail;
 192
 193         if (sscreen->b.info.drm_major == 3)
 194                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 195
 196         si_init_blit_functions(sctx);
 197         si_init_compute_functions(sctx);
 198         si_init_cp_dma_functions(sctx);
 199         si_init_debug_functions(sctx);
 200         si_init_msaa_functions(sctx);
 201         si_init_streamout_functions(sctx);
 202
 203         if (sscreen->b.info.has_hw_decode) {
 204                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 205                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 206         } else {
 207                 sctx->b.b.create_video_codec = vl_create_decoder;
 208                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 209         }
 210
 211         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 212                                        si_context_gfx_flush, sctx);
 213         sctx->b.gfx.flush = si_context_gfx_flush;
 214
 215         /* Border colors. */
 216         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 217                                           sizeof(*sctx->border_color_table));
 218         if (!sctx->border_color_table)
 219                 goto fail;
 220
 221         sctx->border_color_buffer = (struct r600_resource*)
 222                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 223                                    SI_MAX_BORDER_COLORS *
 224                                    sizeof(*sctx->border_color_table));
 225         if (!sctx->border_color_buffer)
 226                 goto fail;
 227
 228         sctx->border_color_map =
 229                 ws->buffer_map(sctx->border_color_buffer->buf,
 230                                NULL, PIPE_TRANSFER_WRITE);
 231         if (!sctx->border_color_map)
 232                 goto fail;
 233
 234         si_init_all_descriptors(sctx);
 235         si_init_state_functions(sctx);
 236         si_init_shader_functions(sctx);
 237         si_init_viewport_functions(sctx);
 238         si_init_ia_multi_vgt_param_table(sctx);
 239
 240         if (sctx->b.chip_class >= CIK)
 241                 cik_init_sdma_functions(sctx);
 242         else
 243                 si_init_dma_functions(sctx);
 244
 245         if (sscreen->b.debug_flags & DBG(FORCE_DMA))
 246                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 247
 248         sctx->blitter = util_blitter_create(&sctx->b.b);
 249         if (sctx->blitter == NULL)
 250                 goto fail;
 251         sctx->blitter->draw_rectangle = si_draw_rectangle;
 252         sctx->blitter->skip_viewport_restore = true;
 253
 254         sctx->sample_mask.sample_mask = 0xffff;
 255
 256         /* these must be last */
 257         si_begin_new_cs(sctx);
 258
 259         if (sctx->b.chip_class >= GFX9) {
 260                 sctx->wait_mem_scratch = (struct r600_resource*)
 261                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 262                 if (!sctx->wait_mem_scratch)
 263                         goto fail;
 264
 265                 /* Initialize the memory. */
 266                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 267                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 268                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 269                             S_370_WR_CONFIRM(1) |
 270                             S_370_ENGINE_SEL(V_370_ME));
 271                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 272                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 273                 radeon_emit(cs, sctx->wait_mem_number);
 274         }
 275
 276         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 277          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 278         if (sctx->b.chip_class == CIK) {
 279                 sctx->null_const_buf.buffer =
 280                         si_aligned_buffer_create(screen,
 281                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 282                                                    PIPE_USAGE_DEFAULT, 16,
 283                                                    sctx->screen->b.info.tcc_cache_line_size);
 284                 if (!sctx->null_const_buf.buffer)
 285                         goto fail;
 286                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 287
 288                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 289                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 290                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 291                                                               &sctx->null_const_buf);
 292                         }
 293                 }
 294
 295                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 296                                  &sctx->null_const_buf);
 297                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 298                                  &sctx->null_const_buf);
 299                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 300                                  &sctx->null_const_buf);
 301                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 302                                  &sctx->null_const_buf);
 303                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 304                                  &sctx->null_const_buf);
 305
 306                 /* Clear the NULL constant buffer, because loads should return zeros. */
 307                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 308                                      sctx->null_const_buf.buffer->width0, 0,
 309                                      R600_COHERENCY_SHADER);
 310         }
 311
 312         uint64_t max_threads_per_block;
 313         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 314                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 315                                   &max_threads_per_block);
 316
 317         /* The maximum number of scratch waves. Scratch space isn't divided
 318          * evenly between CUs. The number is only a function of the number of CUs.
 319          * We can decrease the constant to decrease the scratch buffer size.
 320          *
 321          * sctx->scratch_waves must be >= the maximum posible size of
 322          * 1 threadgroup, so that the hw doesn't hang from being unable
 323          * to start any.
 324          *
 325          * The recommended value is 4 per CU at most. Higher numbers don't
 326          * bring much benefit, but they still occupy chip resources (think
 327          * async compute). I've seen ~2% performance difference between 4 and 32.
 328          */
 329         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 330                                    max_threads_per_block / 64);
 331
 332         sctx->tm = si_create_llvm_target_machine(sscreen);
 333
 334         /* Bindless handles. */
 335         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 336                                                     _mesa_key_pointer_equal);
 337         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 338                                                     _mesa_key_pointer_equal);
 339
 340         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 341         util_dynarray_init(&sctx->resident_img_handles, NULL);
 342         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 343         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 344         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 345
 346         return &sctx->b.b;
 347 fail:
 348         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 349         si_destroy_context(&sctx->b.b);
 350         return NULL;
 351 }
 352
 353 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 354                                                    void *priv, unsigned flags)
 355 {
 356         struct si_screen *sscreen = (struct si_screen *)screen;
 357         struct pipe_context *ctx;
 358
 359         if (sscreen->b.debug_flags & DBG(CHECK_VM))
 360                 flags |= PIPE_CONTEXT_DEBUG;
 361
 362         ctx = si_create_context(screen, flags);
 363
 364         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 365                 return ctx;
 366
 367         /* Clover (compute-only) is unsupported.
 368          *
 369          * Since the threaded context creates shader states from the non-driver
 370          * thread, asynchronous compilation is required for create_{shader}_-
 371          * state not to use pipe_context. Debug contexts (ddebug) disable
 372          * asynchronous compilation, so don't use the threaded context with
 373          * those.
 374          */
 375         if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
 376                 return ctx;
 377
 378         /* When shaders are logged to stderr, asynchronous compilation is
 379          * disabled too. */
 380         if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
 381                 return ctx;
 382
 383         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 384                                        si_replace_buffer_storage,
 385                                        &((struct si_context*)ctx)->b.tc);
 386 }
 387
 388 /*
 389  * pipe_screen
 390  */
 391 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 392 {
 393         /* Old kernels disallowed some register writes for SI
 394          * that are used for indirect dispatches. */
 395         return (sscreen->b.chip_class >= CIK ||
 396                 sscreen->b.info.drm_major == 3 ||
 397                 (sscreen->b.info.drm_major == 2 &&
 398                  sscreen->b.info.drm_minor >= 45));
 399 }
 400
 401 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 402 {
 403         struct si_screen *sscreen = (struct si_screen *)pscreen;
 404
 405         switch (param) {
 406         /* Supported features (boolean caps). */
 407         case PIPE_CAP_ACCELERATED:
 408         case PIPE_CAP_TWO_SIDED_STENCIL:
 409         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 410         case PIPE_CAP_ANISOTROPIC_FILTER:
 411         case PIPE_CAP_POINT_SPRITE:
 412         case PIPE_CAP_OCCLUSION_QUERY:
 413         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 414         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 415         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 416         case PIPE_CAP_TEXTURE_SWIZZLE:
 417         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 418         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 419         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 420         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 421         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 422         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 423         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 424         case PIPE_CAP_SM3:
 425         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 426         case PIPE_CAP_PRIMITIVE_RESTART:
 427         case PIPE_CAP_CONDITIONAL_RENDER:
 428         case PIPE_CAP_TEXTURE_BARRIER:
 429         case PIPE_CAP_INDEP_BLEND_ENABLE:
 430         case PIPE_CAP_INDEP_BLEND_FUNC:
 431         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 432         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 433         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 434         case PIPE_CAP_START_INSTANCE:
 435         case PIPE_CAP_NPOT_TEXTURES:
 436         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 437         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 438         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 439         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 440         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 441         case PIPE_CAP_TGSI_INSTANCEID:
 442         case PIPE_CAP_COMPUTE:
 443         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 444         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 445         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 446         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 447         case PIPE_CAP_CUBE_MAP_ARRAY:
 448         case PIPE_CAP_SAMPLE_SHADING:
 449         case PIPE_CAP_DRAW_INDIRECT:
 450         case PIPE_CAP_CLIP_HALFZ:
 451         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 452         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 453         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 454         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 455         case PIPE_CAP_TGSI_TEXCOORD:
 456         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 457         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 458         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 459         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 460         case PIPE_CAP_SHAREABLE_SHADERS:
 461         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 462         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 463         case PIPE_CAP_TEXTURE_QUERY_LOD:
 464         case PIPE_CAP_TEXTURE_GATHER_SM5:
 465         case PIPE_CAP_TGSI_TXQS:
 466         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 467         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 468         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 469         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 470         case PIPE_CAP_INVALIDATE_BUFFER:
 471         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 472         case PIPE_CAP_QUERY_MEMORY_INFO:
 473         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 474         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 475         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 476         case PIPE_CAP_GENERATE_MIPMAP:
 477         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 478         case PIPE_CAP_STRING_MARKER:
 479         case PIPE_CAP_CLEAR_TEXTURE:
 480         case PIPE_CAP_CULL_DISTANCE:
 481         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 482         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 483         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 484         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 485         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 486         case PIPE_CAP_DOUBLES:
 487         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 488         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 489         case PIPE_CAP_BINDLESS_TEXTURE:
 490         case PIPE_CAP_QUERY_TIMESTAMP:
 491         case PIPE_CAP_QUERY_TIME_ELAPSED:
 492         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 493         case PIPE_CAP_QUERY_SO_OVERFLOW:
 494         case PIPE_CAP_MEMOBJ:
 495         case PIPE_CAP_LOAD_CONSTBUF:
 496         case PIPE_CAP_INT64:
 497         case PIPE_CAP_INT64_DIVMOD:
 498         case PIPE_CAP_TGSI_CLOCK:
 499         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 500         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 501         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 502         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 503                 return 1;
 504
 505         case PIPE_CAP_TGSI_VOTE:
 506                 return HAVE_LLVM >= 0x0400;
 507
 508         case PIPE_CAP_TGSI_BALLOT:
 509                 return HAVE_LLVM >= 0x0500;
 510
 511         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 512                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 513
 514         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 515                 return (sscreen->b.info.drm_major == 2 &&
 516                         sscreen->b.info.drm_minor >= 43) ||
 517                        sscreen->b.info.drm_major == 3;
 518
 519         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 520                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 521                 return sscreen->b.chip_class < CIK ||
 522                        (sscreen->b.info.drm_major == 2 &&
 523                         sscreen->b.info.drm_minor >= 35) ||
 524                        sscreen->b.info.drm_major == 3;
 525
 526         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 527                 return R600_MAP_BUFFER_ALIGNMENT;
 528
 529         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 530         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 531         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 532         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 533         case PIPE_CAP_MAX_VERTEX_STREAMS:
 534         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 535                 return 4;
 536
 537         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 538                 if (sscreen->b.debug_flags & DBG(NIR))
 539                         return 140; /* no geometry and tessellation shaders yet */
 540                 if (si_have_tgsi_compute(sscreen))
 541                         return 450;
 542                 return 420;
 543
 544         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 545                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 546
 547         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 548         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 549         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 550                 /* SI doesn't support unaligned loads.
 551                  * CIK needs DRM 2.50.0 on radeon. */
 552                 return sscreen->b.chip_class == SI ||
 553                        (sscreen->b.info.drm_major == 2 &&
 554                         sscreen->b.info.drm_minor < 50);
 555
 556         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 557                 /* TODO: GFX9 hangs. */
 558                 if (sscreen->b.chip_class >= GFX9)
 559                         return 0;
 560                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 561                  * faults are mitigated in software.
 562                  */
 563                 if (sscreen->b.chip_class >= CIK &&
 564                     sscreen->b.info.drm_major == 3 &&
 565                     sscreen->b.info.drm_minor >= 13)
 566                         return RADEON_SPARSE_PAGE_SIZE;
 567                 return 0;
 568
 569         /* Unsupported features. */
 570         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 571         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 572         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 573         case PIPE_CAP_USER_VERTEX_BUFFERS:
 574         case PIPE_CAP_FAKE_SW_MSAA:
 575         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 576         case PIPE_CAP_VERTEXID_NOBASE:
 577         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 578         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 579         case PIPE_CAP_TGSI_FS_FBFETCH:
 580         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 581         case PIPE_CAP_UMA:
 582         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 583         case PIPE_CAP_POST_DEPTH_COVERAGE:
 584         case PIPE_CAP_TILE_RASTER_ORDER:
 585         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 586                 return 0;
 587
 588         case PIPE_CAP_NATIVE_FENCE_FD:
 589                 return sscreen->b.info.has_sync_file;
 590
 591         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 592                 return si_have_tgsi_compute(sscreen);
 593
 594         case PIPE_CAP_DRAW_PARAMETERS:
 595         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 596         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 597                 return sscreen->has_draw_indirect_multi;
 598
 599         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 600                 return 30;
 601
 602         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 603                 return sscreen->b.chip_class <= VI ?
 604                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 605
 606         /* Stream output. */
 607         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 608         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 609                 return 32*4;
 610
 611         /* Geometry shader output. */
 612         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 613                 return 1024;
 614         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 615                 return 4095;
 616
 617         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 618                 return 2048;
 619
 620         /* Texturing. */
 621         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 622         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 623                 return 15; /* 16384 */
 624         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 625                 /* textures support 8192, but layered rendering supports 2048 */
 626                 return 12;
 627         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 628                 /* textures support 8192, but layered rendering supports 2048 */
 629                 return 2048;
 630
 631         /* Viewports and render targets. */
 632         case PIPE_CAP_MAX_VIEWPORTS:
 633                 return SI_MAX_VIEWPORTS;
 634         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 635         case PIPE_CAP_MAX_RENDER_TARGETS:
 636                 return 8;
 637
 638         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 639         case PIPE_CAP_MIN_TEXEL_OFFSET:
 640                 return -32;
 641
 642         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 643         case PIPE_CAP_MAX_TEXEL_OFFSET:
 644                 return 31;
 645
 646         case PIPE_CAP_ENDIANNESS:
 647                 return PIPE_ENDIAN_LITTLE;
 648
 649         case PIPE_CAP_VENDOR_ID:
 650                 return ATI_VENDOR_ID;
 651         case PIPE_CAP_DEVICE_ID:
 652                 return sscreen->b.info.pci_id;
 653         case PIPE_CAP_VIDEO_MEMORY:
 654                 return sscreen->b.info.vram_size >> 20;
 655         case PIPE_CAP_PCI_GROUP:
 656                 return sscreen->b.info.pci_domain;
 657         case PIPE_CAP_PCI_BUS:
 658                 return sscreen->b.info.pci_bus;
 659         case PIPE_CAP_PCI_DEVICE:
 660                 return sscreen->b.info.pci_dev;
 661         case PIPE_CAP_PCI_FUNCTION:
 662                 return sscreen->b.info.pci_func;
 663         }
 664         return 0;
 665 }
 666
 667 static int si_get_shader_param(struct pipe_screen* pscreen,
 668                                enum pipe_shader_type shader,
 669                                enum pipe_shader_cap param)
 670 {
 671         struct si_screen *sscreen = (struct si_screen *)pscreen;
 672
 673         switch(shader)
 674         {
 675         case PIPE_SHADER_FRAGMENT:
 676         case PIPE_SHADER_VERTEX:
 677         case PIPE_SHADER_GEOMETRY:
 678         case PIPE_SHADER_TESS_CTRL:
 679         case PIPE_SHADER_TESS_EVAL:
 680                 break;
 681         case PIPE_SHADER_COMPUTE:
 682                 switch (param) {
 683                 case PIPE_SHADER_CAP_PREFERRED_IR:
 684                         return PIPE_SHADER_IR_NATIVE;
 685
 686                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 687                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 688
 689                         if (si_have_tgsi_compute(sscreen))
 690                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 691
 692                         return ir;
 693                 }
 694
 695                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 696                         uint64_t max_const_buffer_size;
 697                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 698                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 699                                 &max_const_buffer_size);
 700                         return MIN2(max_const_buffer_size, INT_MAX);
 701                 }
 702                 default:
 703                         /* If compute shaders don't require a special value
 704                          * for this cap, we can return the same value we
 705                          * do for other shader types. */
 706                         break;
 707                 }
 708                 break;
 709         default:
 710                 return 0;
 711         }
 712
 713         switch (param) {
 714         /* Shader limits. */
 715         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 716         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 717         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 718         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 719         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 720                 return 16384;
 721         case PIPE_SHADER_CAP_MAX_INPUTS:
 722                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 723         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 724                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 725         case PIPE_SHADER_CAP_MAX_TEMPS:
 726                 return 256; /* Max native temporaries. */
 727         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 728                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 729         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 730                 return SI_NUM_CONST_BUFFERS;
 731         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 732         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 733                 return SI_NUM_SAMPLERS;
 734         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 735                 return SI_NUM_SHADER_BUFFERS;
 736         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 737                 return SI_NUM_IMAGES;
 738         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 739                 return 32;
 740         case PIPE_SHADER_CAP_PREFERRED_IR:
 741                 if (sscreen->b.debug_flags & DBG(NIR) &&
 742                     (shader == PIPE_SHADER_VERTEX ||
 743                      shader == PIPE_SHADER_FRAGMENT))
 744                         return PIPE_SHADER_IR_NIR;
 745                 return PIPE_SHADER_IR_TGSI;
 746         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 747                 return 4;
 748
 749         /* Supported boolean features. */
 750         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 751         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 752         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 753         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 754         case PIPE_SHADER_CAP_INTEGERS:
 755         case PIPE_SHADER_CAP_INT64_ATOMICS:
 756         case PIPE_SHADER_CAP_FP16:
 757         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 758         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 759         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 760         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 761         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 762         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 763                 return 1;
 764
 765         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 766                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 767                 return shader != PIPE_SHADER_GEOMETRY &&
 768                        (sscreen->llvm_has_working_vgpr_indexing ||
 769                         /* TCS and TES load inputs directly from LDS or
 770                          * offchip memory, so indirect indexing is trivial. */
 771                         shader == PIPE_SHADER_TESS_CTRL ||
 772                         shader == PIPE_SHADER_TESS_EVAL);
 773
 774         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 775                 return sscreen->llvm_has_working_vgpr_indexing ||
 776                        /* TCS stores outputs directly to memory. */
 777                        shader == PIPE_SHADER_TESS_CTRL;
 778
 779         /* Unsupported boolean features. */
 780         case PIPE_SHADER_CAP_SUBROUTINES:
 781         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 782                 return 0;
 783         }
 784         return 0;
 785 }
 786
 787 static const struct nir_shader_compiler_options nir_options = {
 788         .vertex_id_zero_based = true,
 789         .lower_scmp = true,
 790         .lower_flrp32 = true,
 791         .lower_fsat = true,
 792         .lower_fdiv = true,
 793         .lower_sub = true,
 794         .lower_ffma = true,
 795         .lower_pack_snorm_2x16 = true,
 796         .lower_pack_snorm_4x8 = true,
 797         .lower_pack_unorm_2x16 = true,
 798         .lower_pack_unorm_4x8 = true,
 799         .lower_unpack_snorm_2x16 = true,
 800         .lower_unpack_snorm_4x8 = true,
 801         .lower_unpack_unorm_2x16 = true,
 802         .lower_unpack_unorm_4x8 = true,
 803         .lower_extract_byte = true,
 804         .lower_extract_word = true,
 805         .max_unroll_iterations = 32,
 806         .native_integers = true,
 807 };
 808
 809 static const void *
 810 si_get_compiler_options(struct pipe_screen *screen,
 811                         enum pipe_shader_ir ir,
 812                         enum pipe_shader_type shader)
 813 {
 814         assert(ir == PIPE_SHADER_IR_NIR);
 815         return &nir_options;
 816 }
 817
 818 static void si_destroy_screen(struct pipe_screen* pscreen)
 819 {
 820         struct si_screen *sscreen = (struct si_screen *)pscreen;
 821         struct si_shader_part *parts[] = {
 822                 sscreen->vs_prologs,
 823                 sscreen->tcs_epilogs,
 824                 sscreen->gs_prologs,
 825                 sscreen->ps_prologs,
 826                 sscreen->ps_epilogs
 827         };
 828         unsigned i;
 829
 830         if (!sscreen->b.ws->unref(sscreen->b.ws))
 831                 return;
 832
 833         util_queue_destroy(&sscreen->shader_compiler_queue);
 834         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 835
 836         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 837                 if (sscreen->tm[i])
 838                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 839
 840         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 841                 if (sscreen->tm_low_priority[i])
 842                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 843
 844         /* Free shader parts. */
 845         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 846                 while (parts[i]) {
 847                         struct si_shader_part *part = parts[i];
 848
 849                         parts[i] = part->next;
 850                         si_radeon_shader_binary_clean(&part->binary);
 851                         FREE(part);
 852                 }
 853         }
 854         mtx_destroy(&sscreen->shader_parts_mutex);
 855         si_destroy_shader_cache(sscreen);
 856         si_destroy_common_screen(&sscreen->b);
 857 }
 858
 859 static bool si_init_gs_info(struct si_screen *sscreen)
 860 {
 861         /* gs_table_depth is not used by GFX9 */
 862         if (sscreen->b.chip_class >= GFX9)
 863                 return true;
 864
 865         switch (sscreen->b.family) {
 866         case CHIP_OLAND:
 867         case CHIP_HAINAN:
 868         case CHIP_KAVERI:
 869         case CHIP_KABINI:
 870         case CHIP_MULLINS:
 871         case CHIP_ICELAND:
 872         case CHIP_CARRIZO:
 873         case CHIP_STONEY:
 874                 sscreen->gs_table_depth = 16;
 875                 return true;
 876         case CHIP_TAHITI:
 877         case CHIP_PITCAIRN:
 878         case CHIP_VERDE:
 879         case CHIP_BONAIRE:
 880         case CHIP_HAWAII:
 881         case CHIP_TONGA:
 882         case CHIP_FIJI:
 883         case CHIP_POLARIS10:
 884         case CHIP_POLARIS11:
 885         case CHIP_POLARIS12:
 886                 sscreen->gs_table_depth = 32;
 887                 return true;
 888         default:
 889                 return false;
 890         }
 891 }
 892
 893 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 894 {
 895         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 896         unsigned i;
 897
 898         if (!family)
 899                 return;
 900
 901         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 902                 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
 903                         /* Override family and chip_class. */
 904                         sscreen->b.family = sscreen->b.info.family = i;
 905
 906                         if (i >= CHIP_VEGA10)
 907                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 908                         else if (i >= CHIP_TONGA)
 909                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 910                         else if (i >= CHIP_BONAIRE)
 911                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 912                         else
 913                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 914
 915                         /* Don't submit any IBs. */
 916                         setenv("RADEON_NOOP", "1", 1);
 917                         return;
 918                 }
 919         }
 920
 921         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 922         exit(1);
 923 }
 924
 925 static void si_test_vmfault(struct si_screen *sscreen)
 926 {
 927         struct pipe_context *ctx = sscreen->b.aux_context;
 928         struct si_context *sctx = (struct si_context *)ctx;
 929         struct pipe_resource *buf =
 930                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 931
 932         if (!buf) {
 933                 puts("Buffer allocation failed.");
 934                 exit(1);
 935         }
 936
 937         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 938
 939         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_CP)) {
 940                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 941                 ctx->flush(ctx, NULL, 0);
 942                 puts("VM fault test: CP - done.");
 943         }
 944         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SDMA)) {
 945                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 946                 ctx->flush(ctx, NULL, 0);
 947                 puts("VM fault test: SDMA - done.");
 948         }
 949         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SHADER)) {
 950                 util_test_constant_buffer(ctx, buf);
 951                 puts("VM fault test: Shader - done.");
 952         }
 953         exit(0);
 954 }
 955
 956 static void radeonsi_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 957 {
 958         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 959 }
 960
 961 static void radeonsi_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 962 {
 963         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 964
 965         ac_compute_device_uuid(&rscreen->info, uuid, PIPE_UUID_SIZE);
 966 }
 967
 968 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 969                                            const struct pipe_screen_config *config)
 970 {
 971         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 972         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 973
 974         if (!sscreen) {
 975                 return NULL;
 976         }
 977
 978         /* Set functions first. */
 979         sscreen->b.b.context_create = si_pipe_create_context;
 980         sscreen->b.b.destroy = si_destroy_screen;
 981         sscreen->b.b.get_param = si_get_param;
 982         sscreen->b.b.get_shader_param = si_get_shader_param;
 983         sscreen->b.b.get_compiler_options = si_get_compiler_options;
 984         sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
 985         sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
 986         sscreen->b.b.resource_create = si_resource_create_common;
 987
 988         si_init_screen_state_functions(sscreen);
 989
 990         /* Set these flags in debug_flags early, so that the shader cache takes
 991          * them into account.
 992          */
 993         if (driQueryOptionb(config->options,
 994                             "glsl_correct_derivatives_after_discard"))
 995                 sscreen->b.debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
 996         if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
 997                 sscreen->b.debug_flags |= DBG(SI_SCHED);
 998
 999         if (!si_common_screen_init(&sscreen->b, ws) ||
1000             !si_init_gs_info(sscreen) ||
1001             !si_init_shader_cache(sscreen)) {
1002                 FREE(sscreen);
1003                 return NULL;
1004         }
1005
1006         /* Only enable as many threads as we have target machines, but at most
1007          * the number of CPUs - 1 if there is more than one.
1008          */
1009         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
1010         num_threads = MAX2(1, num_threads - 1);
1011         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1012         num_compiler_threads_lowprio =
1013                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1014
1015         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1016                              32, num_compiler_threads,
1017                              UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1018                 si_destroy_shader_cache(sscreen);
1019                 FREE(sscreen);
1020                 return NULL;
1021         }
1022
1023         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1024                              "si_shader_low",
1025                              32, num_compiler_threads_lowprio,
1026                              UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1027                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1028                si_destroy_shader_cache(sscreen);
1029                FREE(sscreen);
1030                return NULL;
1031         }
1032
1033         si_handle_env_var_force_family(sscreen);
1034
1035         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1036                 si_init_perfcounters(sscreen);
1037
1038         /* Hawaii has a bug with offchip buffers > 256 that can be worked
1039          * around by setting 4K granularity.
1040          */
1041         sscreen->tess_offchip_block_dw_size =
1042                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1043
1044         /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1045          * on SI. */
1046         sscreen->has_clear_state = sscreen->b.chip_class >= CIK;
1047
1048         sscreen->has_distributed_tess =
1049                 sscreen->b.chip_class >= VI &&
1050                 sscreen->b.info.max_se >= 2;
1051
1052         sscreen->has_draw_indirect_multi =
1053                 (sscreen->b.family >= CHIP_POLARIS10) ||
1054                 (sscreen->b.chip_class == VI &&
1055                  sscreen->b.info.pfp_fw_version >= 121 &&
1056                  sscreen->b.info.me_fw_version >= 87) ||
1057                 (sscreen->b.chip_class == CIK &&
1058                  sscreen->b.info.pfp_fw_version >= 211 &&
1059                  sscreen->b.info.me_fw_version >= 173) ||
1060                 (sscreen->b.chip_class == SI &&
1061                  sscreen->b.info.pfp_fw_version >= 79 &&
1062                  sscreen->b.info.me_fw_version >= 142);
1063
1064         sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
1065                                          sscreen->b.info.max_se >= 2 &&
1066                                          !(sscreen->b.debug_flags & DBG(NO_OUT_OF_ORDER));
1067         sscreen->assume_no_z_fights =
1068                 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1069         sscreen->commutative_blend_add =
1070                 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1071         sscreen->clear_db_cache_before_clear =
1072                 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1073         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1074                                             sscreen->b.family <= CHIP_POLARIS12) ||
1075                                            sscreen->b.family == CHIP_VEGA10 ||
1076                                            sscreen->b.family == CHIP_RAVEN;
1077         sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
1078                                         sscreen->b.family == CHIP_RAVEN;
1079
1080         if (sscreen->b.debug_flags & DBG(DPBB)) {
1081                 sscreen->dpbb_allowed = true;
1082         } else {
1083                 /* Only enable primitive binning on Raven by default. */
1084                 sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
1085                                         !(sscreen->b.debug_flags & DBG(NO_DPBB));
1086         }
1087
1088         if (sscreen->b.debug_flags & DBG(DFSM)) {
1089                 sscreen->dfsm_allowed = sscreen->dpbb_allowed;
1090         } else {
1091                 sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1092                                         !(sscreen->b.debug_flags & DBG(NO_DFSM));
1093         }
1094
1095         /* While it would be nice not to have this flag, we are constrained
1096          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1097          * on GFX9.
1098          */
1099         sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1100
1101         sscreen->b.has_cp_dma = true;
1102         sscreen->b.has_streamout = true;
1103
1104         /* Some chips have RB+ registers, but don't support RB+. Those must
1105          * always disable it.
1106          */
1107         if (sscreen->b.family == CHIP_STONEY ||
1108             sscreen->b.chip_class >= GFX9) {
1109                 sscreen->b.has_rbplus = true;
1110
1111                 sscreen->b.rbplus_allowed =
1112                         !(sscreen->b.debug_flags & DBG(NO_RB_PLUS)) &&
1113                         (sscreen->b.family == CHIP_STONEY ||
1114                          sscreen->b.family == CHIP_RAVEN);
1115         }
1116
1117         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1118         sscreen->use_monolithic_shaders =
1119                 (sscreen->b.debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1120
1121         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1122                                             SI_CONTEXT_INV_VMEM_L1;
1123         if (sscreen->b.chip_class <= VI) {
1124                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1125                 sscreen->b.barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1126         }
1127
1128         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1129
1130         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1131                 sscreen->b.debug_flags |= DBG_ALL_SHADERS;
1132
1133         for (i = 0; i < num_compiler_threads; i++)
1134                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1135         for (i = 0; i < num_compiler_threads_lowprio; i++)
1136                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1137
1138         /* Create the auxiliary context. This must be done last. */
1139         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1140
1141         if (sscreen->b.debug_flags & DBG(TEST_DMA))
1142                 si_test_dma(&sscreen->b);
1143
1144         if (sscreen->b.debug_flags & (DBG(TEST_VMFAULT_CP) |
1145                                       DBG(TEST_VMFAULT_SDMA) |
1146                                       DBG(TEST_VMFAULT_SHADER)))
1147                 si_test_vmfault(sscreen);
1148
1149         return &sscreen->b.b;
1150 }