src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_table, NULL);
  48         r600_resource_reference(&sctx->scratch_buffer, NULL);
  49         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  50
  51         si_pm4_free_state(sctx, sctx->init_config, ~0);
  52         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  53         si_pm4_delete_state(sctx, tf_ring, sctx->tf_state);
  54         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  55                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  56
  57         if (sctx->pstipple_sampler_state)
  58                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  59         if (sctx->dummy_pixel_shader)
  60                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  61         if (sctx->fixed_func_tcs_shader)
  62                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader);
  63         if (sctx->custom_dsa_flush)
  64                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  65         if (sctx->custom_blend_resolve)
  66                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  67         if (sctx->custom_blend_decompress)
  68                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  69         if (sctx->custom_blend_fastclear)
  70                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  71         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  72
  73         if (sctx->blitter)
  74                 util_blitter_destroy(sctx->blitter);
  75
  76         si_pm4_cleanup(sctx);
  77
  78         r600_common_context_cleanup(&sctx->b);
  79
  80 #if HAVE_LLVM >= 0x0306
  81         LLVMDisposeTargetMachine(sctx->tm);
  82 #endif
  83
  84         FREE(sctx);
  85 }
  86
  87 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  88 {
  89         struct si_context *sctx = CALLOC_STRUCT(si_context);
  90         struct si_screen* sscreen = (struct si_screen *)screen;
  91         struct radeon_winsys *ws = sscreen->b.ws;
  92         LLVMTargetRef r600_target;
  93 #if HAVE_LLVM >= 0x0306
  94         const char *triple = "amdgcn--";
  95 #endif
  96         int shader, i;
  97
  98         if (sctx == NULL)
  99                 return NULL;
 100
 101         sctx->b.b.screen = screen; /* this must be set first */
 102         sctx->b.b.priv = priv;
 103         sctx->b.b.destroy = si_destroy_context;
 104         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 105         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 106
 107         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 108                 goto fail;
 109
 110         si_init_blit_functions(sctx);
 111         si_init_compute_functions(sctx);
 112         si_init_cp_dma_functions(sctx);
 113
 114         if (sscreen->b.info.has_uvd) {
 115                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 116                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 117         } else {
 118                 sctx->b.b.create_video_codec = vl_create_decoder;
 119                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 120         }
 121
 122         sctx->b.rings.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 123                                              sctx, sscreen->b.trace_bo ?
 124                                                 sscreen->b.trace_bo->cs_buf : NULL);
 125         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 126
 127         si_init_all_descriptors(sctx);
 128
 129         /* Initialize cache_flush. */
 130         sctx->cache_flush = si_atom_cache_flush;
 131         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 132
 133         sctx->msaa_sample_locs = si_atom_msaa_sample_locs;
 134         sctx->atoms.s.msaa_sample_locs = &sctx->msaa_sample_locs;
 135
 136         sctx->msaa_config = si_atom_msaa_config;
 137         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 138
 139         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 140         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 141
 142         si_init_state_functions(sctx);
 143         si_init_shader_functions(sctx);
 144
 145         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 146                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 147
 148         sctx->blitter = util_blitter_create(&sctx->b.b);
 149         if (sctx->blitter == NULL)
 150                 goto fail;
 151         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 152
 153         /* these must be last */
 154         si_begin_new_cs(sctx);
 155         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 156
 157         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 158          * with a NULL buffer). We need to use a dummy buffer instead. */
 159         if (sctx->b.chip_class == CIK) {
 160                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 161                                                                  PIPE_USAGE_DEFAULT, 16);
 162                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 163
 164                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 165                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 166                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 167                                                               &sctx->null_const_buf);
 168                         }
 169                 }
 170
 171                 /* Clear the NULL constant buffer, because loads should return zeros. */
 172                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 173                                      sctx->null_const_buf.buffer->width0, 0, false);
 174         }
 175
 176         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 177          * this for non-cs shaders.  Using the wrong value here can result in
 178          * GPU lockups, but the maximum value seems to always work.
 179          */
 180         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 181
 182 #if HAVE_LLVM >= 0x0306
 183         /* Initialize LLVM TargetMachine */
 184         r600_target = radeon_llvm_get_r600_target(triple);
 185         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 186                                            r600_get_llvm_processor_name(sscreen->b.family),
 187                                            "+DumpCode,+vgpr-spilling",
 188                                            LLVMCodeGenLevelDefault,
 189                                            LLVMRelocDefault,
 190                                            LLVMCodeModelDefault);
 191 #endif
 192
 193         return &sctx->b.b;
 194 fail:
 195         si_destroy_context(&sctx->b.b);
 196         return NULL;
 197 }
 198
 199 /*
 200  * pipe_screen
 201  */
 202
 203 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 204 {
 205         struct si_screen *sscreen = (struct si_screen *)pscreen;
 206
 207         switch (param) {
 208         /* Supported features (boolean caps). */
 209         case PIPE_CAP_TWO_SIDED_STENCIL:
 210         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 211         case PIPE_CAP_ANISOTROPIC_FILTER:
 212         case PIPE_CAP_POINT_SPRITE:
 213         case PIPE_CAP_OCCLUSION_QUERY:
 214         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 215         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 216         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 217         case PIPE_CAP_TEXTURE_SWIZZLE:
 218         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 219         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 220         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 221         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 222         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 223         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 224         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 225         case PIPE_CAP_SM3:
 226         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 227         case PIPE_CAP_PRIMITIVE_RESTART:
 228         case PIPE_CAP_CONDITIONAL_RENDER:
 229         case PIPE_CAP_TEXTURE_BARRIER:
 230         case PIPE_CAP_INDEP_BLEND_ENABLE:
 231         case PIPE_CAP_INDEP_BLEND_FUNC:
 232         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 233         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 234         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 235         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 236         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 237         case PIPE_CAP_USER_INDEX_BUFFERS:
 238         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 239         case PIPE_CAP_START_INSTANCE:
 240         case PIPE_CAP_NPOT_TEXTURES:
 241         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 242         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 243         case PIPE_CAP_TGSI_INSTANCEID:
 244         case PIPE_CAP_COMPUTE:
 245         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 246         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 247         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 248         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 249         case PIPE_CAP_CUBE_MAP_ARRAY:
 250         case PIPE_CAP_SAMPLE_SHADING:
 251         case PIPE_CAP_DRAW_INDIRECT:
 252         case PIPE_CAP_CLIP_HALFZ:
 253         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 254         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 255         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 256         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 257         case PIPE_CAP_TGSI_TEXCOORD:
 258         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 259         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 260         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 261         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 262                 return 1;
 263
 264         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 265                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 266
 267         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 268                 return sscreen->b.info.drm_major == 2 && sscreen->b.info.drm_minor >= 43;
 269
 270         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 271                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 272                 return sscreen->b.chip_class < CIK ||
 273                        sscreen->b.info.drm_minor >= 35;
 274
 275         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 276                 return R600_MAP_BUFFER_ALIGNMENT;
 277
 278         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 279         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 280                 return 4;
 281
 282         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 283                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 284
 285         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 286                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 287
 288         case PIPE_CAP_TEXTURE_QUERY_LOD:
 289         case PIPE_CAP_TEXTURE_GATHER_SM5:
 290                 return HAVE_LLVM >= 0x0305;
 291         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 292                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 293
 294         /* Unsupported features. */
 295         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 296         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 297         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 298         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 299         case PIPE_CAP_USER_VERTEX_BUFFERS:
 300         case PIPE_CAP_FAKE_SW_MSAA:
 301         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 302         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 303         case PIPE_CAP_VERTEXID_NOBASE:
 304         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 305                 return 0;
 306
 307         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 308                 return 30;
 309
 310         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 311                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 312
 313         /* Stream output. */
 314         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 315                 return sscreen->b.has_streamout ? 4 : 0;
 316         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 317                 return sscreen->b.has_streamout ? 1 : 0;
 318         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 319         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 320                 return sscreen->b.has_streamout ? 32*4 : 0;
 321
 322         /* Geometry shader output. */
 323         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 324                 return 1024;
 325         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 326                 return 4095;
 327         case PIPE_CAP_MAX_VERTEX_STREAMS:
 328                 return 4;
 329
 330         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 331                 return 2048;
 332
 333         /* Texturing. */
 334         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 335         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 336                 return 15; /* 16384 */
 337         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 338                 /* textures support 8192, but layered rendering supports 2048 */
 339                 return 12;
 340         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 341                 /* textures support 8192, but layered rendering supports 2048 */
 342                 return 2048;
 343
 344         /* Render targets. */
 345         case PIPE_CAP_MAX_RENDER_TARGETS:
 346                 return 8;
 347
 348         case PIPE_CAP_MAX_VIEWPORTS:
 349                 return 16;
 350
 351         /* Timer queries, present when the clock frequency is non zero. */
 352         case PIPE_CAP_QUERY_TIMESTAMP:
 353         case PIPE_CAP_QUERY_TIME_ELAPSED:
 354                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 355
 356         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 357         case PIPE_CAP_MIN_TEXEL_OFFSET:
 358                 return -32;
 359
 360         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 361         case PIPE_CAP_MAX_TEXEL_OFFSET:
 362                 return 31;
 363
 364         case PIPE_CAP_ENDIANNESS:
 365                 return PIPE_ENDIAN_LITTLE;
 366
 367         case PIPE_CAP_VENDOR_ID:
 368                 return 0x1002;
 369         case PIPE_CAP_DEVICE_ID:
 370                 return sscreen->b.info.pci_id;
 371         case PIPE_CAP_ACCELERATED:
 372                 return 1;
 373         case PIPE_CAP_VIDEO_MEMORY:
 374                 return sscreen->b.info.vram_size >> 20;
 375         case PIPE_CAP_UMA:
 376                 return 0;
 377         }
 378         return 0;
 379 }
 380
 381 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 382 {
 383         switch(shader)
 384         {
 385         case PIPE_SHADER_FRAGMENT:
 386         case PIPE_SHADER_VERTEX:
 387         case PIPE_SHADER_GEOMETRY:
 388                 break;
 389         case PIPE_SHADER_TESS_CTRL:
 390         case PIPE_SHADER_TESS_EVAL:
 391                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 392                 if (HAVE_LLVM < 0x0306 ||
 393                     (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
 394                         return 0;
 395                 break;
 396         case PIPE_SHADER_COMPUTE:
 397                 switch (param) {
 398                 case PIPE_SHADER_CAP_PREFERRED_IR:
 399 #if HAVE_LLVM < 0x0306
 400                         return PIPE_SHADER_IR_LLVM;
 401 #else
 402                         return PIPE_SHADER_IR_NATIVE;
 403 #endif
 404                 case PIPE_SHADER_CAP_DOUBLES:
 405                         return HAVE_LLVM >= 0x0307;
 406
 407                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 408                         uint64_t max_const_buffer_size;
 409                         pscreen->get_compute_param(pscreen,
 410                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 411                                 &max_const_buffer_size);
 412                         return max_const_buffer_size;
 413                 }
 414                 default:
 415                         /* If compute shaders don't require a special value
 416                          * for this cap, we can return the same value we
 417                          * do for other shader types. */
 418                         break;
 419                 }
 420                 break;
 421         default:
 422                 return 0;
 423         }
 424
 425         switch (param) {
 426         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 427         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 428         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 429         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 430                 return 16384;
 431         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 432                 return 32;
 433         case PIPE_SHADER_CAP_MAX_INPUTS:
 434                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 435         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 436                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 437         case PIPE_SHADER_CAP_MAX_TEMPS:
 438                 return 256; /* Max native temporaries. */
 439         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 440                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 441         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 442                 return SI_NUM_USER_CONST_BUFFERS;
 443         case PIPE_SHADER_CAP_MAX_PREDS:
 444                 return 0; /* FIXME */
 445         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 446                 return 1;
 447         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 448                 return 1;
 449         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 450                 /* Indirection of geometry shader input dimension is not
 451                  * handled yet
 452                  */
 453                 return shader != PIPE_SHADER_GEOMETRY;
 454         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 455         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 456         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 457                 return 1;
 458         case PIPE_SHADER_CAP_INTEGERS:
 459                 return 1;
 460         case PIPE_SHADER_CAP_SUBROUTINES:
 461                 return 0;
 462         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 463         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 464                 return 16;
 465         case PIPE_SHADER_CAP_PREFERRED_IR:
 466                 return PIPE_SHADER_IR_TGSI;
 467         case PIPE_SHADER_CAP_DOUBLES:
 468                 return HAVE_LLVM >= 0x0307;
 469         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 470         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 471                 return 0;
 472         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 473         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 474                 return 1;
 475         }
 476         return 0;
 477 }
 478
 479 static void si_destroy_screen(struct pipe_screen* pscreen)
 480 {
 481         struct si_screen *sscreen = (struct si_screen *)pscreen;
 482
 483         if (sscreen == NULL)
 484                 return;
 485
 486         if (!sscreen->b.ws->unref(sscreen->b.ws))
 487                 return;
 488
 489         r600_destroy_common_screen(&sscreen->b);
 490 }
 491
 492 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 493
 494 /* Initialize pipe config. This is especially important for GPUs
 495  * with 16 pipes and more where it's initialized incorrectly by
 496  * the TILING_CONFIG ioctl. */
 497 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 498 {
 499         unsigned mode2d;
 500
 501         /* This is okay, because there can be no 2D tiling without
 502          * the tile mode array, so we won't need the pipe config.
 503          * Return "success".
 504          */
 505         if (!sscreen->b.info.si_tile_mode_array_valid)
 506                 return true;
 507
 508         /* The same index is used for the 2D mode on CIK too. */
 509         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 510
 511         switch (G_009910_PIPE_CONFIG(mode2d)) {
 512         case V_02803C_ADDR_SURF_P2:
 513                 sscreen->b.tiling_info.num_channels = 2;
 514                 break;
 515         case V_02803C_X_ADDR_SURF_P4_8X16:
 516         case V_02803C_X_ADDR_SURF_P4_16X16:
 517         case V_02803C_X_ADDR_SURF_P4_16X32:
 518         case V_02803C_X_ADDR_SURF_P4_32X32:
 519                 sscreen->b.tiling_info.num_channels = 4;
 520                 break;
 521         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 522         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 523         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 524         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 525         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 526         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 527         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 528                 sscreen->b.tiling_info.num_channels = 8;
 529                 break;
 530         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 531         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 532                 sscreen->b.tiling_info.num_channels = 16;
 533                 break;
 534         default:
 535                 assert(0);
 536                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 537                         G_009910_PIPE_CONFIG(mode2d));
 538                 return false;
 539         }
 540         return true;
 541 }
 542
 543 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 544 {
 545         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 546
 547         if (sscreen == NULL) {
 548                 return NULL;
 549         }
 550
 551         /* Set functions first. */
 552         sscreen->b.b.context_create = si_create_context;
 553         sscreen->b.b.destroy = si_destroy_screen;
 554         sscreen->b.b.get_param = si_get_param;
 555         sscreen->b.b.get_shader_param = si_get_shader_param;
 556         sscreen->b.b.is_format_supported = si_is_format_supported;
 557         sscreen->b.b.resource_create = r600_resource_create_common;
 558
 559         if (!r600_common_screen_init(&sscreen->b, ws) ||
 560             !si_initialize_pipe_config(sscreen)) {
 561                 FREE(sscreen);
 562                 return NULL;
 563         }
 564
 565         sscreen->b.has_cp_dma = true;
 566         sscreen->b.has_streamout = true;
 567
 568         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 569                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 570
 571         /* Create the auxiliary context. This must be done last. */
 572         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 573
 574         return &sscreen->b.b;
 575 }