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radeonsi: initialize shader compilers in threads on demand
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
45 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
46 #include <xf86drm.h>
47
48 #include <llvm/Config/llvm-config.h>
49
50 static struct pipe_context *si_create_context(struct pipe_screen *screen,
51 unsigned flags);
52
53 static const struct debug_named_value debug_options[] = {
54 /* Shader logging options: */
55 { "vs", DBG(VS), "Print vertex shaders" },
56 { "ps", DBG(PS), "Print pixel shaders" },
57 { "gs", DBG(GS), "Print geometry shaders" },
58 { "tcs", DBG(TCS), "Print tessellation control shaders" },
59 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
60 { "cs", DBG(CS), "Print compute shaders" },
61 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
62 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
63 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
64 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
65
66 /* Shader compiler options the shader cache should be aware of: */
67 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
68 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
69 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
70 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
71 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
72 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
73 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
74 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
75
76 /* Shader compiler options (with no effect on the shader cache): */
77 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
78 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
79 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
80
81 /* Information logging options: */
82 { "info", DBG(INFO), "Print driver information" },
83 { "tex", DBG(TEX), "Print texture info" },
84 { "compute", DBG(COMPUTE), "Print compute info" },
85 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
86
87 /* Driver options: */
88 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
89 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
90 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
91 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
92 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
93 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
94
95 /* 3D engine options: */
96 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
97 { "nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline." },
98 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
99 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
100 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
101 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
102 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
103 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
104 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
105 { "dpbb", DBG(DPBB), "Enable DPBB." },
106 { "dfsm", DBG(DFSM), "Enable DFSM." },
107 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
108 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
109 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
110 { "notiling", DBG(NO_TILING), "Disable tiling" },
111 { "nodcc", DBG(NO_DCC), "Disable DCC." },
112 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
113 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
114 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
115 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
116
117 /* Tests: */
118 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
119 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
120 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
121 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
122 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
123 { "testgds", DBG(TEST_GDS), "Test GDS." },
124 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
125 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
126
127 DEBUG_NAMED_VALUE_END /* must be last */
128 };
129
130 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
131 {
132 /* Only create the less-optimizing version of the compiler on APUs
133 * predating Ryzen (Raven). */
134 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
135 sscreen->info.chip_class <= GFX8;
136
137 enum ac_target_machine_options tm_options =
138 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
139 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
140 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
141 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
142 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
143 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
144 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
145
146 ac_init_llvm_once();
147 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
148 compiler->passes = ac_create_llvm_passes(compiler->tm);
149
150 if (compiler->tm_wave32)
151 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
152 if (compiler->low_opt_tm)
153 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
154 }
155
156 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
157 {
158 ac_destroy_llvm_compiler(compiler);
159 }
160
161 /*
162 * pipe_context
163 */
164 static void si_destroy_context(struct pipe_context *context)
165 {
166 struct si_context *sctx = (struct si_context *)context;
167 int i;
168
169 util_queue_finish(&sctx->screen->shader_compiler_queue);
170 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
171
172 /* Unreference the framebuffer normally to disable related logic
173 * properly.
174 */
175 struct pipe_framebuffer_state fb = {};
176 if (context->set_framebuffer_state)
177 context->set_framebuffer_state(context, &fb);
178
179 si_release_all_descriptors(sctx);
180
181 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
182 gfx10_destroy_query(sctx);
183
184 pipe_resource_reference(&sctx->esgs_ring, NULL);
185 pipe_resource_reference(&sctx->gsvs_ring, NULL);
186 pipe_resource_reference(&sctx->tess_rings, NULL);
187 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
188 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
189 si_resource_reference(&sctx->border_color_buffer, NULL);
190 free(sctx->border_color_table);
191 si_resource_reference(&sctx->scratch_buffer, NULL);
192 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
193 si_resource_reference(&sctx->wait_mem_scratch, NULL);
194
195 si_pm4_free_state(sctx, sctx->init_config, ~0);
196 if (sctx->init_config_gs_rings)
197 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
198 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
199 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
200
201 if (sctx->fixed_func_tcs_shader.cso)
202 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
203 if (sctx->custom_dsa_flush)
204 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
205 if (sctx->custom_blend_resolve)
206 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
207 if (sctx->custom_blend_fmask_decompress)
208 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
209 if (sctx->custom_blend_eliminate_fastclear)
210 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
211 if (sctx->custom_blend_dcc_decompress)
212 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
213 if (sctx->vs_blit_pos)
214 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
215 if (sctx->vs_blit_pos_layered)
216 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
217 if (sctx->vs_blit_color)
218 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
219 if (sctx->vs_blit_color_layered)
220 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
221 if (sctx->vs_blit_texcoord)
222 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
223 if (sctx->cs_clear_buffer)
224 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
225 if (sctx->cs_copy_buffer)
226 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
227 if (sctx->cs_copy_image)
228 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
229 if (sctx->cs_copy_image_1d_array)
230 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
231 if (sctx->cs_clear_render_target)
232 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
233 if (sctx->cs_clear_render_target_1d_array)
234 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
235 if (sctx->cs_dcc_retile)
236 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
237
238 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
239 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
240 if (sctx->cs_fmask_expand[i][j]) {
241 sctx->b.delete_compute_state(&sctx->b,
242 sctx->cs_fmask_expand[i][j]);
243 }
244 }
245 }
246
247 if (sctx->blitter)
248 util_blitter_destroy(sctx->blitter);
249
250 /* Release DCC stats. */
251 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
252 assert(!sctx->dcc_stats[i].query_active);
253
254 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
255 if (sctx->dcc_stats[i].ps_stats[j])
256 sctx->b.destroy_query(&sctx->b,
257 sctx->dcc_stats[i].ps_stats[j]);
258
259 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
260 }
261
262 if (sctx->query_result_shader)
263 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
264 if (sctx->sh_query_result_shader)
265 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
266
267 if (sctx->gfx_cs)
268 sctx->ws->cs_destroy(sctx->gfx_cs);
269 if (sctx->dma_cs)
270 sctx->ws->cs_destroy(sctx->dma_cs);
271 if (sctx->ctx)
272 sctx->ws->ctx_destroy(sctx->ctx);
273
274 if (sctx->b.stream_uploader)
275 u_upload_destroy(sctx->b.stream_uploader);
276 if (sctx->b.const_uploader)
277 u_upload_destroy(sctx->b.const_uploader);
278 if (sctx->cached_gtt_allocator)
279 u_upload_destroy(sctx->cached_gtt_allocator);
280
281 slab_destroy_child(&sctx->pool_transfers);
282 slab_destroy_child(&sctx->pool_transfers_unsync);
283
284 if (sctx->allocator_zeroed_memory)
285 u_suballocator_destroy(sctx->allocator_zeroed_memory);
286
287 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
288 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
289 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
290 si_resource_reference(&sctx->eop_bug_scratch, NULL);
291 si_resource_reference(&sctx->index_ring, NULL);
292 si_resource_reference(&sctx->barrier_buf, NULL);
293 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
294 pb_reference(&sctx->gds, NULL);
295 pb_reference(&sctx->gds_oa, NULL);
296
297 si_destroy_compiler(&sctx->compiler);
298
299 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
300
301 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
302 _mesa_hash_table_destroy(sctx->img_handles, NULL);
303
304 util_dynarray_fini(&sctx->resident_tex_handles);
305 util_dynarray_fini(&sctx->resident_img_handles);
306 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
307 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
308 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
309 si_unref_sdma_uploads(sctx);
310 free(sctx->sdma_uploads);
311 FREE(sctx);
312 }
313
314 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
315 {
316 struct si_context *sctx = (struct si_context *)ctx;
317 struct si_screen *sscreen = sctx->screen;
318 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx);
319
320 if (status != PIPE_NO_RESET) {
321 /* Call the state tracker to set a no-op API dispatch. */
322 if (sctx->device_reset_callback.reset) {
323 sctx->device_reset_callback.reset(sctx->device_reset_callback.data,
324 status);
325 }
326
327 /* Re-create the auxiliary context, because it won't submit
328 * any new IBs due to a GPU reset.
329 */
330 simple_mtx_lock(&sscreen->aux_context_lock);
331
332 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
333 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
334 sscreen->aux_context->destroy(sscreen->aux_context);
335
336 sscreen->aux_context = si_create_context(&sscreen->b,
337 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
338 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
339 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
340 simple_mtx_unlock(&sscreen->aux_context_lock);
341 }
342 return status;
343 }
344
345 static void si_set_device_reset_callback(struct pipe_context *ctx,
346 const struct pipe_device_reset_callback *cb)
347 {
348 struct si_context *sctx = (struct si_context *)ctx;
349
350 if (cb)
351 sctx->device_reset_callback = *cb;
352 else
353 memset(&sctx->device_reset_callback, 0,
354 sizeof(sctx->device_reset_callback));
355 }
356
357 /* Apitrace profiling:
358 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
359 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
360 * and remember its number.
361 * 3) In Mesa, enable queries and performance counters around that draw
362 * call and print the results.
363 * 4) glretrace --benchmark --markers ..
364 */
365 static void si_emit_string_marker(struct pipe_context *ctx,
366 const char *string, int len)
367 {
368 struct si_context *sctx = (struct si_context *)ctx;
369
370 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
371
372 if (sctx->log)
373 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
374 }
375
376 static void si_set_debug_callback(struct pipe_context *ctx,
377 const struct pipe_debug_callback *cb)
378 {
379 struct si_context *sctx = (struct si_context *)ctx;
380 struct si_screen *screen = sctx->screen;
381
382 util_queue_finish(&screen->shader_compiler_queue);
383 util_queue_finish(&screen->shader_compiler_queue_low_priority);
384
385 if (cb)
386 sctx->debug = *cb;
387 else
388 memset(&sctx->debug, 0, sizeof(sctx->debug));
389 }
390
391 static void si_set_log_context(struct pipe_context *ctx,
392 struct u_log_context *log)
393 {
394 struct si_context *sctx = (struct si_context *)ctx;
395 sctx->log = log;
396
397 if (log)
398 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
399 }
400
401 static void si_set_context_param(struct pipe_context *ctx,
402 enum pipe_context_param param,
403 unsigned value)
404 {
405 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
406
407 switch (param) {
408 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
409 ws->pin_threads_to_L3_cache(ws, value);
410 break;
411 default:;
412 }
413 }
414
415 static struct pipe_context *si_create_context(struct pipe_screen *screen,
416 unsigned flags)
417 {
418 struct si_screen* sscreen = (struct si_screen *)screen;
419
420 /* Don't create a context if it's not compute-only and hw is compute-only. */
421 if (!sscreen->info.has_graphics &&
422 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
423 return NULL;
424
425 struct si_context *sctx = CALLOC_STRUCT(si_context);
426 struct radeon_winsys *ws = sscreen->ws;
427 int shader, i;
428 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
429
430 if (!sctx)
431 return NULL;
432
433 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
434 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
435
436 if (flags & PIPE_CONTEXT_DEBUG)
437 sscreen->record_llvm_ir = true; /* racy but not critical */
438
439 sctx->b.screen = screen; /* this must be set first */
440 sctx->b.priv = NULL;
441 sctx->b.destroy = si_destroy_context;
442 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
443 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
444
445 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
446 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
447
448 sctx->ws = sscreen->ws;
449 sctx->family = sscreen->info.family;
450 sctx->chip_class = sscreen->info.chip_class;
451
452 if (sctx->chip_class == GFX7 ||
453 sctx->chip_class == GFX8 ||
454 sctx->chip_class == GFX9) {
455 sctx->eop_bug_scratch = si_resource(
456 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
457 16 * sscreen->info.num_render_backends));
458 if (!sctx->eop_bug_scratch)
459 goto fail;
460 }
461
462 /* Initialize context allocators. */
463 sctx->allocator_zeroed_memory =
464 u_suballocator_create(&sctx->b, 128 * 1024,
465 0, PIPE_USAGE_DEFAULT,
466 SI_RESOURCE_FLAG_UNMAPPABLE |
467 SI_RESOURCE_FLAG_CLEAR, false);
468 if (!sctx->allocator_zeroed_memory)
469 goto fail;
470
471 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
472 0, PIPE_USAGE_STREAM,
473 SI_RESOURCE_FLAG_READ_ONLY);
474 if (!sctx->b.stream_uploader)
475 goto fail;
476
477 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
478 0, PIPE_USAGE_STAGING, 0);
479 if (!sctx->cached_gtt_allocator)
480 goto fail;
481
482 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
483 if (!sctx->ctx)
484 goto fail;
485
486 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
487 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
488 (void*)si_flush_dma_cs,
489 sctx, stop_exec_on_failure);
490 }
491
492 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
493 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
494 0, PIPE_USAGE_DEFAULT,
495 SI_RESOURCE_FLAG_32BIT |
496 (use_sdma_upload ?
497 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
498 if (!sctx->b.const_uploader)
499 goto fail;
500
501 if (use_sdma_upload)
502 u_upload_enable_flush_explicit(sctx->b.const_uploader);
503
504 sctx->gfx_cs = ws->cs_create(sctx->ctx,
505 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
506 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
507
508 /* Border colors. */
509 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
510 sizeof(*sctx->border_color_table));
511 if (!sctx->border_color_table)
512 goto fail;
513
514 sctx->border_color_buffer = si_resource(
515 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
516 SI_MAX_BORDER_COLORS *
517 sizeof(*sctx->border_color_table)));
518 if (!sctx->border_color_buffer)
519 goto fail;
520
521 sctx->border_color_map =
522 ws->buffer_map(sctx->border_color_buffer->buf,
523 NULL, PIPE_TRANSFER_WRITE);
524 if (!sctx->border_color_map)
525 goto fail;
526
527 sctx->ngg = sscreen->use_ngg;
528
529 /* Initialize context functions used by graphics and compute. */
530 if (sctx->chip_class >= GFX10)
531 sctx->emit_cache_flush = gfx10_emit_cache_flush;
532 else
533 sctx->emit_cache_flush = si_emit_cache_flush;
534
535 sctx->b.emit_string_marker = si_emit_string_marker;
536 sctx->b.set_debug_callback = si_set_debug_callback;
537 sctx->b.set_log_context = si_set_log_context;
538 sctx->b.set_context_param = si_set_context_param;
539 sctx->b.get_device_reset_status = si_get_reset_status;
540 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
541
542 si_init_all_descriptors(sctx);
543 si_init_buffer_functions(sctx);
544 si_init_clear_functions(sctx);
545 si_init_blit_functions(sctx);
546 si_init_compute_functions(sctx);
547 si_init_compute_blit_functions(sctx);
548 si_init_debug_functions(sctx);
549 si_init_fence_functions(sctx);
550 si_init_query_functions(sctx);
551 si_init_state_compute_functions(sctx);
552 si_init_context_texture_functions(sctx);
553
554 /* Initialize graphics-only context functions. */
555 if (sctx->has_graphics) {
556 if (sctx->chip_class >= GFX10)
557 gfx10_init_query(sctx);
558 si_init_msaa_functions(sctx);
559 si_init_shader_functions(sctx);
560 si_init_state_functions(sctx);
561 si_init_streamout_functions(sctx);
562 si_init_viewport_functions(sctx);
563
564 sctx->blitter = util_blitter_create(&sctx->b);
565 if (sctx->blitter == NULL)
566 goto fail;
567 sctx->blitter->skip_viewport_restore = true;
568
569 /* Some states are expected to be always non-NULL. */
570 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
571 sctx->queued.named.blend = sctx->noop_blend;
572
573 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
574 sctx->queued.named.dsa = sctx->noop_dsa;
575
576 sctx->discard_rasterizer_state =
577 util_blitter_get_discard_rasterizer_state(sctx->blitter);
578 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
579
580 si_init_draw_functions(sctx);
581 si_initialize_prim_discard_tunables(sctx);
582 }
583
584 /* Initialize SDMA functions. */
585 if (sctx->chip_class >= GFX7)
586 cik_init_sdma_functions(sctx);
587 else
588 si_init_dma_functions(sctx);
589
590 if (sscreen->debug_flags & DBG(FORCE_DMA))
591 sctx->b.resource_copy_region = sctx->dma_copy;
592
593 sctx->sample_mask = 0xffff;
594
595 /* Initialize multimedia functions. */
596 if (sscreen->info.has_hw_decode) {
597 sctx->b.create_video_codec = si_uvd_create_decoder;
598 sctx->b.create_video_buffer = si_video_buffer_create;
599 } else {
600 sctx->b.create_video_codec = vl_create_decoder;
601 sctx->b.create_video_buffer = vl_video_buffer_create;
602 }
603
604 if (sctx->chip_class >= GFX9) {
605 sctx->wait_mem_scratch = si_resource(
606 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
607 if (!sctx->wait_mem_scratch)
608 goto fail;
609
610 /* Initialize the memory. */
611 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
612 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
613 }
614
615 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
616 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
617 if (sctx->chip_class == GFX7) {
618 sctx->null_const_buf.buffer =
619 pipe_aligned_buffer_create(screen,
620 SI_RESOURCE_FLAG_32BIT,
621 PIPE_USAGE_DEFAULT, 16,
622 sctx->screen->info.tcc_cache_line_size);
623 if (!sctx->null_const_buf.buffer)
624 goto fail;
625 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
626
627 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
628 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
629 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
630 sctx->b.set_constant_buffer(&sctx->b, shader, i,
631 &sctx->null_const_buf);
632 }
633 }
634
635 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
636 &sctx->null_const_buf);
637 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
638 &sctx->null_const_buf);
639 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
640 &sctx->null_const_buf);
641 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
642 &sctx->null_const_buf);
643 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
644 &sctx->null_const_buf);
645 }
646
647 uint64_t max_threads_per_block;
648 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
649 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
650 &max_threads_per_block);
651
652 /* The maximum number of scratch waves. Scratch space isn't divided
653 * evenly between CUs. The number is only a function of the number of CUs.
654 * We can decrease the constant to decrease the scratch buffer size.
655 *
656 * sctx->scratch_waves must be >= the maximum posible size of
657 * 1 threadgroup, so that the hw doesn't hang from being unable
658 * to start any.
659 *
660 * The recommended value is 4 per CU at most. Higher numbers don't
661 * bring much benefit, but they still occupy chip resources (think
662 * async compute). I've seen ~2% performance difference between 4 and 32.
663 */
664 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
665 max_threads_per_block / 64);
666
667 si_init_compiler(sscreen, &sctx->compiler);
668
669 /* Bindless handles. */
670 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
671 _mesa_key_pointer_equal);
672 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
673 _mesa_key_pointer_equal);
674
675 util_dynarray_init(&sctx->resident_tex_handles, NULL);
676 util_dynarray_init(&sctx->resident_img_handles, NULL);
677 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
678 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
679 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
680
681 sctx->sample_pos_buffer =
682 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
683 sizeof(sctx->sample_positions));
684 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
685 sizeof(sctx->sample_positions), &sctx->sample_positions);
686
687 /* this must be last */
688 si_begin_new_gfx_cs(sctx);
689
690 if (sctx->chip_class == GFX7) {
691 /* Clear the NULL constant buffer, because loads should return zeros.
692 * Note that this forces CP DMA to be used, because clover deadlocks
693 * for some reason when the compute codepath is used.
694 */
695 uint32_t clear_value = 0;
696 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
697 sctx->null_const_buf.buffer->width0,
698 &clear_value, 4, SI_COHERENCY_SHADER, true);
699 }
700 return &sctx->b;
701 fail:
702 fprintf(stderr, "radeonsi: Failed to create a context.\n");
703 si_destroy_context(&sctx->b);
704 return NULL;
705 }
706
707 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
708 void *priv, unsigned flags)
709 {
710 struct si_screen *sscreen = (struct si_screen *)screen;
711 struct pipe_context *ctx;
712
713 if (sscreen->debug_flags & DBG(CHECK_VM))
714 flags |= PIPE_CONTEXT_DEBUG;
715
716 ctx = si_create_context(screen, flags);
717
718 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
719 return ctx;
720
721 /* Clover (compute-only) is unsupported. */
722 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
723 return ctx;
724
725 /* When shaders are logged to stderr, asynchronous compilation is
726 * disabled too. */
727 if (sscreen->debug_flags & DBG_ALL_SHADERS)
728 return ctx;
729
730 /* Use asynchronous flushes only on amdgpu, since the radeon
731 * implementation for fence_server_sync is incomplete. */
732 return threaded_context_create(ctx, &sscreen->pool_transfers,
733 si_replace_buffer_storage,
734 sscreen->info.is_amdgpu ? si_create_fence : NULL,
735 &((struct si_context*)ctx)->tc);
736 }
737
738 /*
739 * pipe_screen
740 */
741 static void si_destroy_screen(struct pipe_screen* pscreen)
742 {
743 struct si_screen *sscreen = (struct si_screen *)pscreen;
744 struct si_shader_part *parts[] = {
745 sscreen->vs_prologs,
746 sscreen->tcs_epilogs,
747 sscreen->gs_prologs,
748 sscreen->ps_prologs,
749 sscreen->ps_epilogs
750 };
751 unsigned i;
752
753 if (!sscreen->ws->unref(sscreen->ws))
754 return;
755
756 simple_mtx_destroy(&sscreen->aux_context_lock);
757
758 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
759 if (aux_log) {
760 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
761 u_log_context_destroy(aux_log);
762 FREE(aux_log);
763 }
764
765 sscreen->aux_context->destroy(sscreen->aux_context);
766
767 util_queue_destroy(&sscreen->shader_compiler_queue);
768 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
769
770 /* Release the reference on glsl types of the compiler threads. */
771 glsl_type_singleton_decref();
772
773 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
774 si_destroy_compiler(&sscreen->compiler[i]);
775
776 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
777 si_destroy_compiler(&sscreen->compiler_lowp[i]);
778
779 /* Free shader parts. */
780 for (i = 0; i < ARRAY_SIZE(parts); i++) {
781 while (parts[i]) {
782 struct si_shader_part *part = parts[i];
783
784 parts[i] = part->next;
785 si_shader_binary_clean(&part->binary);
786 FREE(part);
787 }
788 }
789 simple_mtx_destroy(&sscreen->shader_parts_mutex);
790 si_destroy_shader_cache(sscreen);
791
792 si_destroy_perfcounters(sscreen);
793 si_gpu_load_kill_thread(sscreen);
794
795 simple_mtx_destroy(&sscreen->gpu_load_mutex);
796
797 slab_destroy_parent(&sscreen->pool_transfers);
798
799 disk_cache_destroy(sscreen->disk_shader_cache);
800 sscreen->ws->destroy(sscreen->ws);
801 FREE(sscreen);
802 }
803
804 static void si_init_gs_info(struct si_screen *sscreen)
805 {
806 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
807 sscreen->info.family);
808 }
809
810 static void si_test_vmfault(struct si_screen *sscreen)
811 {
812 struct pipe_context *ctx = sscreen->aux_context;
813 struct si_context *sctx = (struct si_context *)ctx;
814 struct pipe_resource *buf =
815 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
816
817 if (!buf) {
818 puts("Buffer allocation failed.");
819 exit(1);
820 }
821
822 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
823
824 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
825 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
826 SI_COHERENCY_NONE, L2_BYPASS);
827 ctx->flush(ctx, NULL, 0);
828 puts("VM fault test: CP - done.");
829 }
830 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
831 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
832 ctx->flush(ctx, NULL, 0);
833 puts("VM fault test: SDMA - done.");
834 }
835 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
836 util_test_constant_buffer(ctx, buf);
837 puts("VM fault test: Shader - done.");
838 }
839 exit(0);
840 }
841
842 static void si_test_gds_memory_management(struct si_context *sctx,
843 unsigned alloc_size, unsigned alignment,
844 enum radeon_bo_domain domain)
845 {
846 struct radeon_winsys *ws = sctx->ws;
847 struct radeon_cmdbuf *cs[8];
848 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
849
850 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
851 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
852 NULL, NULL, false);
853 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
854 assert(gds_bo[i]);
855 }
856
857 for (unsigned iterations = 0; iterations < 20000; iterations++) {
858 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
859 /* This clears GDS with CP DMA.
860 *
861 * We don't care if GDS is present. Just add some packet
862 * to make the GPU busy for a moment.
863 */
864 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
865 SI_CPDMA_SKIP_BO_LIST_UPDATE |
866 SI_CPDMA_SKIP_CHECK_CS_SPACE |
867 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
868
869 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
870 RADEON_USAGE_READWRITE, 0);
871 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
872 }
873 }
874 exit(0);
875 }
876
877 static void si_disk_cache_create(struct si_screen *sscreen)
878 {
879 /* Don't use the cache if shader dumping is enabled. */
880 if (sscreen->debug_flags & DBG_ALL_SHADERS)
881 return;
882
883 struct mesa_sha1 ctx;
884 unsigned char sha1[20];
885 char cache_id[20 * 2 + 1];
886
887 _mesa_sha1_init(&ctx);
888
889 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
890 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
891 &ctx))
892 return;
893
894 _mesa_sha1_final(&ctx, sha1);
895 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
896
897 /* These flags affect shader compilation. */
898 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
899 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
900
901 /* Add the high bits of 32-bit addresses, which affects
902 * how 32-bit addresses are expanded to 64 bits.
903 */
904 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
905 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
906 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
907
908 sscreen->disk_shader_cache =
909 disk_cache_create(sscreen->info.name,
910 cache_id,
911 shader_debug_flags);
912 }
913
914 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
915 unsigned max_threads)
916 {
917 struct si_screen *sscreen = (struct si_screen *)screen;
918
919 /* This function doesn't allow a greater number of threads than
920 * the queue had at its creation. */
921 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
922 max_threads);
923 /* Don't change the number of threads on the low priority queue. */
924 }
925
926 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
927 void *shader,
928 enum pipe_shader_type shader_type)
929 {
930 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
931
932 return util_queue_fence_is_signalled(&sel->ready);
933 }
934
935 static struct pipe_screen *
936 radeonsi_screen_create_impl(struct radeon_winsys *ws,
937 const struct pipe_screen_config *config)
938 {
939 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
940 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
941
942 if (!sscreen) {
943 return NULL;
944 }
945
946 sscreen->ws = ws;
947 ws->query_info(ws, &sscreen->info);
948
949 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
950 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
951 FREE(sscreen);
952 return NULL;
953 }
954
955 if (sscreen->info.chip_class >= GFX9) {
956 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
957 } else {
958 ac_get_raster_config(&sscreen->info,
959 &sscreen->pa_sc_raster_config,
960 &sscreen->pa_sc_raster_config_1,
961 &sscreen->se_tile_repeat);
962 }
963
964 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
965 debug_options, 0);
966 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
967 debug_options, 0);
968
969 if (sscreen->debug_flags & DBG(NO_GFX))
970 sscreen->info.has_graphics = false;
971
972 /* Set functions first. */
973 sscreen->b.context_create = si_pipe_create_context;
974 sscreen->b.destroy = si_destroy_screen;
975 sscreen->b.set_max_shader_compiler_threads =
976 si_set_max_shader_compiler_threads;
977 sscreen->b.is_parallel_shader_compilation_finished =
978 si_is_parallel_shader_compilation_finished;
979 sscreen->b.finalize_nir = si_finalize_nir;
980
981 si_init_screen_get_functions(sscreen);
982 si_init_screen_buffer_functions(sscreen);
983 si_init_screen_fence_functions(sscreen);
984 si_init_screen_state_functions(sscreen);
985 si_init_screen_texture_functions(sscreen);
986 si_init_screen_query_functions(sscreen);
987
988 /* Set these flags in debug_flags early, so that the shader cache takes
989 * them into account.
990 */
991 if (driQueryOptionb(config->options,
992 "glsl_correct_derivatives_after_discard"))
993 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
994 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
995 sscreen->debug_flags |= DBG(SI_SCHED);
996
997 if (sscreen->debug_flags & DBG(INFO))
998 ac_print_gpu_info(&sscreen->info);
999
1000 slab_create_parent(&sscreen->pool_transfers,
1001 sizeof(struct si_transfer), 64);
1002
1003 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1004 if (sscreen->force_aniso == -1) {
1005 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1006 }
1007
1008 if (sscreen->force_aniso >= 0) {
1009 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1010 /* round down to a power of two */
1011 1 << util_logbase2(sscreen->force_aniso));
1012 }
1013
1014 (void) simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
1015 (void) simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1016
1017 si_init_gs_info(sscreen);
1018 if (!si_init_shader_cache(sscreen)) {
1019 FREE(sscreen);
1020 return NULL;
1021 }
1022
1023 si_disk_cache_create(sscreen);
1024
1025 /* Determine the number of shader compiler threads. */
1026 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1027
1028 if (hw_threads >= 12) {
1029 num_comp_hi_threads = hw_threads * 3 / 4;
1030 num_comp_lo_threads = hw_threads / 3;
1031 } else if (hw_threads >= 6) {
1032 num_comp_hi_threads = hw_threads - 2;
1033 num_comp_lo_threads = hw_threads / 2;
1034 } else if (hw_threads >= 2) {
1035 num_comp_hi_threads = hw_threads - 1;
1036 num_comp_lo_threads = hw_threads / 2;
1037 } else {
1038 num_comp_hi_threads = 1;
1039 num_comp_lo_threads = 1;
1040 }
1041
1042 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1043 ARRAY_SIZE(sscreen->compiler));
1044 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1045 ARRAY_SIZE(sscreen->compiler_lowp));
1046
1047 /* Take a reference on the glsl types for the compiler threads. */
1048 glsl_type_singleton_init_or_ref();
1049
1050 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1051 64, num_comp_hi_threads,
1052 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1053 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1054 si_destroy_shader_cache(sscreen);
1055 FREE(sscreen);
1056 glsl_type_singleton_decref();
1057 return NULL;
1058 }
1059
1060 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1061 "shlo",
1062 64, num_comp_lo_threads,
1063 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1064 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1065 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1066 si_destroy_shader_cache(sscreen);
1067 FREE(sscreen);
1068 glsl_type_singleton_decref();
1069 return NULL;
1070 }
1071
1072 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1073 si_init_perfcounters(sscreen);
1074
1075 /* Determine tessellation ring info. */
1076 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1077 sscreen->info.family != CHIP_CARRIZO &&
1078 sscreen->info.family != CHIP_STONEY;
1079 /* This must be one less than the maximum number due to a hw limitation.
1080 * Various hardware bugs need this.
1081 */
1082 unsigned max_offchip_buffers_per_se;
1083
1084 if (sscreen->info.chip_class >= GFX10)
1085 max_offchip_buffers_per_se = 256;
1086 /* Only certain chips can use the maximum value. */
1087 else if (sscreen->info.family == CHIP_VEGA12 ||
1088 sscreen->info.family == CHIP_VEGA20)
1089 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1090 else
1091 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1092
1093 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1094 sscreen->info.max_se;
1095 unsigned offchip_granularity;
1096
1097 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1098 * around by setting 4K granularity.
1099 */
1100 if (sscreen->info.family == CHIP_HAWAII) {
1101 sscreen->tess_offchip_block_dw_size = 4096;
1102 offchip_granularity = V_03093C_X_4K_DWORDS;
1103 } else {
1104 sscreen->tess_offchip_block_dw_size = 8192;
1105 offchip_granularity = V_03093C_X_8K_DWORDS;
1106 }
1107
1108 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1109 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1110 sscreen->tess_offchip_block_dw_size * 4;
1111
1112 if (sscreen->info.chip_class >= GFX7) {
1113 if (sscreen->info.chip_class >= GFX8)
1114 --max_offchip_buffers;
1115 sscreen->vgt_hs_offchip_param =
1116 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1117 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1118 } else {
1119 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1120 sscreen->vgt_hs_offchip_param =
1121 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1122 }
1123
1124 sscreen->has_draw_indirect_multi =
1125 (sscreen->info.family >= CHIP_POLARIS10) ||
1126 (sscreen->info.chip_class == GFX8 &&
1127 sscreen->info.pfp_fw_version >= 121 &&
1128 sscreen->info.me_fw_version >= 87) ||
1129 (sscreen->info.chip_class == GFX7 &&
1130 sscreen->info.pfp_fw_version >= 211 &&
1131 sscreen->info.me_fw_version >= 173) ||
1132 (sscreen->info.chip_class == GFX6 &&
1133 sscreen->info.pfp_fw_version >= 79 &&
1134 sscreen->info.me_fw_version >= 142);
1135
1136 sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast &&
1137 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1138 sscreen->assume_no_z_fights =
1139 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1140 sscreen->commutative_blend_add =
1141 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1142
1143 {
1144 #define OPT_BOOL(name, dflt, description) \
1145 sscreen->options.name = \
1146 driQueryOptionb(config->options, "radeonsi_"#name);
1147 #include "si_debug_options.h"
1148 }
1149
1150 sscreen->use_ngg = sscreen->info.chip_class >= GFX10 &&
1151 sscreen->info.family != CHIP_NAVI14 &&
1152 !(sscreen->debug_flags & DBG(NO_NGG));
1153 sscreen->use_ngg_streamout = false;
1154
1155 /* Only enable primitive binning on APUs by default. */
1156 if (sscreen->info.chip_class >= GFX10) {
1157 sscreen->dpbb_allowed = true;
1158 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1159 } else if (sscreen->info.chip_class == GFX9) {
1160 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1161 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1162 }
1163
1164 /* Process DPBB enable flags. */
1165 if (sscreen->debug_flags & DBG(DPBB)) {
1166 sscreen->dpbb_allowed = true;
1167 if (sscreen->debug_flags & DBG(DFSM))
1168 sscreen->dfsm_allowed = true;
1169 }
1170
1171 /* Process DPBB disable flags. */
1172 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1173 sscreen->dpbb_allowed = false;
1174 sscreen->dfsm_allowed = false;
1175 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1176 sscreen->dfsm_allowed = false;
1177 }
1178
1179 /* While it would be nice not to have this flag, we are constrained
1180 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1181 */
1182 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1183
1184 sscreen->dcc_msaa_allowed =
1185 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1186
1187 (void) simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1188 sscreen->use_monolithic_shaders =
1189 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1190
1191 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1192 SI_CONTEXT_INV_VCACHE;
1193 if (sscreen->info.chip_class <= GFX8) {
1194 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1195 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1196 }
1197
1198 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1199 sscreen->debug_flags |= DBG_ALL_SHADERS;
1200
1201 /* Syntax:
1202 * EQAA=s,z,c
1203 * Example:
1204 * EQAA=8,4,2
1205
1206 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1207 * Constraints:
1208 * s >= z >= c (ignoring this only wastes memory)
1209 * s = [2..16]
1210 * z = [2..8]
1211 * c = [2..8]
1212 *
1213 * Only MSAA color and depth buffers are overriden.
1214 */
1215 if (sscreen->info.has_eqaa_surface_allocator) {
1216 const char *eqaa = debug_get_option("EQAA", NULL);
1217 unsigned s,z,f;
1218
1219 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1220 sscreen->eqaa_force_coverage_samples = s;
1221 sscreen->eqaa_force_z_samples = z;
1222 sscreen->eqaa_force_color_samples = f;
1223 }
1224 }
1225
1226 sscreen->ge_wave_size = 64;
1227 sscreen->ps_wave_size = 64;
1228 sscreen->compute_wave_size = 64;
1229
1230 if (sscreen->info.chip_class >= GFX10) {
1231 /* Pixels shaders: Wave64 is recommended.
1232 * Compute shaders: There are piglit failures with Wave32.
1233 */
1234 sscreen->ge_wave_size = 32;
1235
1236 if (sscreen->debug_flags & DBG(W32_GE))
1237 sscreen->ge_wave_size = 32;
1238 if (sscreen->debug_flags & DBG(W32_PS))
1239 sscreen->ps_wave_size = 32;
1240 if (sscreen->debug_flags & DBG(W32_CS))
1241 sscreen->compute_wave_size = 32;
1242
1243 if (sscreen->debug_flags & DBG(W64_GE))
1244 sscreen->ge_wave_size = 64;
1245 if (sscreen->debug_flags & DBG(W64_PS))
1246 sscreen->ps_wave_size = 64;
1247 if (sscreen->debug_flags & DBG(W64_CS))
1248 sscreen->compute_wave_size = 64;
1249 }
1250
1251 /* Create the auxiliary context. This must be done last. */
1252 sscreen->aux_context = si_create_context(&sscreen->b,
1253 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1254 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1255 if (sscreen->options.aux_debug) {
1256 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1257 u_log_context_init(log);
1258 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1259 }
1260
1261 if (sscreen->debug_flags & DBG(TEST_DMA))
1262 si_test_dma(sscreen);
1263
1264 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1265 si_test_dma_perf(sscreen);
1266 }
1267
1268 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1269 DBG(TEST_VMFAULT_SDMA) |
1270 DBG(TEST_VMFAULT_SHADER)))
1271 si_test_vmfault(sscreen);
1272
1273 if (sscreen->debug_flags & DBG(TEST_GDS))
1274 si_test_gds((struct si_context*)sscreen->aux_context);
1275
1276 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1277 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1278 32 * 1024, 4, RADEON_DOMAIN_GDS);
1279 }
1280 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1281 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1282 4, 1, RADEON_DOMAIN_OA);
1283 }
1284
1285 return &sscreen->b;
1286 }
1287
1288 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1289 {
1290 drmVersionPtr version = drmGetVersion(fd);
1291 struct radeon_winsys *rw = NULL;
1292
1293 switch (version->version_major) {
1294 case 2:
1295 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1296 break;
1297 case 3:
1298 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1299 break;
1300 }
1301
1302 drmFreeVersion(version);
1303 return rw ? rw->screen : NULL;
1304 }