src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  46         r600_resource_reference(&sctx->border_color_table, NULL);
  47         r600_resource_reference(&sctx->scratch_buffer, NULL);
  48         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  49
  50         si_pm4_free_state(sctx, sctx->init_config, ~0);
  51         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  52         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  53                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  54
  55         if (sctx->pstipple_sampler_state)
  56                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  57         if (sctx->dummy_pixel_shader) {
  58                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  59         }
  60         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  61         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  62         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  63         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  64         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  65
  66         util_blitter_destroy(sctx->blitter);
  67
  68         si_pm4_cleanup(sctx);
  69
  70         r600_common_context_cleanup(&sctx->b);
  71
  72 #if HAVE_LLVM >= 0x0306
  73         LLVMDisposeTargetMachine(sctx->tm);
  74 #endif
  75
  76         FREE(sctx);
  77 }
  78
  79 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  80 {
  81         struct si_context *sctx = CALLOC_STRUCT(si_context);
  82         struct si_screen* sscreen = (struct si_screen *)screen;
  83         struct radeon_winsys *ws = sscreen->b.ws;
  84         LLVMTargetRef r600_target;
  85 #if HAVE_LLVM >= 0x0306
  86         const char *triple = "amdgcn--";
  87 #endif
  88         int shader, i;
  89
  90         if (sctx == NULL)
  91                 return NULL;
  92
  93         sctx->b.b.screen = screen; /* this must be set first */
  94         sctx->b.b.priv = priv;
  95         sctx->b.b.destroy = si_destroy_context;
  96         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
  97
  98         if (!r600_common_context_init(&sctx->b, &sscreen->b))
  99                 goto fail;
 100
 101         si_init_blit_functions(sctx);
 102         si_init_compute_functions(sctx);
 103
 104         if (sscreen->b.info.has_uvd) {
 105                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 106                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 107         } else {
 108                 sctx->b.b.create_video_codec = vl_create_decoder;
 109                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 110         }
 111
 112         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
 113                                              sctx, sscreen->b.trace_bo ?
 114                                                 sscreen->b.trace_bo->cs_buf : NULL);
 115         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 116
 117         si_init_all_descriptors(sctx);
 118
 119         /* Initialize cache_flush. */
 120         sctx->cache_flush = si_atom_cache_flush;
 121         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 122
 123         sctx->msaa_sample_locs = si_atom_msaa_sample_locs;
 124         sctx->atoms.s.msaa_sample_locs = &sctx->msaa_sample_locs;
 125
 126         sctx->msaa_config = si_atom_msaa_config;
 127         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 128
 129         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 130         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 131
 132         si_init_state_functions(sctx);
 133         si_init_shader_functions(sctx);
 134
 135         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 136                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 137
 138         sctx->blitter = util_blitter_create(&sctx->b.b);
 139         if (sctx->blitter == NULL)
 140                 goto fail;
 141         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 142
 143         /* these must be last */
 144         si_begin_new_cs(sctx);
 145         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 146
 147         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 148          * with a NULL buffer). We need to use a dummy buffer instead. */
 149         if (sctx->b.chip_class == CIK) {
 150                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 151                                                                  PIPE_USAGE_DEFAULT, 16);
 152                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 153
 154                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 155                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 156                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 157                                                               &sctx->null_const_buf);
 158                         }
 159                 }
 160
 161                 /* Clear the NULL constant buffer, because loads should return zeros. */
 162                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 163                                      sctx->null_const_buf.buffer->width0, 0, false);
 164         }
 165
 166         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 167          * this for non-cs shaders.  Using the wrong value here can result in
 168          * GPU lockups, but the maximum value seems to always work.
 169          */
 170         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 171
 172 #if HAVE_LLVM >= 0x0306
 173         /* Initialize LLVM TargetMachine */
 174         r600_target = radeon_llvm_get_r600_target(triple);
 175         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 176                                            r600_get_llvm_processor_name(sscreen->b.family),
 177                                            "+DumpCode,+vgpr-spilling",
 178                                            LLVMCodeGenLevelDefault,
 179                                            LLVMRelocDefault,
 180                                            LLVMCodeModelDefault);
 181 #endif
 182
 183         return &sctx->b.b;
 184 fail:
 185         si_destroy_context(&sctx->b.b);
 186         return NULL;
 187 }
 188
 189 /*
 190  * pipe_screen
 191  */
 192
 193 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 194 {
 195         struct si_screen *sscreen = (struct si_screen *)pscreen;
 196
 197         switch (param) {
 198         /* Supported features (boolean caps). */
 199         case PIPE_CAP_TWO_SIDED_STENCIL:
 200         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 201         case PIPE_CAP_ANISOTROPIC_FILTER:
 202         case PIPE_CAP_POINT_SPRITE:
 203         case PIPE_CAP_OCCLUSION_QUERY:
 204         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 205         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 206         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 207         case PIPE_CAP_TEXTURE_SWIZZLE:
 208         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 209         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 210         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 211         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 212         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 213         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 214         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 215         case PIPE_CAP_SM3:
 216         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 217         case PIPE_CAP_PRIMITIVE_RESTART:
 218         case PIPE_CAP_CONDITIONAL_RENDER:
 219         case PIPE_CAP_TEXTURE_BARRIER:
 220         case PIPE_CAP_INDEP_BLEND_ENABLE:
 221         case PIPE_CAP_INDEP_BLEND_FUNC:
 222         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 223         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 224         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 225         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 226         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 227         case PIPE_CAP_USER_INDEX_BUFFERS:
 228         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 229         case PIPE_CAP_START_INSTANCE:
 230         case PIPE_CAP_NPOT_TEXTURES:
 231         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 232         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 233         case PIPE_CAP_TGSI_INSTANCEID:
 234         case PIPE_CAP_COMPUTE:
 235         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 236         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 237         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 238         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 239         case PIPE_CAP_CUBE_MAP_ARRAY:
 240         case PIPE_CAP_SAMPLE_SHADING:
 241         case PIPE_CAP_DRAW_INDIRECT:
 242         case PIPE_CAP_CLIP_HALFZ:
 243         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 244         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 245         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 246         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 247         case PIPE_CAP_TGSI_TEXCOORD:
 248                 return 1;
 249
 250         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 251                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 252
 253         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 254                 return sscreen->b.info.drm_major == 2 && sscreen->b.info.drm_minor >= 43;
 255
 256         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 257                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 258                 return sscreen->b.chip_class < CIK ||
 259                        sscreen->b.info.drm_minor >= 35;
 260
 261         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 262                 return R600_MAP_BUFFER_ALIGNMENT;
 263
 264         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 265         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 266                 return 4;
 267
 268         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 269                 return 330;
 270
 271         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 272                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 273
 274         case PIPE_CAP_TEXTURE_QUERY_LOD:
 275         case PIPE_CAP_TEXTURE_GATHER_SM5:
 276                 return HAVE_LLVM >= 0x0305;
 277         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 278                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 279
 280         /* Unsupported features. */
 281         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 282         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 283         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 284         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 285         case PIPE_CAP_USER_VERTEX_BUFFERS:
 286         case PIPE_CAP_FAKE_SW_MSAA:
 287         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 288         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 289         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 290         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 291         case PIPE_CAP_VERTEXID_NOBASE:
 292         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 293                 return 0;
 294
 295         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 296                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 297
 298         /* Stream output. */
 299         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 300                 return sscreen->b.has_streamout ? 4 : 0;
 301         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 302                 return sscreen->b.has_streamout ? 1 : 0;
 303         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 304         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 305                 return sscreen->b.has_streamout ? 32*4 : 0;
 306
 307         /* Geometry shader output. */
 308         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 309                 return 1024;
 310         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 311                 return 4095;
 312         case PIPE_CAP_MAX_VERTEX_STREAMS:
 313                 return 1;
 314
 315         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 316                 return 2048;
 317
 318         /* Texturing. */
 319         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 320         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 321                 return 15; /* 16384 */
 322         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 323                 /* textures support 8192, but layered rendering supports 2048 */
 324                 return 12;
 325         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 326                 /* textures support 8192, but layered rendering supports 2048 */
 327                 return 2048;
 328
 329         /* Render targets. */
 330         case PIPE_CAP_MAX_RENDER_TARGETS:
 331                 return 8;
 332
 333         case PIPE_CAP_MAX_VIEWPORTS:
 334                 return 16;
 335
 336         /* Timer queries, present when the clock frequency is non zero. */
 337         case PIPE_CAP_QUERY_TIMESTAMP:
 338         case PIPE_CAP_QUERY_TIME_ELAPSED:
 339                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 340
 341         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 342         case PIPE_CAP_MIN_TEXEL_OFFSET:
 343                 return -32;
 344
 345         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 346         case PIPE_CAP_MAX_TEXEL_OFFSET:
 347                 return 31;
 348
 349         case PIPE_CAP_ENDIANNESS:
 350                 return PIPE_ENDIAN_LITTLE;
 351
 352         case PIPE_CAP_VENDOR_ID:
 353                 return 0x1002;
 354         case PIPE_CAP_DEVICE_ID:
 355                 return sscreen->b.info.pci_id;
 356         case PIPE_CAP_ACCELERATED:
 357                 return 1;
 358         case PIPE_CAP_VIDEO_MEMORY:
 359                 return sscreen->b.info.vram_size >> 20;
 360         case PIPE_CAP_UMA:
 361                 return 0;
 362         }
 363         return 0;
 364 }
 365
 366 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 367 {
 368         switch(shader)
 369         {
 370         case PIPE_SHADER_FRAGMENT:
 371         case PIPE_SHADER_VERTEX:
 372         case PIPE_SHADER_GEOMETRY:
 373                 break;
 374         case PIPE_SHADER_COMPUTE:
 375                 switch (param) {
 376                 case PIPE_SHADER_CAP_PREFERRED_IR:
 377 #if HAVE_LLVM < 0x0306
 378                         return PIPE_SHADER_IR_LLVM;
 379 #else
 380                         return PIPE_SHADER_IR_NATIVE;
 381 #endif
 382                 case PIPE_SHADER_CAP_DOUBLES:
 383                         return HAVE_LLVM >= 0x0307;
 384
 385                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 386                         uint64_t max_const_buffer_size;
 387                         pscreen->get_compute_param(pscreen,
 388                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 389                                 &max_const_buffer_size);
 390                         return max_const_buffer_size;
 391                 }
 392                 default:
 393                         /* If compute shaders don't require a special value
 394                          * for this cap, we can return the same value we
 395                          * do for other shader types. */
 396                         break;
 397                 }
 398                 break;
 399         default:
 400                 /* TODO: support tessellation */
 401                 return 0;
 402         }
 403
 404         switch (param) {
 405         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 406         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 407         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 408         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 409                 return 16384;
 410         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 411                 return 32;
 412         case PIPE_SHADER_CAP_MAX_INPUTS:
 413                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 414         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 415                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 416         case PIPE_SHADER_CAP_MAX_TEMPS:
 417                 return 256; /* Max native temporaries. */
 418         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 419                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 420         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 421                 return SI_NUM_USER_CONST_BUFFERS;
 422         case PIPE_SHADER_CAP_MAX_PREDS:
 423                 return 0; /* FIXME */
 424         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 425                 return 1;
 426         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 427                 return 1;
 428         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 429                 /* Indirection of geometry shader input dimension is not
 430                  * handled yet
 431                  */
 432                 return shader < PIPE_SHADER_GEOMETRY;
 433         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 434         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 435         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 436                 return 1;
 437         case PIPE_SHADER_CAP_INTEGERS:
 438                 return 1;
 439         case PIPE_SHADER_CAP_SUBROUTINES:
 440                 return 0;
 441         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 442         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 443                 return 16;
 444         case PIPE_SHADER_CAP_PREFERRED_IR:
 445                 return PIPE_SHADER_IR_TGSI;
 446         case PIPE_SHADER_CAP_DOUBLES:
 447                 return HAVE_LLVM >= 0x0307;
 448         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 449         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 450                 return 0;
 451         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 452         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 453                 return 1;
 454         }
 455         return 0;
 456 }
 457
 458 static void si_destroy_screen(struct pipe_screen* pscreen)
 459 {
 460         struct si_screen *sscreen = (struct si_screen *)pscreen;
 461
 462         if (sscreen == NULL)
 463                 return;
 464
 465         if (!sscreen->b.ws->unref(sscreen->b.ws))
 466                 return;
 467
 468         r600_destroy_common_screen(&sscreen->b);
 469 }
 470
 471 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 472
 473 /* Initialize pipe config. This is especially important for GPUs
 474  * with 16 pipes and more where it's initialized incorrectly by
 475  * the TILING_CONFIG ioctl. */
 476 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 477 {
 478         unsigned mode2d;
 479
 480         /* This is okay, because there can be no 2D tiling without
 481          * the tile mode array, so we won't need the pipe config.
 482          * Return "success".
 483          */
 484         if (!sscreen->b.info.si_tile_mode_array_valid)
 485                 return true;
 486
 487         /* The same index is used for the 2D mode on CIK too. */
 488         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 489
 490         switch (G_009910_PIPE_CONFIG(mode2d)) {
 491         case V_02803C_ADDR_SURF_P2:
 492                 sscreen->b.tiling_info.num_channels = 2;
 493                 break;
 494         case V_02803C_X_ADDR_SURF_P4_8X16:
 495         case V_02803C_X_ADDR_SURF_P4_16X16:
 496         case V_02803C_X_ADDR_SURF_P4_16X32:
 497         case V_02803C_X_ADDR_SURF_P4_32X32:
 498                 sscreen->b.tiling_info.num_channels = 4;
 499                 break;
 500         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 501         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 502         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 503         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 504         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 505         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 506         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 507                 sscreen->b.tiling_info.num_channels = 8;
 508                 break;
 509         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 510         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 511                 sscreen->b.tiling_info.num_channels = 16;
 512                 break;
 513         default:
 514                 assert(0);
 515                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 516                         G_009910_PIPE_CONFIG(mode2d));
 517                 return false;
 518         }
 519         return true;
 520 }
 521
 522 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 523 {
 524         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 525
 526         if (sscreen == NULL) {
 527                 return NULL;
 528         }
 529
 530         /* Set functions first. */
 531         sscreen->b.b.context_create = si_create_context;
 532         sscreen->b.b.destroy = si_destroy_screen;
 533         sscreen->b.b.get_param = si_get_param;
 534         sscreen->b.b.get_shader_param = si_get_shader_param;
 535         sscreen->b.b.is_format_supported = si_is_format_supported;
 536         sscreen->b.b.resource_create = r600_resource_create_common;
 537
 538         if (!r600_common_screen_init(&sscreen->b, ws) ||
 539             !si_initialize_pipe_config(sscreen)) {
 540                 FREE(sscreen);
 541                 return NULL;
 542         }
 543
 544         sscreen->b.has_cp_dma = true;
 545         sscreen->b.has_streamout = true;
 546
 547         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 548                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 549
 550         /* Create the auxiliary context. This must be done last. */
 551         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 552
 553         return &sscreen->b.b;
 554 }