src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_buffer, NULL);
  48         free(sctx->border_color_table);
  49         r600_resource_reference(&sctx->scratch_buffer, NULL);
  50         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  51
  52         si_pm4_free_state(sctx, sctx->init_config, ~0);
  53         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  54                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  55
  56         if (sctx->pstipple_sampler_state)
  57                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  58         if (sctx->dummy_pixel_shader)
  59                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  60         if (sctx->fixed_func_tcs_shader)
  61                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader);
  62         if (sctx->custom_dsa_flush)
  63                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  64         if (sctx->custom_blend_resolve)
  65                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  66         if (sctx->custom_blend_decompress)
  67                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  68         if (sctx->custom_blend_fastclear)
  69                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  70         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  71
  72         if (sctx->blitter)
  73                 util_blitter_destroy(sctx->blitter);
  74
  75         r600_common_context_cleanup(&sctx->b);
  76
  77 #if HAVE_LLVM >= 0x0306
  78         LLVMDisposeTargetMachine(sctx->tm);
  79 #endif
  80
  81         r600_resource_reference(&sctx->trace_buf, NULL);
  82         r600_resource_reference(&sctx->last_trace_buf, NULL);
  83         free(sctx->last_ib);
  84         if (sctx->last_bo_list) {
  85                 for (i = 0; i < sctx->last_bo_count; i++)
  86                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  87                 free(sctx->last_bo_list);
  88         }
  89         FREE(sctx);
  90 }
  91
  92 static enum pipe_reset_status
  93 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  94 {
  95         struct si_context *sctx = (struct si_context *)ctx;
  96
  97         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  98 }
  99
 100 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 101                                               void *priv, unsigned flags)
 102 {
 103         struct si_context *sctx = CALLOC_STRUCT(si_context);
 104         struct si_screen* sscreen = (struct si_screen *)screen;
 105         struct radeon_winsys *ws = sscreen->b.ws;
 106         LLVMTargetRef r600_target;
 107 #if HAVE_LLVM >= 0x0306
 108         const char *triple = "amdgcn--";
 109 #endif
 110         int shader, i;
 111
 112         if (sctx == NULL)
 113                 return NULL;
 114
 115         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 116                 flags |= PIPE_CONTEXT_DEBUG;
 117
 118         sctx->b.b.screen = screen; /* this must be set first */
 119         sctx->b.b.priv = priv;
 120         sctx->b.b.destroy = si_destroy_context;
 121         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 122         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 123         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 124
 125         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 126                 goto fail;
 127
 128         if (sscreen->b.info.drm_major == 3)
 129                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 130
 131         si_init_blit_functions(sctx);
 132         si_init_compute_functions(sctx);
 133         si_init_cp_dma_functions(sctx);
 134         si_init_debug_functions(sctx);
 135
 136         if (sscreen->b.info.has_uvd) {
 137                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 138                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 139         } else {
 140                 sctx->b.b.create_video_codec = vl_create_decoder;
 141                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 142         }
 143
 144         sctx->b.rings.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 145                                              sctx, sscreen->b.trace_bo ?
 146                                                 sscreen->b.trace_bo->cs_buf : NULL);
 147         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 148
 149         /* Border colors. */
 150         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 151                                           sizeof(*sctx->border_color_table));
 152         if (!sctx->border_color_table)
 153                 goto fail;
 154
 155         sctx->border_color_buffer = (struct r600_resource*)
 156                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 157                                    SI_MAX_BORDER_COLORS *
 158                                    sizeof(*sctx->border_color_table));
 159         if (!sctx->border_color_buffer)
 160                 goto fail;
 161
 162         sctx->border_color_map =
 163                 ws->buffer_map(sctx->border_color_buffer->cs_buf,
 164                                NULL, PIPE_TRANSFER_WRITE);
 165         if (!sctx->border_color_map)
 166                 goto fail;
 167
 168         si_init_all_descriptors(sctx);
 169         si_init_state_functions(sctx);
 170         si_init_shader_functions(sctx);
 171
 172         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 173                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 174
 175         sctx->blitter = util_blitter_create(&sctx->b.b);
 176         if (sctx->blitter == NULL)
 177                 goto fail;
 178         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 179
 180         sctx->sample_mask.sample_mask = 0xffff;
 181
 182         /* these must be last */
 183         si_begin_new_cs(sctx);
 184         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 185
 186         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 187          * with a NULL buffer). We need to use a dummy buffer instead. */
 188         if (sctx->b.chip_class == CIK) {
 189                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 190                                                                  PIPE_USAGE_DEFAULT, 16);
 191                 if (!sctx->null_const_buf.buffer)
 192                         goto fail;
 193                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 194
 195                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 196                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 197                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 198                                                               &sctx->null_const_buf);
 199                         }
 200                 }
 201
 202                 /* Clear the NULL constant buffer, because loads should return zeros. */
 203                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 204                                      sctx->null_const_buf.buffer->width0, 0, false);
 205         }
 206
 207         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 208          * this for non-cs shaders.  Using the wrong value here can result in
 209          * GPU lockups, but the maximum value seems to always work.
 210          */
 211         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 212
 213 #if HAVE_LLVM >= 0x0306
 214         /* Initialize LLVM TargetMachine */
 215         r600_target = radeon_llvm_get_r600_target(triple);
 216         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 217                                            r600_get_llvm_processor_name(sscreen->b.family),
 218                                            "+DumpCode,+vgpr-spilling",
 219                                            LLVMCodeGenLevelDefault,
 220                                            LLVMRelocDefault,
 221                                            LLVMCodeModelDefault);
 222 #endif
 223
 224         return &sctx->b.b;
 225 fail:
 226         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 227         si_destroy_context(&sctx->b.b);
 228         return NULL;
 229 }
 230
 231 /*
 232  * pipe_screen
 233  */
 234
 235 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 236 {
 237         struct si_screen *sscreen = (struct si_screen *)pscreen;
 238
 239         switch (param) {
 240         /* Supported features (boolean caps). */
 241         case PIPE_CAP_TWO_SIDED_STENCIL:
 242         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 243         case PIPE_CAP_ANISOTROPIC_FILTER:
 244         case PIPE_CAP_POINT_SPRITE:
 245         case PIPE_CAP_OCCLUSION_QUERY:
 246         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 247         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 248         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 249         case PIPE_CAP_TEXTURE_SWIZZLE:
 250         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 251         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 252         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 253         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 254         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 255         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 256         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 257         case PIPE_CAP_SM3:
 258         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 259         case PIPE_CAP_PRIMITIVE_RESTART:
 260         case PIPE_CAP_CONDITIONAL_RENDER:
 261         case PIPE_CAP_TEXTURE_BARRIER:
 262         case PIPE_CAP_INDEP_BLEND_ENABLE:
 263         case PIPE_CAP_INDEP_BLEND_FUNC:
 264         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 265         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 266         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 267         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 268         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 269         case PIPE_CAP_USER_INDEX_BUFFERS:
 270         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 271         case PIPE_CAP_START_INSTANCE:
 272         case PIPE_CAP_NPOT_TEXTURES:
 273         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 274         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 275         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 276         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 277         case PIPE_CAP_TGSI_INSTANCEID:
 278         case PIPE_CAP_COMPUTE:
 279         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 280         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 281         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 282         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 283         case PIPE_CAP_CUBE_MAP_ARRAY:
 284         case PIPE_CAP_SAMPLE_SHADING:
 285         case PIPE_CAP_DRAW_INDIRECT:
 286         case PIPE_CAP_CLIP_HALFZ:
 287         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 288         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 289         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 290         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 291         case PIPE_CAP_TGSI_TEXCOORD:
 292         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 293         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 294         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 295         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 296         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 297         case PIPE_CAP_TEXTURE_QUERY_LOD:
 298         case PIPE_CAP_TEXTURE_GATHER_SM5:
 299         case PIPE_CAP_TGSI_TXQS:
 300         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 301                 return 1;
 302
 303         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 304                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 305
 306         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 307                 return (sscreen->b.info.drm_major == 2 &&
 308                         sscreen->b.info.drm_minor >= 43) ||
 309                        sscreen->b.info.drm_major == 3;
 310
 311         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 312                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 313                 return sscreen->b.chip_class < CIK ||
 314                        (sscreen->b.info.drm_major == 2 &&
 315                         sscreen->b.info.drm_minor >= 35) ||
 316                        sscreen->b.info.drm_major == 3;
 317
 318         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 319                 return R600_MAP_BUFFER_ALIGNMENT;
 320
 321         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 322         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 323         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 324                 return 4;
 325
 326         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 327                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 328
 329         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 330                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 331
 332         /* Unsupported features. */
 333         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 334         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 335         case PIPE_CAP_USER_VERTEX_BUFFERS:
 336         case PIPE_CAP_FAKE_SW_MSAA:
 337         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 338         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 339         case PIPE_CAP_VERTEXID_NOBASE:
 340                 return 0;
 341
 342         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 343                 return 30;
 344
 345         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 346                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 347
 348         /* Stream output. */
 349         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 350                 return sscreen->b.has_streamout ? 4 : 0;
 351         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 352                 return sscreen->b.has_streamout ? 1 : 0;
 353         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 354         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 355                 return sscreen->b.has_streamout ? 32*4 : 0;
 356
 357         /* Geometry shader output. */
 358         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 359                 return 1024;
 360         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 361                 return 4095;
 362         case PIPE_CAP_MAX_VERTEX_STREAMS:
 363                 return 4;
 364
 365         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 366                 return 2048;
 367
 368         /* Texturing. */
 369         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 370         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 371                 return 15; /* 16384 */
 372         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 373                 /* textures support 8192, but layered rendering supports 2048 */
 374                 return 12;
 375         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 376                 /* textures support 8192, but layered rendering supports 2048 */
 377                 return 2048;
 378
 379         /* Render targets. */
 380         case PIPE_CAP_MAX_RENDER_TARGETS:
 381                 return 8;
 382
 383         case PIPE_CAP_MAX_VIEWPORTS:
 384                 return SI_MAX_VIEWPORTS;
 385
 386         /* Timer queries, present when the clock frequency is non zero. */
 387         case PIPE_CAP_QUERY_TIMESTAMP:
 388         case PIPE_CAP_QUERY_TIME_ELAPSED:
 389                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 390
 391         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 392         case PIPE_CAP_MIN_TEXEL_OFFSET:
 393                 return -32;
 394
 395         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 396         case PIPE_CAP_MAX_TEXEL_OFFSET:
 397                 return 31;
 398
 399         case PIPE_CAP_ENDIANNESS:
 400                 return PIPE_ENDIAN_LITTLE;
 401
 402         case PIPE_CAP_VENDOR_ID:
 403                 return 0x1002;
 404         case PIPE_CAP_DEVICE_ID:
 405                 return sscreen->b.info.pci_id;
 406         case PIPE_CAP_ACCELERATED:
 407                 return 1;
 408         case PIPE_CAP_VIDEO_MEMORY:
 409                 return sscreen->b.info.vram_size >> 20;
 410         case PIPE_CAP_UMA:
 411                 return 0;
 412         }
 413         return 0;
 414 }
 415
 416 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 417 {
 418         switch(shader)
 419         {
 420         case PIPE_SHADER_FRAGMENT:
 421         case PIPE_SHADER_VERTEX:
 422         case PIPE_SHADER_GEOMETRY:
 423                 break;
 424         case PIPE_SHADER_TESS_CTRL:
 425         case PIPE_SHADER_TESS_EVAL:
 426                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 427                 if (HAVE_LLVM < 0x0306 ||
 428                     (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
 429                         return 0;
 430                 break;
 431         case PIPE_SHADER_COMPUTE:
 432                 switch (param) {
 433                 case PIPE_SHADER_CAP_PREFERRED_IR:
 434 #if HAVE_LLVM < 0x0306
 435                         return PIPE_SHADER_IR_LLVM;
 436 #else
 437                         return PIPE_SHADER_IR_NATIVE;
 438 #endif
 439                 case PIPE_SHADER_CAP_DOUBLES:
 440                         return HAVE_LLVM >= 0x0307;
 441
 442                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 443                         uint64_t max_const_buffer_size;
 444                         pscreen->get_compute_param(pscreen,
 445                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 446                                 &max_const_buffer_size);
 447                         return max_const_buffer_size;
 448                 }
 449                 default:
 450                         /* If compute shaders don't require a special value
 451                          * for this cap, we can return the same value we
 452                          * do for other shader types. */
 453                         break;
 454                 }
 455                 break;
 456         default:
 457                 return 0;
 458         }
 459
 460         switch (param) {
 461         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 462         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 463         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 464         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 465                 return 16384;
 466         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 467                 return 32;
 468         case PIPE_SHADER_CAP_MAX_INPUTS:
 469                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 470         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 471                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 472         case PIPE_SHADER_CAP_MAX_TEMPS:
 473                 return 256; /* Max native temporaries. */
 474         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 475                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 476         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 477                 return SI_NUM_USER_CONST_BUFFERS;
 478         case PIPE_SHADER_CAP_MAX_PREDS:
 479                 return 0; /* FIXME */
 480         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 481                 return 1;
 482         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 483                 return 1;
 484         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 485                 /* Indirection of geometry shader input dimension is not
 486                  * handled yet
 487                  */
 488                 return shader != PIPE_SHADER_GEOMETRY;
 489         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 490         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 491         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 492                 return 1;
 493         case PIPE_SHADER_CAP_INTEGERS:
 494                 return 1;
 495         case PIPE_SHADER_CAP_SUBROUTINES:
 496                 return 0;
 497         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 498         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 499                 return 16;
 500         case PIPE_SHADER_CAP_PREFERRED_IR:
 501                 return PIPE_SHADER_IR_TGSI;
 502         case PIPE_SHADER_CAP_DOUBLES:
 503                 return HAVE_LLVM >= 0x0307;
 504         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 505         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 506                 return 0;
 507         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 508         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 509                 return 1;
 510         }
 511         return 0;
 512 }
 513
 514 static void si_destroy_screen(struct pipe_screen* pscreen)
 515 {
 516         struct si_screen *sscreen = (struct si_screen *)pscreen;
 517
 518         if (sscreen == NULL)
 519                 return;
 520
 521         if (!sscreen->b.ws->unref(sscreen->b.ws))
 522                 return;
 523
 524         r600_destroy_common_screen(&sscreen->b);
 525 }
 526
 527 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 528
 529 /* Initialize pipe config. This is especially important for GPUs
 530  * with 16 pipes and more where it's initialized incorrectly by
 531  * the TILING_CONFIG ioctl. */
 532 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 533 {
 534         unsigned mode2d;
 535
 536         /* This is okay, because there can be no 2D tiling without
 537          * the tile mode array, so we won't need the pipe config.
 538          * Return "success".
 539          */
 540         if (!sscreen->b.info.si_tile_mode_array_valid)
 541                 return true;
 542
 543         /* The same index is used for the 2D mode on CIK too. */
 544         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 545
 546         switch (G_009910_PIPE_CONFIG(mode2d)) {
 547         case V_02803C_ADDR_SURF_P2:
 548                 sscreen->b.tiling_info.num_channels = 2;
 549                 break;
 550         case V_02803C_X_ADDR_SURF_P4_8X16:
 551         case V_02803C_X_ADDR_SURF_P4_16X16:
 552         case V_02803C_X_ADDR_SURF_P4_16X32:
 553         case V_02803C_X_ADDR_SURF_P4_32X32:
 554                 sscreen->b.tiling_info.num_channels = 4;
 555                 break;
 556         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 557         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 558         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 559         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 560         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 561         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 562         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 563                 sscreen->b.tiling_info.num_channels = 8;
 564                 break;
 565         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 566         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 567                 sscreen->b.tiling_info.num_channels = 16;
 568                 break;
 569         default:
 570                 assert(0);
 571                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 572                         G_009910_PIPE_CONFIG(mode2d));
 573                 return false;
 574         }
 575         return true;
 576 }
 577
 578 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 579 {
 580         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 581
 582         if (sscreen == NULL) {
 583                 return NULL;
 584         }
 585
 586         /* Set functions first. */
 587         sscreen->b.b.context_create = si_create_context;
 588         sscreen->b.b.destroy = si_destroy_screen;
 589         sscreen->b.b.get_param = si_get_param;
 590         sscreen->b.b.get_shader_param = si_get_shader_param;
 591         sscreen->b.b.is_format_supported = si_is_format_supported;
 592         sscreen->b.b.resource_create = r600_resource_create_common;
 593
 594         if (!r600_common_screen_init(&sscreen->b, ws) ||
 595             !si_initialize_pipe_config(sscreen)) {
 596                 FREE(sscreen);
 597                 return NULL;
 598         }
 599
 600         sscreen->b.has_cp_dma = true;
 601         sscreen->b.has_streamout = true;
 602
 603         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 604                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 605
 606         /* Create the auxiliary context. This must be done last. */
 607         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 608
 609         return &sscreen->b.b;
 610 }