2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_format.h"
34 #include "util/u_transfer.h"
35 #include "util/u_surface.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_simple_shaders.h"
40 #include "util/u_upload_mgr.h"
41 #include "vl/vl_decoder.h"
42 #include "vl/vl_video_buffer.h"
43 #include "os/os_time.h"
44 #include "pipebuffer/pb_buffer.h"
46 #include "radeon/radeon_uvd.h"
49 #include "si_resource.h"
52 #include "../radeon/r600_cs.h"
57 void si_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
60 struct si_context
*sctx
= (struct si_context
*)ctx
;
61 struct pipe_query
*render_cond
= NULL
;
62 boolean render_cond_cond
= FALSE
;
63 unsigned render_cond_mode
= 0;
66 *fence
= sctx
->b
.ws
->cs_create_fence(sctx
->b
.rings
.gfx
.cs
);
69 /* Disable render condition. */
70 if (sctx
->b
.current_render_cond
) {
71 render_cond
= sctx
->b
.current_render_cond
;
72 render_cond_cond
= sctx
->b
.current_render_cond_cond
;
73 render_cond_mode
= sctx
->b
.current_render_cond_mode
;
74 ctx
->render_condition(ctx
, NULL
, FALSE
, 0);
77 si_context_flush(sctx
, flags
);
79 /* Re-enable render condition. */
81 ctx
->render_condition(ctx
, render_cond
, render_cond_cond
, render_cond_mode
);
85 static void si_flush_from_st(struct pipe_context
*ctx
,
86 struct pipe_fence_handle
**fence
,
90 flags
& PIPE_FLUSH_END_OF_FRAME
? RADEON_FLUSH_END_OF_FRAME
: 0);
93 static void si_flush_from_winsys(void *ctx
, unsigned flags
)
95 si_flush((struct pipe_context
*)ctx
, NULL
, flags
);
98 static void si_destroy_context(struct pipe_context
*context
)
100 struct si_context
*sctx
= (struct si_context
*)context
;
102 si_release_all_descriptors(sctx
);
104 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
105 r600_resource_reference(&sctx
->border_color_table
, NULL
);
107 if (sctx
->dummy_pixel_shader
) {
108 sctx
->b
.b
.delete_fs_state(&sctx
->b
.b
, sctx
->dummy_pixel_shader
);
110 for (int i
= 0; i
< 8; i
++) {
111 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush_depth_stencil
[i
]);
112 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush_depth
[i
]);
113 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush_stencil
[i
]);
115 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush_inplace
);
116 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
117 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
118 util_unreference_framebuffer_state(&sctx
->framebuffer
);
120 util_blitter_destroy(sctx
->blitter
);
122 r600_common_context_cleanup(&sctx
->b
);
126 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
, void *priv
)
128 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
129 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
135 sctx
->b
.b
.screen
= screen
; /* this must be set first */
136 sctx
->b
.b
.priv
= priv
;
137 sctx
->b
.b
.destroy
= si_destroy_context
;
138 sctx
->b
.b
.flush
= si_flush_from_st
;
139 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
141 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
))
144 si_init_blit_functions(sctx
);
145 si_init_compute_functions(sctx
);
147 if (sscreen
->b
.info
.has_uvd
) {
148 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
149 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
151 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
152 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
155 sctx
->b
.rings
.gfx
.cs
= sctx
->b
.ws
->cs_create(sctx
->b
.ws
, RING_GFX
, NULL
);
156 sctx
->b
.rings
.gfx
.flush
= si_flush_from_winsys
;
158 si_init_all_descriptors(sctx
);
160 /* Initialize cache_flush. */
161 sctx
->cache_flush
= si_atom_cache_flush
;
162 sctx
->atoms
.cache_flush
= &sctx
->cache_flush
;
164 sctx
->atoms
.streamout_begin
= &sctx
->b
.streamout
.begin_atom
;
166 switch (sctx
->b
.chip_class
) {
169 si_init_state_functions(sctx
);
170 si_init_config(sctx
);
173 R600_ERR("Unsupported chip class %d.\n", sctx
->b
.chip_class
);
177 sctx
->b
.ws
->cs_set_flush_callback(sctx
->b
.rings
.gfx
.cs
, si_flush_from_winsys
, sctx
);
179 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
180 if (sctx
->blitter
== NULL
)
183 sctx
->dummy_pixel_shader
=
184 util_make_fragment_cloneinput_shader(&sctx
->b
.b
, 0,
185 TGSI_SEMANTIC_GENERIC
,
186 TGSI_INTERPOLATE_CONSTANT
);
187 sctx
->b
.b
.bind_fs_state(&sctx
->b
.b
, sctx
->dummy_pixel_shader
);
189 /* these must be last */
190 si_begin_new_cs(sctx
);
191 r600_query_init_backend_mask(&sctx
->b
); /* this emits commands and must be last */
193 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
194 * with a NULL buffer). We need to use a dummy buffer instead. */
195 if (sctx
->b
.chip_class
== CIK
) {
196 sctx
->null_const_buf
.buffer
= pipe_buffer_create(screen
, PIPE_BIND_CONSTANT_BUFFER
,
197 PIPE_USAGE_STATIC
, 16);
198 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
200 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
201 for (i
= 0; i
< NUM_CONST_BUFFERS
; i
++) {
202 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
203 &sctx
->null_const_buf
);
207 /* Clear the NULL constant buffer, because loads should return zeros. */
208 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
209 sctx
->null_const_buf
.buffer
->width0
, 0);
214 si_destroy_context(&sctx
->b
.b
);
222 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
224 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
227 /* Supported features (boolean caps). */
228 case PIPE_CAP_TWO_SIDED_STENCIL
:
229 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
230 case PIPE_CAP_ANISOTROPIC_FILTER
:
231 case PIPE_CAP_POINT_SPRITE
:
232 case PIPE_CAP_OCCLUSION_QUERY
:
233 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
234 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
235 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
236 case PIPE_CAP_TEXTURE_SWIZZLE
:
237 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
238 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
239 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
240 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
241 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
242 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
244 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
245 case PIPE_CAP_PRIMITIVE_RESTART
:
246 case PIPE_CAP_CONDITIONAL_RENDER
:
247 case PIPE_CAP_TEXTURE_BARRIER
:
248 case PIPE_CAP_INDEP_BLEND_ENABLE
:
249 case PIPE_CAP_INDEP_BLEND_FUNC
:
250 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
251 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
252 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
253 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
254 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
255 case PIPE_CAP_USER_INDEX_BUFFERS
:
256 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
257 case PIPE_CAP_START_INSTANCE
:
258 case PIPE_CAP_NPOT_TEXTURES
:
259 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
260 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
261 case PIPE_CAP_TGSI_INSTANCEID
:
262 case PIPE_CAP_COMPUTE
:
263 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
264 case PIPE_CAP_TGSI_VS_LAYER
:
265 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
268 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
269 /* 2D tiling on CIK is supported since DRM 2.35.0 */
270 return HAVE_LLVM
>= 0x0304 && (sscreen
->b
.chip_class
< CIK
||
271 sscreen
->b
.info
.drm_minor
>= 35);
273 case PIPE_CAP_TGSI_TEXCOORD
:
276 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
279 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
282 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
285 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
287 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
288 return MIN2(sscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
290 /* Unsupported features. */
291 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
292 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
293 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
294 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
295 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
296 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
297 case PIPE_CAP_USER_VERTEX_BUFFERS
:
298 case PIPE_CAP_CUBE_MAP_ARRAY
:
301 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
302 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
305 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
306 return sscreen
->b
.has_streamout
? 4 : 0;
307 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
308 return sscreen
->b
.has_streamout
? 1 : 0;
309 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
310 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
311 return sscreen
->b
.has_streamout
? 32*4 : 0;
314 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
315 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
316 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
318 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
320 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
323 /* Render targets. */
324 case PIPE_CAP_MAX_RENDER_TARGETS
:
327 case PIPE_CAP_MAX_VIEWPORTS
:
330 /* Timer queries, present when the clock frequency is non zero. */
331 case PIPE_CAP_QUERY_TIMESTAMP
:
332 case PIPE_CAP_QUERY_TIME_ELAPSED
:
333 return sscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
335 case PIPE_CAP_MIN_TEXEL_OFFSET
:
338 case PIPE_CAP_MAX_TEXEL_OFFSET
:
340 case PIPE_CAP_ENDIANNESS
:
341 return PIPE_ENDIAN_LITTLE
;
346 static int si_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
350 case PIPE_SHADER_FRAGMENT
:
351 case PIPE_SHADER_VERTEX
:
353 case PIPE_SHADER_GEOMETRY
:
354 /* TODO: support and enable geometry programs */
356 case PIPE_SHADER_COMPUTE
:
358 case PIPE_SHADER_CAP_PREFERRED_IR
:
359 return PIPE_SHADER_IR_LLVM
;
364 /* TODO: support tessellation */
369 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
370 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
371 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
372 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
374 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
376 case PIPE_SHADER_CAP_MAX_INPUTS
:
378 case PIPE_SHADER_CAP_MAX_TEMPS
:
379 return 256; /* Max native temporaries. */
380 case PIPE_SHADER_CAP_MAX_ADDRS
:
381 /* FIXME Isn't this equal to TEMPS? */
382 return 1; /* Max native address registers */
383 case PIPE_SHADER_CAP_MAX_CONSTS
:
384 return 4096; /* actually only memory limits this */
385 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
386 return NUM_PIPE_CONST_BUFFERS
;
387 case PIPE_SHADER_CAP_MAX_PREDS
:
388 return 0; /* FIXME */
389 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
391 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
393 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
394 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
395 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
396 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
398 case PIPE_SHADER_CAP_INTEGERS
:
400 case PIPE_SHADER_CAP_SUBROUTINES
:
402 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
403 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
405 case PIPE_SHADER_CAP_PREFERRED_IR
:
406 return PIPE_SHADER_IR_TGSI
;
411 static void si_destroy_screen(struct pipe_screen
* pscreen
)
413 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
418 if (!radeon_winsys_unref(sscreen
->b
.ws
))
421 r600_common_screen_cleanup(&sscreen
->b
);
424 if (sscreen
->b
.trace_bo
) {
425 sscreen
->ws
->buffer_unmap(sscreen
->b
.trace_bo
->cs_buf
);
426 pipe_resource_reference((struct pipe_resource
**)&sscreen
->b
.trace_bo
, NULL
);
430 sscreen
->b
.ws
->destroy(sscreen
->b
.ws
);
434 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
436 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
437 if (sscreen
== NULL
) {
441 /* Set functions first. */
442 sscreen
->b
.b
.context_create
= si_create_context
;
443 sscreen
->b
.b
.destroy
= si_destroy_screen
;
444 sscreen
->b
.b
.get_param
= si_get_param
;
445 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
446 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
448 if (!r600_common_screen_init(&sscreen
->b
, ws
)) {
453 sscreen
->b
.has_cp_dma
= true;
454 sscreen
->b
.has_streamout
= HAVE_LLVM
>= 0x0304;
456 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE
))
457 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
460 sscreen
->b
.cs_count
= 0;
461 if (sscreen
->info
.drm_minor
>= 28) {
462 sscreen
->b
.trace_bo
= (struct r600_resource
*)pipe_buffer_create(&sscreen
->screen
,
466 if (sscreen
->b
.trace_bo
) {
467 sscreen
->b
.trace_ptr
= sscreen
->ws
->buffer_map(sscreen
->b
.trace_bo
->cs_buf
, NULL
,
468 PIPE_TRANSFER_UNSYNCHRONIZED
);
473 /* Create the auxiliary context. This must be done last. */
474 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
);
476 return &sscreen
->b
.b
;