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radeonsi: remove useless #includes
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "radeon/radeon_uvd.h"
33 #include "util/disk_cache.h"
34 #include "util/u_log.h"
35 #include "util/u_memory.h"
36 #include "util/u_suballoc.h"
37 #include "util/u_tests.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/xmlconfig.h"
40 #include "vl/vl_decoder.h"
41 #include "driver_ddebug/dd_util.h"
42
43 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
44 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
45 #include <xf86drm.h>
46
47 static struct pipe_context *si_create_context(struct pipe_screen *screen,
48 unsigned flags);
49
50 static const struct debug_named_value debug_options[] = {
51 /* Shader logging options: */
52 { "vs", DBG(VS), "Print vertex shaders" },
53 { "ps", DBG(PS), "Print pixel shaders" },
54 { "gs", DBG(GS), "Print geometry shaders" },
55 { "tcs", DBG(TCS), "Print tessellation control shaders" },
56 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
57 { "cs", DBG(CS), "Print compute shaders" },
58 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
59 { "nonir", DBG(NO_NIR), "Don't print NIR when printing shaders"},
60 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
61 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
62
63 /* Shader compiler options the shader cache should be aware of: */
64 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
66 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
67 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
68 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
69 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
70 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
71 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
72
73 /* Shader compiler options (with no effect on the shader cache): */
74 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
75 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
76 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
77
78 /* Information logging options: */
79 { "info", DBG(INFO), "Print driver information" },
80 { "tex", DBG(TEX), "Print texture info" },
81 { "compute", DBG(COMPUTE), "Print compute info" },
82 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
83
84 /* Driver options: */
85 { "forcedma", DBG(FORCE_SDMA), "Use SDMA for all operations when possible." },
86 { "nodma", DBG(NO_SDMA), "Disable SDMA" },
87 { "nodmaclear", DBG(NO_SDMA_CLEARS), "Disable SDMA clears" },
88 { "nodmacopyimage", DBG(NO_SDMA_COPY_IMAGE), "Disable SDMA image copies" },
89 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
90 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
91 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
92 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
93
94 /* 3D engine options: */
95 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
96 { "nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline." },
97 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
98 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
99 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
100 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
101 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
102 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
103 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
104 { "dpbb", DBG(DPBB), "Enable DPBB." },
105 { "dfsm", DBG(DFSM), "Enable DFSM." },
106 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
107 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
108 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
109 { "notiling", DBG(NO_TILING), "Disable tiling" },
110 { "nodcc", DBG(NO_DCC), "Disable DCC." },
111 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
112 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
113 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
114 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
115
116 /* Tests: */
117 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
118 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
119 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
120 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
121 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
122 { "testgds", DBG(TEST_GDS), "Test GDS." },
123 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
124 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
125
126 DEBUG_NAMED_VALUE_END /* must be last */
127 };
128
129 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
130 {
131 /* Only create the less-optimizing version of the compiler on APUs
132 * predating Ryzen (Raven). */
133 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
134 sscreen->info.chip_class <= GFX8;
135
136 enum ac_target_machine_options tm_options =
137 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
138 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
139 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
140 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
141 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
142 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
143 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
144
145 ac_init_llvm_once();
146 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
147 compiler->passes = ac_create_llvm_passes(compiler->tm);
148
149 if (compiler->tm_wave32)
150 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
151 if (compiler->low_opt_tm)
152 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
153 }
154
155 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
156 {
157 ac_destroy_llvm_compiler(compiler);
158 }
159
160 /*
161 * pipe_context
162 */
163 static void si_destroy_context(struct pipe_context *context)
164 {
165 struct si_context *sctx = (struct si_context *)context;
166 int i;
167
168 util_queue_finish(&sctx->screen->shader_compiler_queue);
169 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
170
171 /* Unreference the framebuffer normally to disable related logic
172 * properly.
173 */
174 struct pipe_framebuffer_state fb = {};
175 if (context->set_framebuffer_state)
176 context->set_framebuffer_state(context, &fb);
177
178 si_release_all_descriptors(sctx);
179
180 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
181 gfx10_destroy_query(sctx);
182
183 pipe_resource_reference(&sctx->esgs_ring, NULL);
184 pipe_resource_reference(&sctx->gsvs_ring, NULL);
185 pipe_resource_reference(&sctx->tess_rings, NULL);
186 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
187 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
188 si_resource_reference(&sctx->border_color_buffer, NULL);
189 free(sctx->border_color_table);
190 si_resource_reference(&sctx->scratch_buffer, NULL);
191 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
192 si_resource_reference(&sctx->wait_mem_scratch, NULL);
193
194 si_pm4_free_state(sctx, sctx->init_config, ~0);
195 if (sctx->init_config_gs_rings)
196 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
197 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
198 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
199
200 if (sctx->fixed_func_tcs_shader.cso)
201 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
202 if (sctx->custom_dsa_flush)
203 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
204 if (sctx->custom_blend_resolve)
205 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
206 if (sctx->custom_blend_fmask_decompress)
207 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
208 if (sctx->custom_blend_eliminate_fastclear)
209 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
210 if (sctx->custom_blend_dcc_decompress)
211 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
212 if (sctx->vs_blit_pos)
213 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
214 if (sctx->vs_blit_pos_layered)
215 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
216 if (sctx->vs_blit_color)
217 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
218 if (sctx->vs_blit_color_layered)
219 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
220 if (sctx->vs_blit_texcoord)
221 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
222 if (sctx->cs_clear_buffer)
223 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
224 if (sctx->cs_copy_buffer)
225 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
226 if (sctx->cs_copy_image)
227 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
228 if (sctx->cs_copy_image_1d_array)
229 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
230 if (sctx->cs_clear_render_target)
231 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
232 if (sctx->cs_clear_render_target_1d_array)
233 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
234 if (sctx->cs_clear_12bytes_buffer)
235 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer);
236 if (sctx->cs_dcc_retile)
237 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
238
239 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
240 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
241 if (sctx->cs_fmask_expand[i][j]) {
242 sctx->b.delete_compute_state(&sctx->b,
243 sctx->cs_fmask_expand[i][j]);
244 }
245 }
246 }
247
248 if (sctx->blitter)
249 util_blitter_destroy(sctx->blitter);
250
251 /* Release DCC stats. */
252 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
253 assert(!sctx->dcc_stats[i].query_active);
254
255 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
256 if (sctx->dcc_stats[i].ps_stats[j])
257 sctx->b.destroy_query(&sctx->b,
258 sctx->dcc_stats[i].ps_stats[j]);
259
260 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
261 }
262
263 if (sctx->query_result_shader)
264 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
265 if (sctx->sh_query_result_shader)
266 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
267
268 if (sctx->gfx_cs)
269 sctx->ws->cs_destroy(sctx->gfx_cs);
270 if (sctx->sdma_cs)
271 sctx->ws->cs_destroy(sctx->sdma_cs);
272 if (sctx->ctx)
273 sctx->ws->ctx_destroy(sctx->ctx);
274
275 if (sctx->b.stream_uploader)
276 u_upload_destroy(sctx->b.stream_uploader);
277 if (sctx->b.const_uploader)
278 u_upload_destroy(sctx->b.const_uploader);
279 if (sctx->cached_gtt_allocator)
280 u_upload_destroy(sctx->cached_gtt_allocator);
281
282 slab_destroy_child(&sctx->pool_transfers);
283 slab_destroy_child(&sctx->pool_transfers_unsync);
284
285 if (sctx->allocator_zeroed_memory)
286 u_suballocator_destroy(sctx->allocator_zeroed_memory);
287
288 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
289 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
290 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
291 si_resource_reference(&sctx->eop_bug_scratch, NULL);
292 si_resource_reference(&sctx->index_ring, NULL);
293 si_resource_reference(&sctx->barrier_buf, NULL);
294 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
295 pb_reference(&sctx->gds, NULL);
296 pb_reference(&sctx->gds_oa, NULL);
297
298 si_destroy_compiler(&sctx->compiler);
299
300 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
301
302 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
303 _mesa_hash_table_destroy(sctx->img_handles, NULL);
304
305 util_dynarray_fini(&sctx->resident_tex_handles);
306 util_dynarray_fini(&sctx->resident_img_handles);
307 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
308 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
309 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
310 si_unref_sdma_uploads(sctx);
311 free(sctx->sdma_uploads);
312 FREE(sctx);
313 }
314
315 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
316 {
317 struct si_context *sctx = (struct si_context *)ctx;
318 struct si_screen *sscreen = sctx->screen;
319 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx);
320
321 if (status != PIPE_NO_RESET) {
322 /* Call the state tracker to set a no-op API dispatch. */
323 if (sctx->device_reset_callback.reset) {
324 sctx->device_reset_callback.reset(sctx->device_reset_callback.data,
325 status);
326 }
327
328 /* Re-create the auxiliary context, because it won't submit
329 * any new IBs due to a GPU reset.
330 */
331 simple_mtx_lock(&sscreen->aux_context_lock);
332
333 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
334 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
335 sscreen->aux_context->destroy(sscreen->aux_context);
336
337 sscreen->aux_context = si_create_context(&sscreen->b,
338 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
339 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
340 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
341 simple_mtx_unlock(&sscreen->aux_context_lock);
342 }
343 return status;
344 }
345
346 static void si_set_device_reset_callback(struct pipe_context *ctx,
347 const struct pipe_device_reset_callback *cb)
348 {
349 struct si_context *sctx = (struct si_context *)ctx;
350
351 if (cb)
352 sctx->device_reset_callback = *cb;
353 else
354 memset(&sctx->device_reset_callback, 0,
355 sizeof(sctx->device_reset_callback));
356 }
357
358 /* Apitrace profiling:
359 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
360 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
361 * and remember its number.
362 * 3) In Mesa, enable queries and performance counters around that draw
363 * call and print the results.
364 * 4) glretrace --benchmark --markers ..
365 */
366 static void si_emit_string_marker(struct pipe_context *ctx,
367 const char *string, int len)
368 {
369 struct si_context *sctx = (struct si_context *)ctx;
370
371 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
372
373 if (sctx->log)
374 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
375 }
376
377 static void si_set_debug_callback(struct pipe_context *ctx,
378 const struct pipe_debug_callback *cb)
379 {
380 struct si_context *sctx = (struct si_context *)ctx;
381 struct si_screen *screen = sctx->screen;
382
383 util_queue_finish(&screen->shader_compiler_queue);
384 util_queue_finish(&screen->shader_compiler_queue_low_priority);
385
386 if (cb)
387 sctx->debug = *cb;
388 else
389 memset(&sctx->debug, 0, sizeof(sctx->debug));
390 }
391
392 static void si_set_log_context(struct pipe_context *ctx,
393 struct u_log_context *log)
394 {
395 struct si_context *sctx = (struct si_context *)ctx;
396 sctx->log = log;
397
398 if (log)
399 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
400 }
401
402 static void si_set_context_param(struct pipe_context *ctx,
403 enum pipe_context_param param,
404 unsigned value)
405 {
406 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
407
408 switch (param) {
409 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
410 ws->pin_threads_to_L3_cache(ws, value);
411 break;
412 default:;
413 }
414 }
415
416 static struct pipe_context *si_create_context(struct pipe_screen *screen,
417 unsigned flags)
418 {
419 struct si_screen* sscreen = (struct si_screen *)screen;
420
421 /* Don't create a context if it's not compute-only and hw is compute-only. */
422 if (!sscreen->info.has_graphics &&
423 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
424 return NULL;
425
426 struct si_context *sctx = CALLOC_STRUCT(si_context);
427 struct radeon_winsys *ws = sscreen->ws;
428 int shader, i;
429 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
430
431 if (!sctx)
432 return NULL;
433
434 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
435 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
436
437 if (flags & PIPE_CONTEXT_DEBUG)
438 sscreen->record_llvm_ir = true; /* racy but not critical */
439
440 sctx->b.screen = screen; /* this must be set first */
441 sctx->b.priv = NULL;
442 sctx->b.destroy = si_destroy_context;
443 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
444 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
445
446 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
447 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
448
449 sctx->ws = sscreen->ws;
450 sctx->family = sscreen->info.family;
451 sctx->chip_class = sscreen->info.chip_class;
452
453 if (sctx->chip_class == GFX7 ||
454 sctx->chip_class == GFX8 ||
455 sctx->chip_class == GFX9) {
456 sctx->eop_bug_scratch = si_resource(
457 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
458 16 * sscreen->info.num_render_backends));
459 if (!sctx->eop_bug_scratch)
460 goto fail;
461 }
462
463 /* Initialize context allocators. */
464 sctx->allocator_zeroed_memory =
465 u_suballocator_create(&sctx->b, 128 * 1024,
466 0, PIPE_USAGE_DEFAULT,
467 SI_RESOURCE_FLAG_UNMAPPABLE |
468 SI_RESOURCE_FLAG_CLEAR, false);
469 if (!sctx->allocator_zeroed_memory)
470 goto fail;
471
472 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
473 0, PIPE_USAGE_STREAM,
474 SI_RESOURCE_FLAG_READ_ONLY);
475 if (!sctx->b.stream_uploader)
476 goto fail;
477
478 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
479 0, PIPE_USAGE_STAGING, 0);
480 if (!sctx->cached_gtt_allocator)
481 goto fail;
482
483 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
484 if (!sctx->ctx)
485 goto fail;
486
487 if (sscreen->info.num_rings[RING_DMA] &&
488 !(sscreen->debug_flags & DBG(NO_SDMA)) &&
489 /* SDMA causes corruption on RX 580:
490 * https://gitlab.freedesktop.org/mesa/mesa/issues/1399
491 * https://gitlab.freedesktop.org/mesa/mesa/issues/1889
492 */
493 (sctx->chip_class != GFX8 || sscreen->debug_flags & DBG(FORCE_SDMA)) &&
494 /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
495 * https://bugs.freedesktop.org/show_bug.cgi?id=111481
496 * https://gitlab.freedesktop.org/mesa/mesa/issues/1907
497 */
498 (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_SDMA))) {
499 sctx->sdma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
500 (void*)si_flush_dma_cs,
501 sctx, stop_exec_on_failure);
502 }
503
504 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->sdma_cs;
505 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
506 0, PIPE_USAGE_DEFAULT,
507 SI_RESOURCE_FLAG_32BIT |
508 (use_sdma_upload ?
509 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
510 if (!sctx->b.const_uploader)
511 goto fail;
512
513 if (use_sdma_upload)
514 u_upload_enable_flush_explicit(sctx->b.const_uploader);
515
516 sctx->gfx_cs = ws->cs_create(sctx->ctx,
517 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
518 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
519
520 /* Border colors. */
521 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
522 sizeof(*sctx->border_color_table));
523 if (!sctx->border_color_table)
524 goto fail;
525
526 sctx->border_color_buffer = si_resource(
527 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
528 SI_MAX_BORDER_COLORS *
529 sizeof(*sctx->border_color_table)));
530 if (!sctx->border_color_buffer)
531 goto fail;
532
533 sctx->border_color_map =
534 ws->buffer_map(sctx->border_color_buffer->buf,
535 NULL, PIPE_TRANSFER_WRITE);
536 if (!sctx->border_color_map)
537 goto fail;
538
539 sctx->ngg = sscreen->use_ngg;
540
541 /* Initialize context functions used by graphics and compute. */
542 if (sctx->chip_class >= GFX10)
543 sctx->emit_cache_flush = gfx10_emit_cache_flush;
544 else
545 sctx->emit_cache_flush = si_emit_cache_flush;
546
547 sctx->b.emit_string_marker = si_emit_string_marker;
548 sctx->b.set_debug_callback = si_set_debug_callback;
549 sctx->b.set_log_context = si_set_log_context;
550 sctx->b.set_context_param = si_set_context_param;
551 sctx->b.get_device_reset_status = si_get_reset_status;
552 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
553
554 si_init_all_descriptors(sctx);
555 si_init_buffer_functions(sctx);
556 si_init_clear_functions(sctx);
557 si_init_blit_functions(sctx);
558 si_init_compute_functions(sctx);
559 si_init_compute_blit_functions(sctx);
560 si_init_debug_functions(sctx);
561 si_init_fence_functions(sctx);
562 si_init_query_functions(sctx);
563 si_init_state_compute_functions(sctx);
564 si_init_context_texture_functions(sctx);
565
566 /* Initialize graphics-only context functions. */
567 if (sctx->has_graphics) {
568 if (sctx->chip_class >= GFX10)
569 gfx10_init_query(sctx);
570 si_init_msaa_functions(sctx);
571 si_init_shader_functions(sctx);
572 si_init_state_functions(sctx);
573 si_init_streamout_functions(sctx);
574 si_init_viewport_functions(sctx);
575
576 sctx->blitter = util_blitter_create(&sctx->b);
577 if (sctx->blitter == NULL)
578 goto fail;
579 sctx->blitter->skip_viewport_restore = true;
580
581 /* Some states are expected to be always non-NULL. */
582 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
583 sctx->queued.named.blend = sctx->noop_blend;
584
585 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
586 sctx->queued.named.dsa = sctx->noop_dsa;
587
588 sctx->discard_rasterizer_state =
589 util_blitter_get_discard_rasterizer_state(sctx->blitter);
590 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
591
592 si_init_draw_functions(sctx);
593
594 /* If aux_context == NULL, we are initializing aux_context right now. */
595 bool is_aux_context = !sscreen->aux_context;
596 si_initialize_prim_discard_tunables(sscreen, is_aux_context,
597 &sctx->prim_discard_vertex_count_threshold,
598 &sctx->index_ring_size_per_ib);
599 }
600
601 /* Initialize SDMA functions. */
602 if (sctx->chip_class >= GFX7)
603 cik_init_sdma_functions(sctx);
604 else
605 sctx->dma_copy = si_resource_copy_region;
606
607 if (sscreen->debug_flags & DBG(FORCE_SDMA))
608 sctx->b.resource_copy_region = sctx->dma_copy;
609
610 sctx->sample_mask = 0xffff;
611
612 /* Initialize multimedia functions. */
613 if (sscreen->info.has_hw_decode) {
614 sctx->b.create_video_codec = si_uvd_create_decoder;
615 sctx->b.create_video_buffer = si_video_buffer_create;
616 } else {
617 sctx->b.create_video_codec = vl_create_decoder;
618 sctx->b.create_video_buffer = vl_video_buffer_create;
619 }
620
621 if (sctx->chip_class >= GFX9) {
622 sctx->wait_mem_scratch = si_resource(
623 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
624 if (!sctx->wait_mem_scratch)
625 goto fail;
626
627 /* Initialize the memory. */
628 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
629 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
630 }
631
632 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
633 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
634 if (sctx->chip_class == GFX7) {
635 sctx->null_const_buf.buffer =
636 pipe_aligned_buffer_create(screen,
637 SI_RESOURCE_FLAG_32BIT,
638 PIPE_USAGE_DEFAULT, 16,
639 sctx->screen->info.tcc_cache_line_size);
640 if (!sctx->null_const_buf.buffer)
641 goto fail;
642 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
643
644 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
645 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
646 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
647 sctx->b.set_constant_buffer(&sctx->b, shader, i,
648 &sctx->null_const_buf);
649 }
650 }
651
652 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
653 &sctx->null_const_buf);
654 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
655 &sctx->null_const_buf);
656 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
657 &sctx->null_const_buf);
658 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
659 &sctx->null_const_buf);
660 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
661 &sctx->null_const_buf);
662 }
663
664 uint64_t max_threads_per_block;
665 screen->get_compute_param(screen, PIPE_SHADER_IR_NIR,
666 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
667 &max_threads_per_block);
668
669 /* The maximum number of scratch waves. Scratch space isn't divided
670 * evenly between CUs. The number is only a function of the number of CUs.
671 * We can decrease the constant to decrease the scratch buffer size.
672 *
673 * sctx->scratch_waves must be >= the maximum posible size of
674 * 1 threadgroup, so that the hw doesn't hang from being unable
675 * to start any.
676 *
677 * The recommended value is 4 per CU at most. Higher numbers don't
678 * bring much benefit, but they still occupy chip resources (think
679 * async compute). I've seen ~2% performance difference between 4 and 32.
680 */
681 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
682 max_threads_per_block / 64);
683
684 /* Bindless handles. */
685 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
686 _mesa_key_pointer_equal);
687 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
688 _mesa_key_pointer_equal);
689
690 util_dynarray_init(&sctx->resident_tex_handles, NULL);
691 util_dynarray_init(&sctx->resident_img_handles, NULL);
692 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
693 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
694 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
695
696 sctx->sample_pos_buffer =
697 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
698 sizeof(sctx->sample_positions));
699 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
700 sizeof(sctx->sample_positions), &sctx->sample_positions);
701
702 /* this must be last */
703 si_begin_new_gfx_cs(sctx);
704
705 if (sctx->chip_class == GFX7) {
706 /* Clear the NULL constant buffer, because loads should return zeros.
707 * Note that this forces CP DMA to be used, because clover deadlocks
708 * for some reason when the compute codepath is used.
709 */
710 uint32_t clear_value = 0;
711 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
712 sctx->null_const_buf.buffer->width0,
713 &clear_value, 4, SI_COHERENCY_SHADER, true);
714 }
715 return &sctx->b;
716 fail:
717 fprintf(stderr, "radeonsi: Failed to create a context.\n");
718 si_destroy_context(&sctx->b);
719 return NULL;
720 }
721
722 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
723 void *priv, unsigned flags)
724 {
725 struct si_screen *sscreen = (struct si_screen *)screen;
726 struct pipe_context *ctx;
727
728 if (sscreen->debug_flags & DBG(CHECK_VM))
729 flags |= PIPE_CONTEXT_DEBUG;
730
731 ctx = si_create_context(screen, flags);
732
733 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
734 return ctx;
735
736 /* Clover (compute-only) is unsupported. */
737 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
738 return ctx;
739
740 /* When shaders are logged to stderr, asynchronous compilation is
741 * disabled too. */
742 if (sscreen->debug_flags & DBG_ALL_SHADERS)
743 return ctx;
744
745 /* Use asynchronous flushes only on amdgpu, since the radeon
746 * implementation for fence_server_sync is incomplete. */
747 return threaded_context_create(ctx, &sscreen->pool_transfers,
748 si_replace_buffer_storage,
749 sscreen->info.is_amdgpu ? si_create_fence : NULL,
750 &((struct si_context*)ctx)->tc);
751 }
752
753 /*
754 * pipe_screen
755 */
756 static void si_destroy_screen(struct pipe_screen* pscreen)
757 {
758 struct si_screen *sscreen = (struct si_screen *)pscreen;
759 struct si_shader_part *parts[] = {
760 sscreen->vs_prologs,
761 sscreen->tcs_epilogs,
762 sscreen->gs_prologs,
763 sscreen->ps_prologs,
764 sscreen->ps_epilogs
765 };
766 unsigned i;
767
768 if (!sscreen->ws->unref(sscreen->ws))
769 return;
770
771 simple_mtx_destroy(&sscreen->aux_context_lock);
772
773 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
774 if (aux_log) {
775 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
776 u_log_context_destroy(aux_log);
777 FREE(aux_log);
778 }
779
780 sscreen->aux_context->destroy(sscreen->aux_context);
781
782 util_queue_destroy(&sscreen->shader_compiler_queue);
783 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
784
785 /* Release the reference on glsl types of the compiler threads. */
786 glsl_type_singleton_decref();
787
788 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
789 si_destroy_compiler(&sscreen->compiler[i]);
790
791 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
792 si_destroy_compiler(&sscreen->compiler_lowp[i]);
793
794 /* Free shader parts. */
795 for (i = 0; i < ARRAY_SIZE(parts); i++) {
796 while (parts[i]) {
797 struct si_shader_part *part = parts[i];
798
799 parts[i] = part->next;
800 si_shader_binary_clean(&part->binary);
801 FREE(part);
802 }
803 }
804 simple_mtx_destroy(&sscreen->shader_parts_mutex);
805 si_destroy_shader_cache(sscreen);
806
807 si_destroy_perfcounters(sscreen);
808 si_gpu_load_kill_thread(sscreen);
809
810 simple_mtx_destroy(&sscreen->gpu_load_mutex);
811
812 slab_destroy_parent(&sscreen->pool_transfers);
813
814 disk_cache_destroy(sscreen->disk_shader_cache);
815 sscreen->ws->destroy(sscreen->ws);
816 FREE(sscreen);
817 }
818
819 static void si_init_gs_info(struct si_screen *sscreen)
820 {
821 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
822 sscreen->info.family);
823 }
824
825 static void si_test_vmfault(struct si_screen *sscreen)
826 {
827 struct pipe_context *ctx = sscreen->aux_context;
828 struct si_context *sctx = (struct si_context *)ctx;
829 struct pipe_resource *buf =
830 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
831
832 if (!buf) {
833 puts("Buffer allocation failed.");
834 exit(1);
835 }
836
837 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
838
839 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
840 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
841 SI_COHERENCY_NONE, L2_BYPASS);
842 ctx->flush(ctx, NULL, 0);
843 puts("VM fault test: CP - done.");
844 }
845 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
846 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
847 ctx->flush(ctx, NULL, 0);
848 puts("VM fault test: SDMA - done.");
849 }
850 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
851 util_test_constant_buffer(ctx, buf);
852 puts("VM fault test: Shader - done.");
853 }
854 exit(0);
855 }
856
857 static void si_test_gds_memory_management(struct si_context *sctx,
858 unsigned alloc_size, unsigned alignment,
859 enum radeon_bo_domain domain)
860 {
861 struct radeon_winsys *ws = sctx->ws;
862 struct radeon_cmdbuf *cs[8];
863 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
864
865 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
866 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
867 NULL, NULL, false);
868 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
869 assert(gds_bo[i]);
870 }
871
872 for (unsigned iterations = 0; iterations < 20000; iterations++) {
873 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
874 /* This clears GDS with CP DMA.
875 *
876 * We don't care if GDS is present. Just add some packet
877 * to make the GPU busy for a moment.
878 */
879 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
880 SI_CPDMA_SKIP_BO_LIST_UPDATE |
881 SI_CPDMA_SKIP_CHECK_CS_SPACE |
882 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
883
884 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
885 RADEON_USAGE_READWRITE, 0);
886 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
887 }
888 }
889 exit(0);
890 }
891
892 static void si_disk_cache_create(struct si_screen *sscreen)
893 {
894 /* Don't use the cache if shader dumping is enabled. */
895 if (sscreen->debug_flags & DBG_ALL_SHADERS)
896 return;
897
898 struct mesa_sha1 ctx;
899 unsigned char sha1[20];
900 char cache_id[20 * 2 + 1];
901
902 _mesa_sha1_init(&ctx);
903
904 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
905 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
906 &ctx))
907 return;
908
909 _mesa_sha1_final(&ctx, sha1);
910 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
911
912 /* These flags affect shader compilation. */
913 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
914 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
915
916 /* Add the high bits of 32-bit addresses, which affects
917 * how 32-bit addresses are expanded to 64 bits.
918 */
919 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
920 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
921 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
922
923 sscreen->disk_shader_cache =
924 disk_cache_create(sscreen->info.name,
925 cache_id,
926 shader_debug_flags);
927 }
928
929 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
930 unsigned max_threads)
931 {
932 struct si_screen *sscreen = (struct si_screen *)screen;
933
934 /* This function doesn't allow a greater number of threads than
935 * the queue had at its creation. */
936 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
937 max_threads);
938 /* Don't change the number of threads on the low priority queue. */
939 }
940
941 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
942 void *shader,
943 enum pipe_shader_type shader_type)
944 {
945 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
946
947 return util_queue_fence_is_signalled(&sel->ready);
948 }
949
950 static struct pipe_screen *
951 radeonsi_screen_create_impl(struct radeon_winsys *ws,
952 const struct pipe_screen_config *config)
953 {
954 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
955 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
956
957 if (!sscreen) {
958 return NULL;
959 }
960
961 sscreen->ws = ws;
962 ws->query_info(ws, &sscreen->info);
963
964 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
965 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
966 FREE(sscreen);
967 return NULL;
968 }
969
970 if (sscreen->info.chip_class >= GFX9) {
971 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
972 } else {
973 ac_get_raster_config(&sscreen->info,
974 &sscreen->pa_sc_raster_config,
975 &sscreen->pa_sc_raster_config_1,
976 &sscreen->se_tile_repeat);
977 }
978
979 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
980 debug_options, 0);
981 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
982 debug_options, 0);
983
984 if (sscreen->debug_flags & DBG(NO_GFX))
985 sscreen->info.has_graphics = false;
986
987 /* Set functions first. */
988 sscreen->b.context_create = si_pipe_create_context;
989 sscreen->b.destroy = si_destroy_screen;
990 sscreen->b.set_max_shader_compiler_threads =
991 si_set_max_shader_compiler_threads;
992 sscreen->b.is_parallel_shader_compilation_finished =
993 si_is_parallel_shader_compilation_finished;
994 sscreen->b.finalize_nir = si_finalize_nir;
995
996 si_init_screen_get_functions(sscreen);
997 si_init_screen_buffer_functions(sscreen);
998 si_init_screen_fence_functions(sscreen);
999 si_init_screen_state_functions(sscreen);
1000 si_init_screen_texture_functions(sscreen);
1001 si_init_screen_query_functions(sscreen);
1002
1003 /* Set these flags in debug_flags early, so that the shader cache takes
1004 * them into account.
1005 */
1006 if (driQueryOptionb(config->options,
1007 "glsl_correct_derivatives_after_discard"))
1008 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1009 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
1010 sscreen->debug_flags |= DBG(SI_SCHED);
1011
1012 if (sscreen->debug_flags & DBG(INFO))
1013 ac_print_gpu_info(&sscreen->info);
1014
1015 slab_create_parent(&sscreen->pool_transfers,
1016 sizeof(struct si_transfer), 64);
1017
1018 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1019 if (sscreen->force_aniso == -1) {
1020 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1021 }
1022
1023 if (sscreen->force_aniso >= 0) {
1024 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1025 /* round down to a power of two */
1026 1 << util_logbase2(sscreen->force_aniso));
1027 }
1028
1029 (void) simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
1030 (void) simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1031
1032 si_init_gs_info(sscreen);
1033 if (!si_init_shader_cache(sscreen)) {
1034 FREE(sscreen);
1035 return NULL;
1036 }
1037
1038 {
1039 #define OPT_BOOL(name, dflt, description) \
1040 sscreen->options.name = \
1041 driQueryOptionb(config->options, "radeonsi_"#name);
1042 #include "si_debug_options.h"
1043 }
1044
1045 si_disk_cache_create(sscreen);
1046
1047 /* Determine the number of shader compiler threads. */
1048 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1049
1050 if (hw_threads >= 12) {
1051 num_comp_hi_threads = hw_threads * 3 / 4;
1052 num_comp_lo_threads = hw_threads / 3;
1053 } else if (hw_threads >= 6) {
1054 num_comp_hi_threads = hw_threads - 2;
1055 num_comp_lo_threads = hw_threads / 2;
1056 } else if (hw_threads >= 2) {
1057 num_comp_hi_threads = hw_threads - 1;
1058 num_comp_lo_threads = hw_threads / 2;
1059 } else {
1060 num_comp_hi_threads = 1;
1061 num_comp_lo_threads = 1;
1062 }
1063
1064 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1065 ARRAY_SIZE(sscreen->compiler));
1066 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1067 ARRAY_SIZE(sscreen->compiler_lowp));
1068
1069 /* Take a reference on the glsl types for the compiler threads. */
1070 glsl_type_singleton_init_or_ref();
1071
1072 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1073 64, num_comp_hi_threads,
1074 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1075 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1076 si_destroy_shader_cache(sscreen);
1077 FREE(sscreen);
1078 glsl_type_singleton_decref();
1079 return NULL;
1080 }
1081
1082 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1083 "shlo",
1084 64, num_comp_lo_threads,
1085 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1086 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1087 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1088 si_destroy_shader_cache(sscreen);
1089 FREE(sscreen);
1090 glsl_type_singleton_decref();
1091 return NULL;
1092 }
1093
1094 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1095 si_init_perfcounters(sscreen);
1096
1097 unsigned prim_discard_vertex_count_threshold, tmp;
1098 si_initialize_prim_discard_tunables(sscreen, false,
1099 &prim_discard_vertex_count_threshold,
1100 &tmp);
1101 /* Compute-shader-based culling doesn't support VBOs in user SGPRs. */
1102 if (prim_discard_vertex_count_threshold == UINT_MAX)
1103 sscreen->num_vbos_in_user_sgprs = sscreen->info.chip_class >= GFX9 ? 5 : 1;
1104
1105 /* Determine tessellation ring info. */
1106 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1107 sscreen->info.family != CHIP_CARRIZO &&
1108 sscreen->info.family != CHIP_STONEY;
1109 /* This must be one less than the maximum number due to a hw limitation.
1110 * Various hardware bugs need this.
1111 */
1112 unsigned max_offchip_buffers_per_se;
1113
1114 if (sscreen->info.chip_class >= GFX10)
1115 max_offchip_buffers_per_se = 256;
1116 /* Only certain chips can use the maximum value. */
1117 else if (sscreen->info.family == CHIP_VEGA12 ||
1118 sscreen->info.family == CHIP_VEGA20)
1119 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1120 else
1121 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1122
1123 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1124 sscreen->info.max_se;
1125 unsigned offchip_granularity;
1126
1127 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1128 * around by setting 4K granularity.
1129 */
1130 if (sscreen->info.family == CHIP_HAWAII) {
1131 sscreen->tess_offchip_block_dw_size = 4096;
1132 offchip_granularity = V_03093C_X_4K_DWORDS;
1133 } else {
1134 sscreen->tess_offchip_block_dw_size = 8192;
1135 offchip_granularity = V_03093C_X_8K_DWORDS;
1136 }
1137
1138 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1139 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1140 sscreen->tess_offchip_block_dw_size * 4;
1141
1142 if (sscreen->info.chip_class >= GFX7) {
1143 if (sscreen->info.chip_class >= GFX8)
1144 --max_offchip_buffers;
1145 sscreen->vgt_hs_offchip_param =
1146 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1147 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1148 } else {
1149 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1150 sscreen->vgt_hs_offchip_param =
1151 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1152 }
1153
1154 sscreen->has_draw_indirect_multi =
1155 (sscreen->info.family >= CHIP_POLARIS10) ||
1156 (sscreen->info.chip_class == GFX8 &&
1157 sscreen->info.pfp_fw_version >= 121 &&
1158 sscreen->info.me_fw_version >= 87) ||
1159 (sscreen->info.chip_class == GFX7 &&
1160 sscreen->info.pfp_fw_version >= 211 &&
1161 sscreen->info.me_fw_version >= 173) ||
1162 (sscreen->info.chip_class == GFX6 &&
1163 sscreen->info.pfp_fw_version >= 79 &&
1164 sscreen->info.me_fw_version >= 142);
1165
1166 sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast &&
1167 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1168 sscreen->assume_no_z_fights =
1169 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1170 sscreen->commutative_blend_add =
1171 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1172
1173 sscreen->use_ngg = sscreen->info.chip_class >= GFX10 &&
1174 sscreen->info.family != CHIP_NAVI14 &&
1175 !(sscreen->debug_flags & DBG(NO_NGG));
1176 sscreen->use_ngg_streamout = false;
1177
1178 /* Only enable primitive binning on APUs by default. */
1179 if (sscreen->info.chip_class >= GFX10) {
1180 sscreen->dpbb_allowed = true;
1181 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1182 } else if (sscreen->info.chip_class == GFX9) {
1183 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1184 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1185 }
1186
1187 /* Process DPBB enable flags. */
1188 if (sscreen->debug_flags & DBG(DPBB)) {
1189 sscreen->dpbb_allowed = true;
1190 if (sscreen->debug_flags & DBG(DFSM))
1191 sscreen->dfsm_allowed = true;
1192 }
1193
1194 /* Process DPBB disable flags. */
1195 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1196 sscreen->dpbb_allowed = false;
1197 sscreen->dfsm_allowed = false;
1198 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1199 sscreen->dfsm_allowed = false;
1200 }
1201
1202 /* While it would be nice not to have this flag, we are constrained
1203 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1204 */
1205 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1206
1207 sscreen->dcc_msaa_allowed =
1208 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1209
1210 (void) simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1211 sscreen->use_monolithic_shaders =
1212 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1213
1214 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1215 SI_CONTEXT_INV_VCACHE;
1216 if (sscreen->info.chip_class <= GFX8) {
1217 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1218 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1219 }
1220
1221 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1222 sscreen->debug_flags |= DBG_ALL_SHADERS;
1223
1224 /* Syntax:
1225 * EQAA=s,z,c
1226 * Example:
1227 * EQAA=8,4,2
1228
1229 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1230 * Constraints:
1231 * s >= z >= c (ignoring this only wastes memory)
1232 * s = [2..16]
1233 * z = [2..8]
1234 * c = [2..8]
1235 *
1236 * Only MSAA color and depth buffers are overriden.
1237 */
1238 if (sscreen->info.has_eqaa_surface_allocator) {
1239 const char *eqaa = debug_get_option("EQAA", NULL);
1240 unsigned s,z,f;
1241
1242 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1243 sscreen->eqaa_force_coverage_samples = s;
1244 sscreen->eqaa_force_z_samples = z;
1245 sscreen->eqaa_force_color_samples = f;
1246 }
1247 }
1248
1249 sscreen->ge_wave_size = 64;
1250 sscreen->ps_wave_size = 64;
1251 sscreen->compute_wave_size = 64;
1252
1253 if (sscreen->info.chip_class >= GFX10) {
1254 /* Pixels shaders: Wave64 is recommended.
1255 * Compute shaders: There are piglit failures with Wave32.
1256 */
1257 sscreen->ge_wave_size = 32;
1258
1259 if (sscreen->debug_flags & DBG(W32_GE))
1260 sscreen->ge_wave_size = 32;
1261 if (sscreen->debug_flags & DBG(W32_PS))
1262 sscreen->ps_wave_size = 32;
1263 if (sscreen->debug_flags & DBG(W32_CS))
1264 sscreen->compute_wave_size = 32;
1265
1266 if (sscreen->debug_flags & DBG(W64_GE))
1267 sscreen->ge_wave_size = 64;
1268 if (sscreen->debug_flags & DBG(W64_PS))
1269 sscreen->ps_wave_size = 64;
1270 if (sscreen->debug_flags & DBG(W64_CS))
1271 sscreen->compute_wave_size = 64;
1272 }
1273
1274 /* Create the auxiliary context. This must be done last. */
1275 sscreen->aux_context = si_create_context(&sscreen->b,
1276 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1277 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1278 if (sscreen->options.aux_debug) {
1279 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1280 u_log_context_init(log);
1281 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1282 }
1283
1284 if (sscreen->debug_flags & DBG(TEST_DMA))
1285 si_test_dma(sscreen);
1286
1287 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1288 si_test_dma_perf(sscreen);
1289 }
1290
1291 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1292 DBG(TEST_VMFAULT_SDMA) |
1293 DBG(TEST_VMFAULT_SHADER)))
1294 si_test_vmfault(sscreen);
1295
1296 if (sscreen->debug_flags & DBG(TEST_GDS))
1297 si_test_gds((struct si_context*)sscreen->aux_context);
1298
1299 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1300 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1301 32 * 1024, 4, RADEON_DOMAIN_GDS);
1302 }
1303 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1304 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1305 4, 1, RADEON_DOMAIN_OA);
1306 }
1307
1308 return &sscreen->b;
1309 }
1310
1311 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1312 {
1313 drmVersionPtr version = drmGetVersion(fd);
1314 struct radeon_winsys *rw = NULL;
1315
1316 switch (version->version_major) {
1317 case 2:
1318 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1319 break;
1320 case 3:
1321 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1322 break;
1323 }
1324
1325 drmFreeVersion(version);
1326 return rw ? rw->screen : NULL;
1327 }