src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26
  27 #include "radeon/radeon_uvd.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 void si_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
  37               unsigned flags)
  38 {
  39         struct si_context *sctx = (struct si_context *)ctx;
  40         struct pipe_query *render_cond = NULL;
  41         boolean render_cond_cond = FALSE;
  42         unsigned render_cond_mode = 0;
  43
  44         if (fence) {
  45                 *fence = sctx->b.ws->cs_create_fence(sctx->b.rings.gfx.cs);
  46         }
  47
  48         /* Disable render condition. */
  49         if (sctx->b.current_render_cond) {
  50                 render_cond = sctx->b.current_render_cond;
  51                 render_cond_cond = sctx->b.current_render_cond_cond;
  52                 render_cond_mode = sctx->b.current_render_cond_mode;
  53                 ctx->render_condition(ctx, NULL, FALSE, 0);
  54         }
  55
  56         si_context_flush(sctx, flags);
  57
  58         /* Re-enable render condition. */
  59         if (render_cond) {
  60                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  61         }
  62 }
  63
  64 static void si_flush_from_st(struct pipe_context *ctx,
  65                              struct pipe_fence_handle **fence,
  66                              unsigned flags)
  67 {
  68         si_flush(ctx, fence,
  69                  flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
  70 }
  71
  72 static void si_flush_from_winsys(void *ctx, unsigned flags)
  73 {
  74         si_flush((struct pipe_context*)ctx, NULL, flags);
  75 }
  76
  77 static void si_destroy_context(struct pipe_context *context)
  78 {
  79         struct si_context *sctx = (struct si_context *)context;
  80
  81         si_release_all_descriptors(sctx);
  82
  83         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  84         r600_resource_reference(&sctx->border_color_table, NULL);
  85
  86         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  87         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  88         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  89
  90         if (sctx->dummy_pixel_shader) {
  91                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  92         }
  93         for (int i = 0; i < 8; i++) {
  94                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
  95                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
  96                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
  97         }
  98         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
  99         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
 100         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
 101         util_unreference_framebuffer_state(&sctx->framebuffer.state);
 102
 103         util_blitter_destroy(sctx->blitter);
 104
 105         si_pm4_cleanup(sctx);
 106
 107         r600_common_context_cleanup(&sctx->b);
 108         FREE(sctx);
 109 }
 110
 111 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
 112 {
 113         struct si_context *sctx = CALLOC_STRUCT(si_context);
 114         struct si_screen* sscreen = (struct si_screen *)screen;
 115         int shader, i;
 116
 117         if (sctx == NULL)
 118                 return NULL;
 119
 120         sctx->b.b.screen = screen; /* this must be set first */
 121         sctx->b.b.priv = priv;
 122         sctx->b.b.destroy = si_destroy_context;
 123         sctx->b.b.flush = si_flush_from_st;
 124         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 125
 126         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 127                 goto fail;
 128
 129         si_init_blit_functions(sctx);
 130         si_init_compute_functions(sctx);
 131
 132         if (sscreen->b.info.has_uvd) {
 133                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 134                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 135         } else {
 136                 sctx->b.b.create_video_codec = vl_create_decoder;
 137                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 138         }
 139
 140         sctx->b.rings.gfx.cs = sctx->b.ws->cs_create(sctx->b.ws, RING_GFX, NULL);
 141         sctx->b.rings.gfx.flush = si_flush_from_winsys;
 142
 143         si_init_all_descriptors(sctx);
 144
 145         /* Initialize cache_flush. */
 146         sctx->cache_flush = si_atom_cache_flush;
 147         sctx->atoms.cache_flush = &sctx->cache_flush;
 148
 149         sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
 150
 151         switch (sctx->b.chip_class) {
 152         case SI:
 153         case CIK:
 154                 si_init_state_functions(sctx);
 155                 si_init_config(sctx);
 156                 break;
 157         default:
 158                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 159                 goto fail;
 160         }
 161
 162         sctx->b.ws->cs_set_flush_callback(sctx->b.rings.gfx.cs, si_flush_from_winsys, sctx);
 163
 164         sctx->blitter = util_blitter_create(&sctx->b.b);
 165         if (sctx->blitter == NULL)
 166                 goto fail;
 167
 168         sctx->dummy_pixel_shader =
 169                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 170                                                      TGSI_SEMANTIC_GENERIC,
 171                                                      TGSI_INTERPOLATE_CONSTANT);
 172         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 173
 174         /* these must be last */
 175         si_begin_new_cs(sctx);
 176         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 177
 178         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 179          * with a NULL buffer). We need to use a dummy buffer instead. */
 180         if (sctx->b.chip_class == CIK) {
 181                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 182                                                                  PIPE_USAGE_DEFAULT, 16);
 183                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 184
 185                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 186                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 187                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 188                                                               &sctx->null_const_buf);
 189                         }
 190                 }
 191
 192                 /* Clear the NULL constant buffer, because loads should return zeros. */
 193                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 194                                      sctx->null_const_buf.buffer->width0, 0);
 195         }
 196
 197         return &sctx->b.b;
 198 fail:
 199         si_destroy_context(&sctx->b.b);
 200         return NULL;
 201 }
 202
 203 /*
 204  * pipe_screen
 205  */
 206
 207 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 208 {
 209         struct si_screen *sscreen = (struct si_screen *)pscreen;
 210
 211         switch (param) {
 212         /* Supported features (boolean caps). */
 213         case PIPE_CAP_TWO_SIDED_STENCIL:
 214         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 215         case PIPE_CAP_ANISOTROPIC_FILTER:
 216         case PIPE_CAP_POINT_SPRITE:
 217         case PIPE_CAP_OCCLUSION_QUERY:
 218         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 219         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 220         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 221         case PIPE_CAP_TEXTURE_SWIZZLE:
 222         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 223         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 224         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 225         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 226         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 227         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 228         case PIPE_CAP_SM3:
 229         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 230         case PIPE_CAP_PRIMITIVE_RESTART:
 231         case PIPE_CAP_CONDITIONAL_RENDER:
 232         case PIPE_CAP_TEXTURE_BARRIER:
 233         case PIPE_CAP_INDEP_BLEND_ENABLE:
 234         case PIPE_CAP_INDEP_BLEND_FUNC:
 235         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 236         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 237         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 238         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 239         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 240         case PIPE_CAP_USER_INDEX_BUFFERS:
 241         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 242         case PIPE_CAP_START_INSTANCE:
 243         case PIPE_CAP_NPOT_TEXTURES:
 244         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 245         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 246         case PIPE_CAP_TGSI_INSTANCEID:
 247         case PIPE_CAP_COMPUTE:
 248         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 249         case PIPE_CAP_TGSI_VS_LAYER:
 250         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 251         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 252                 return 1;
 253
 254         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 255                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 256                 return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
 257                                                sscreen->b.info.drm_minor >= 35);
 258
 259         case PIPE_CAP_TGSI_TEXCOORD:
 260                 return 0;
 261
 262         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 263                 return 64;
 264
 265         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 266                 return 256;
 267
 268         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 269                 return HAVE_LLVM >= 0x0305 ? 330 : 140;
 270
 271         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 272                 return 1;
 273         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 274                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 275
 276         /* Unsupported features. */
 277         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 278         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 279         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 280         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 281         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 282         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 283         case PIPE_CAP_USER_VERTEX_BUFFERS:
 284         case PIPE_CAP_CUBE_MAP_ARRAY:
 285         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 286         case PIPE_CAP_TEXTURE_GATHER_SM5:
 287                 return 0;
 288
 289         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 290                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 291
 292         /* Stream output. */
 293         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 294                 return sscreen->b.has_streamout ? 4 : 0;
 295         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 296                 return sscreen->b.has_streamout ? 1 : 0;
 297         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 298         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 299                 return sscreen->b.has_streamout ? 32*4 : 0;
 300
 301         /* Geometry shader output. */
 302         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 303                 return 1024;
 304         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 305                 return 4095;
 306
 307         /* Texturing. */
 308         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 309         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 310         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 311                         return 15;
 312         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 313                 return 16384;
 314
 315         /* Render targets. */
 316         case PIPE_CAP_MAX_RENDER_TARGETS:
 317                 return 8;
 318
 319         case PIPE_CAP_MAX_VIEWPORTS:
 320                 return 1;
 321
 322         /* Timer queries, present when the clock frequency is non zero. */
 323         case PIPE_CAP_QUERY_TIMESTAMP:
 324         case PIPE_CAP_QUERY_TIME_ELAPSED:
 325                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 326
 327         case PIPE_CAP_MIN_TEXEL_OFFSET:
 328                 return -8;
 329
 330         case PIPE_CAP_MAX_TEXEL_OFFSET:
 331                 return 7;
 332         case PIPE_CAP_ENDIANNESS:
 333                 return PIPE_ENDIAN_LITTLE;
 334         }
 335         return 0;
 336 }
 337
 338 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 339 {
 340         switch(shader)
 341         {
 342         case PIPE_SHADER_FRAGMENT:
 343         case PIPE_SHADER_VERTEX:
 344                 break;
 345         case PIPE_SHADER_GEOMETRY:
 346 #if HAVE_LLVM < 0x0305
 347                 return 0;
 348 #endif
 349                 break;
 350         case PIPE_SHADER_COMPUTE:
 351                 switch (param) {
 352                 case PIPE_SHADER_CAP_PREFERRED_IR:
 353                         return PIPE_SHADER_IR_LLVM;
 354                 default:
 355                         return 0;
 356                 }
 357         default:
 358                 /* TODO: support tessellation */
 359                 return 0;
 360         }
 361
 362         switch (param) {
 363         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 364         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 365         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 366         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 367                 return 16384;
 368         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 369                 return 32;
 370         case PIPE_SHADER_CAP_MAX_INPUTS:
 371                 return 32;
 372         case PIPE_SHADER_CAP_MAX_TEMPS:
 373                 return 256; /* Max native temporaries. */
 374         case PIPE_SHADER_CAP_MAX_ADDRS:
 375                 /* FIXME Isn't this equal to TEMPS? */
 376                 return 1; /* Max native address registers */
 377         case PIPE_SHADER_CAP_MAX_CONSTS:
 378                 return 4096; /* actually only memory limits this */
 379         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 380                 return NUM_PIPE_CONST_BUFFERS;
 381         case PIPE_SHADER_CAP_MAX_PREDS:
 382                 return 0; /* FIXME */
 383         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 384                 return 1;
 385         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 386                 return 0;
 387         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 388                 /* Indirection of geometry shader input dimension is not
 389                  * handled yet
 390                  */
 391                 return shader < PIPE_SHADER_GEOMETRY;
 392         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 393         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 394         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 395                 return 1;
 396         case PIPE_SHADER_CAP_INTEGERS:
 397                 return 1;
 398         case PIPE_SHADER_CAP_SUBROUTINES:
 399                 return 0;
 400         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 401         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 402                 return 16;
 403         case PIPE_SHADER_CAP_PREFERRED_IR:
 404                 return PIPE_SHADER_IR_TGSI;
 405         }
 406         return 0;
 407 }
 408
 409 static void si_destroy_screen(struct pipe_screen* pscreen)
 410 {
 411         struct si_screen *sscreen = (struct si_screen *)pscreen;
 412
 413         if (sscreen == NULL)
 414                 return;
 415
 416         if (!radeon_winsys_unref(sscreen->b.ws))
 417                 return;
 418
 419         r600_destroy_common_screen(&sscreen->b);
 420 }
 421
 422 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 423 {
 424         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 425         if (sscreen == NULL) {
 426                 return NULL;
 427         }
 428
 429         /* Set functions first. */
 430         sscreen->b.b.context_create = si_create_context;
 431         sscreen->b.b.destroy = si_destroy_screen;
 432         sscreen->b.b.get_param = si_get_param;
 433         sscreen->b.b.get_shader_param = si_get_shader_param;
 434         sscreen->b.b.is_format_supported = si_is_format_supported;
 435         sscreen->b.b.resource_create = r600_resource_create_common;
 436
 437         if (!r600_common_screen_init(&sscreen->b, ws)) {
 438                 FREE(sscreen);
 439                 return NULL;
 440         }
 441
 442         sscreen->b.has_cp_dma = true;
 443         sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 444
 445         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 446                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 447
 448         /* Create the auxiliary context. This must be done last. */
 449         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 450
 451         return &sscreen->b.b;
 452 }