src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_log.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_suballoc.h"
  34 #include "util/u_tests.h"
  35 #include "util/xmlconfig.h"
  36 #include "vl/vl_decoder.h"
  37 #include "../ddebug/dd_util.h"
  38
  39 #include "compiler/nir/nir.h"
  40
  41 /*
  42  * pipe_context
  43  */
  44 static void si_destroy_context(struct pipe_context *context)
  45 {
  46         struct si_context *sctx = (struct si_context *)context;
  47         int i;
  48
  49         /* Unreference the framebuffer normally to disable related logic
  50          * properly.
  51          */
  52         struct pipe_framebuffer_state fb = {};
  53         if (context->set_framebuffer_state)
  54                 context->set_framebuffer_state(context, &fb);
  55
  56         si_release_all_descriptors(sctx);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_fmask_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  83         if (sctx->custom_blend_eliminate_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87         if (sctx->vs_blit_pos)
  88                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos);
  89         if (sctx->vs_blit_pos_layered)
  90                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos_layered);
  91         if (sctx->vs_blit_color)
  92                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color);
  93         if (sctx->vs_blit_color_layered)
  94                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color_layered);
  95         if (sctx->vs_blit_texcoord)
  96                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_texcoord);
  97
  98         if (sctx->blitter)
  99                 util_blitter_destroy(sctx->blitter);
 100
 101         si_common_context_cleanup(&sctx->b);
 102
 103         LLVMDisposeTargetMachine(sctx->tm);
 104
 105         si_saved_cs_reference(&sctx->current_saved_cs, NULL);
 106
 107         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 108         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 109
 110         util_dynarray_fini(&sctx->resident_tex_handles);
 111         util_dynarray_fini(&sctx->resident_img_handles);
 112         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 113         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 114         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 115         FREE(sctx);
 116 }
 117
 118 static enum pipe_reset_status
 119 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 120 {
 121         struct si_context *sctx = (struct si_context *)ctx;
 122
 123         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 124 }
 125
 126 /* Apitrace profiling:
 127  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 128  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 129  *      and remember its number.
 130  *   3) In Mesa, enable queries and performance counters around that draw
 131  *      call and print the results.
 132  *   4) glretrace --benchmark --markers ..
 133  */
 134 static void si_emit_string_marker(struct pipe_context *ctx,
 135                                   const char *string, int len)
 136 {
 137         struct si_context *sctx = (struct si_context *)ctx;
 138
 139         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 140
 141         if (sctx->b.log)
 142                 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
 143 }
 144
 145 static LLVMTargetMachineRef
 146 si_create_llvm_target_machine(struct si_screen *sscreen)
 147 {
 148         const char *triple = "amdgcn--";
 149         char features[256];
 150
 151         snprintf(features, sizeof(features),
 152                  "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
 153                  sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
 154                  sscreen->llvm_has_working_vgpr_indexing ? "" : ",-promote-alloca",
 155                  sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
 156
 157         return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
 158                                        si_get_llvm_processor_name(sscreen->b.family),
 159                                        features,
 160                                        LLVMCodeGenLevelDefault,
 161                                        LLVMRelocDefault,
 162                                        LLVMCodeModelDefault);
 163 }
 164
 165 static void si_set_log_context(struct pipe_context *ctx,
 166                                struct u_log_context *log)
 167 {
 168         struct si_context *sctx = (struct si_context *)ctx;
 169         sctx->b.log = log;
 170
 171         if (log)
 172                 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
 173 }
 174
 175 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 176                                               unsigned flags)
 177 {
 178         struct si_context *sctx = CALLOC_STRUCT(si_context);
 179         struct si_screen* sscreen = (struct si_screen *)screen;
 180         struct radeon_winsys *ws = sscreen->b.ws;
 181         int shader, i;
 182
 183         if (!sctx)
 184                 return NULL;
 185
 186         if (flags & PIPE_CONTEXT_DEBUG)
 187                 sscreen->record_llvm_ir = true; /* racy but not critical */
 188
 189         sctx->b.b.screen = screen; /* this must be set first */
 190         sctx->b.b.priv = NULL;
 191         sctx->b.b.destroy = si_destroy_context;
 192         sctx->b.b.emit_string_marker = si_emit_string_marker;
 193         sctx->b.b.set_log_context = si_set_log_context;
 194         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 195         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 196         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 197
 198         if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
 199                 goto fail;
 200
 201         if (sscreen->b.info.drm_major == 3)
 202                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 203
 204         si_init_blit_functions(sctx);
 205         si_init_compute_functions(sctx);
 206         si_init_cp_dma_functions(sctx);
 207         si_init_debug_functions(sctx);
 208
 209         if (sscreen->b.info.has_hw_decode) {
 210                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 211                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 212         } else {
 213                 sctx->b.b.create_video_codec = vl_create_decoder;
 214                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 215         }
 216
 217         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 218                                        si_context_gfx_flush, sctx);
 219         sctx->b.gfx.flush = si_context_gfx_flush;
 220
 221         /* Border colors. */
 222         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 223                                           sizeof(*sctx->border_color_table));
 224         if (!sctx->border_color_table)
 225                 goto fail;
 226
 227         sctx->border_color_buffer = (struct r600_resource*)
 228                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 229                                    SI_MAX_BORDER_COLORS *
 230                                    sizeof(*sctx->border_color_table));
 231         if (!sctx->border_color_buffer)
 232                 goto fail;
 233
 234         sctx->border_color_map =
 235                 ws->buffer_map(sctx->border_color_buffer->buf,
 236                                NULL, PIPE_TRANSFER_WRITE);
 237         if (!sctx->border_color_map)
 238                 goto fail;
 239
 240         si_init_all_descriptors(sctx);
 241         si_init_state_functions(sctx);
 242         si_init_shader_functions(sctx);
 243         si_init_viewport_functions(sctx);
 244         si_init_ia_multi_vgt_param_table(sctx);
 245
 246         if (sctx->b.chip_class >= CIK)
 247                 cik_init_sdma_functions(sctx);
 248         else
 249                 si_init_dma_functions(sctx);
 250
 251         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 252                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 253
 254         sctx->blitter = util_blitter_create(&sctx->b.b);
 255         if (sctx->blitter == NULL)
 256                 goto fail;
 257         sctx->blitter->draw_rectangle = si_draw_rectangle;
 258
 259         sctx->sample_mask.sample_mask = 0xffff;
 260
 261         /* these must be last */
 262         si_begin_new_cs(sctx);
 263
 264         if (sctx->b.chip_class >= GFX9) {
 265                 sctx->wait_mem_scratch = (struct r600_resource*)
 266                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 267                 if (!sctx->wait_mem_scratch)
 268                         goto fail;
 269
 270                 /* Initialize the memory. */
 271                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 272                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 273                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 274                             S_370_WR_CONFIRM(1) |
 275                             S_370_ENGINE_SEL(V_370_ME));
 276                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 277                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 278                 radeon_emit(cs, sctx->wait_mem_number);
 279         }
 280
 281         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 282          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 283         if (sctx->b.chip_class == CIK) {
 284                 sctx->null_const_buf.buffer =
 285                         si_aligned_buffer_create(screen,
 286                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 287                                                    PIPE_USAGE_DEFAULT, 16,
 288                                                    sctx->screen->b.info.tcc_cache_line_size);
 289                 if (!sctx->null_const_buf.buffer)
 290                         goto fail;
 291                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 292
 293                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 294                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 295                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 296                                                               &sctx->null_const_buf);
 297                         }
 298                 }
 299
 300                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 301                                  &sctx->null_const_buf);
 302                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 303                                  &sctx->null_const_buf);
 304                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 305                                  &sctx->null_const_buf);
 306                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 307                                  &sctx->null_const_buf);
 308                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 309                                  &sctx->null_const_buf);
 310
 311                 /* Clear the NULL constant buffer, because loads should return zeros. */
 312                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 313                                      sctx->null_const_buf.buffer->width0, 0,
 314                                      R600_COHERENCY_SHADER);
 315         }
 316
 317         uint64_t max_threads_per_block;
 318         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 319                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 320                                   &max_threads_per_block);
 321
 322         /* The maximum number of scratch waves. Scratch space isn't divided
 323          * evenly between CUs. The number is only a function of the number of CUs.
 324          * We can decrease the constant to decrease the scratch buffer size.
 325          *
 326          * sctx->scratch_waves must be >= the maximum posible size of
 327          * 1 threadgroup, so that the hw doesn't hang from being unable
 328          * to start any.
 329          *
 330          * The recommended value is 4 per CU at most. Higher numbers don't
 331          * bring much benefit, but they still occupy chip resources (think
 332          * async compute). I've seen ~2% performance difference between 4 and 32.
 333          */
 334         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 335                                    max_threads_per_block / 64);
 336
 337         sctx->tm = si_create_llvm_target_machine(sscreen);
 338
 339         /* Bindless handles. */
 340         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 341                                                     _mesa_key_pointer_equal);
 342         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 343                                                     _mesa_key_pointer_equal);
 344
 345         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 346         util_dynarray_init(&sctx->resident_img_handles, NULL);
 347         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 348         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 349         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 350
 351         return &sctx->b.b;
 352 fail:
 353         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 354         si_destroy_context(&sctx->b.b);
 355         return NULL;
 356 }
 357
 358 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 359                                                    void *priv, unsigned flags)
 360 {
 361         struct si_screen *sscreen = (struct si_screen *)screen;
 362         struct pipe_context *ctx;
 363
 364         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 365                 flags |= PIPE_CONTEXT_DEBUG;
 366
 367         ctx = si_create_context(screen, flags);
 368
 369         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 370                 return ctx;
 371
 372         /* Clover (compute-only) is unsupported.
 373          *
 374          * Since the threaded context creates shader states from the non-driver
 375          * thread, asynchronous compilation is required for create_{shader}_-
 376          * state not to use pipe_context. Debug contexts (ddebug) disable
 377          * asynchronous compilation, so don't use the threaded context with
 378          * those.
 379          */
 380         if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
 381                 return ctx;
 382
 383         /* When shaders are logged to stderr, asynchronous compilation is
 384          * disabled too. */
 385         if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
 386                 return ctx;
 387
 388         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 389                                        si_replace_buffer_storage,
 390                                        &((struct si_context*)ctx)->b.tc);
 391 }
 392
 393 /*
 394  * pipe_screen
 395  */
 396 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 397 {
 398         /* Old kernels disallowed some register writes for SI
 399          * that are used for indirect dispatches. */
 400         return (sscreen->b.chip_class >= CIK ||
 401                 sscreen->b.info.drm_major == 3 ||
 402                 (sscreen->b.info.drm_major == 2 &&
 403                  sscreen->b.info.drm_minor >= 45));
 404 }
 405
 406 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 407 {
 408         struct si_screen *sscreen = (struct si_screen *)pscreen;
 409
 410         switch (param) {
 411         /* Supported features (boolean caps). */
 412         case PIPE_CAP_ACCELERATED:
 413         case PIPE_CAP_TWO_SIDED_STENCIL:
 414         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 415         case PIPE_CAP_ANISOTROPIC_FILTER:
 416         case PIPE_CAP_POINT_SPRITE:
 417         case PIPE_CAP_OCCLUSION_QUERY:
 418         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 419         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 420         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 421         case PIPE_CAP_TEXTURE_SWIZZLE:
 422         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 423         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 424         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 425         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 426         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 427         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 428         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 429         case PIPE_CAP_SM3:
 430         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 431         case PIPE_CAP_PRIMITIVE_RESTART:
 432         case PIPE_CAP_CONDITIONAL_RENDER:
 433         case PIPE_CAP_TEXTURE_BARRIER:
 434         case PIPE_CAP_INDEP_BLEND_ENABLE:
 435         case PIPE_CAP_INDEP_BLEND_FUNC:
 436         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 437         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 438         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 439         case PIPE_CAP_START_INSTANCE:
 440         case PIPE_CAP_NPOT_TEXTURES:
 441         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 442         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 443         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 444         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 445         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 446         case PIPE_CAP_TGSI_INSTANCEID:
 447         case PIPE_CAP_COMPUTE:
 448         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 449         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 450         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 451         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 452         case PIPE_CAP_CUBE_MAP_ARRAY:
 453         case PIPE_CAP_SAMPLE_SHADING:
 454         case PIPE_CAP_DRAW_INDIRECT:
 455         case PIPE_CAP_CLIP_HALFZ:
 456         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 457         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 458         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 459         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 460         case PIPE_CAP_TGSI_TEXCOORD:
 461         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 462         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 463         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 464         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 465         case PIPE_CAP_SHAREABLE_SHADERS:
 466         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 467         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 468         case PIPE_CAP_TEXTURE_QUERY_LOD:
 469         case PIPE_CAP_TEXTURE_GATHER_SM5:
 470         case PIPE_CAP_TGSI_TXQS:
 471         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 472         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 473         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 474         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 475         case PIPE_CAP_INVALIDATE_BUFFER:
 476         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 477         case PIPE_CAP_QUERY_MEMORY_INFO:
 478         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 479         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 480         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 481         case PIPE_CAP_GENERATE_MIPMAP:
 482         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 483         case PIPE_CAP_STRING_MARKER:
 484         case PIPE_CAP_CLEAR_TEXTURE:
 485         case PIPE_CAP_CULL_DISTANCE:
 486         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 487         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 488         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 489         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 490         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 491         case PIPE_CAP_DOUBLES:
 492         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 493         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 494         case PIPE_CAP_BINDLESS_TEXTURE:
 495         case PIPE_CAP_QUERY_TIMESTAMP:
 496         case PIPE_CAP_QUERY_TIME_ELAPSED:
 497         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 498         case PIPE_CAP_QUERY_SO_OVERFLOW:
 499         case PIPE_CAP_MEMOBJ:
 500         case PIPE_CAP_LOAD_CONSTBUF:
 501         case PIPE_CAP_INT64:
 502         case PIPE_CAP_INT64_DIVMOD:
 503         case PIPE_CAP_TGSI_CLOCK:
 504         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 505         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 506         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 507                 return 1;
 508
 509         case PIPE_CAP_TGSI_VOTE:
 510                 return HAVE_LLVM >= 0x0400;
 511
 512         case PIPE_CAP_TGSI_BALLOT:
 513                 return HAVE_LLVM >= 0x0500;
 514
 515         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 516                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 517
 518         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 519                 return (sscreen->b.info.drm_major == 2 &&
 520                         sscreen->b.info.drm_minor >= 43) ||
 521                        sscreen->b.info.drm_major == 3;
 522
 523         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 524                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 525                 return sscreen->b.chip_class < CIK ||
 526                        (sscreen->b.info.drm_major == 2 &&
 527                         sscreen->b.info.drm_minor >= 35) ||
 528                        sscreen->b.info.drm_major == 3;
 529
 530         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 531                 return R600_MAP_BUFFER_ALIGNMENT;
 532
 533         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 534         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 535         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 536         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 537         case PIPE_CAP_MAX_VERTEX_STREAMS:
 538         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 539                 return 4;
 540
 541         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 542                 if (sscreen->b.debug_flags & DBG_NIR)
 543                         return 140; /* no geometry and tessellation shaders yet */
 544                 if (si_have_tgsi_compute(sscreen))
 545                         return 450;
 546                 return 420;
 547
 548         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 549                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 550
 551         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 552         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 553         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 554                 /* SI doesn't support unaligned loads.
 555                  * CIK needs DRM 2.50.0 on radeon. */
 556                 return sscreen->b.chip_class == SI ||
 557                        (sscreen->b.info.drm_major == 2 &&
 558                         sscreen->b.info.drm_minor < 50);
 559
 560         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 561                 /* TODO: GFX9 hangs. */
 562                 if (sscreen->b.chip_class >= GFX9)
 563                         return 0;
 564                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 565                  * faults are mitigated in software.
 566                  */
 567                 if (sscreen->b.chip_class >= CIK &&
 568                     sscreen->b.info.drm_major == 3 &&
 569                     sscreen->b.info.drm_minor >= 13)
 570                         return RADEON_SPARSE_PAGE_SIZE;
 571                 return 0;
 572
 573         /* Unsupported features. */
 574         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 575         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 576         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 577         case PIPE_CAP_USER_VERTEX_BUFFERS:
 578         case PIPE_CAP_FAKE_SW_MSAA:
 579         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 580         case PIPE_CAP_VERTEXID_NOBASE:
 581         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 582         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 583         case PIPE_CAP_NATIVE_FENCE_FD:
 584         case PIPE_CAP_TGSI_FS_FBFETCH:
 585         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 586         case PIPE_CAP_UMA:
 587         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 588         case PIPE_CAP_POST_DEPTH_COVERAGE:
 589                 return 0;
 590
 591         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 592                 return si_have_tgsi_compute(sscreen);
 593
 594         case PIPE_CAP_DRAW_PARAMETERS:
 595         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 596         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 597                 return sscreen->has_draw_indirect_multi;
 598
 599         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 600                 return 30;
 601
 602         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 603                 return sscreen->b.chip_class <= VI ?
 604                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 605
 606         /* Stream output. */
 607         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 608         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 609                 return 32*4;
 610
 611         /* Geometry shader output. */
 612         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 613                 return 1024;
 614         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 615                 return 4095;
 616
 617         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 618                 return 2048;
 619
 620         /* Texturing. */
 621         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 622         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 623                 return 15; /* 16384 */
 624         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 625                 /* textures support 8192, but layered rendering supports 2048 */
 626                 return 12;
 627         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 628                 /* textures support 8192, but layered rendering supports 2048 */
 629                 return 2048;
 630
 631         /* Viewports and render targets. */
 632         case PIPE_CAP_MAX_VIEWPORTS:
 633                 return SI_MAX_VIEWPORTS;
 634         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 635         case PIPE_CAP_MAX_RENDER_TARGETS:
 636                 return 8;
 637
 638         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 639         case PIPE_CAP_MIN_TEXEL_OFFSET:
 640                 return -32;
 641
 642         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 643         case PIPE_CAP_MAX_TEXEL_OFFSET:
 644                 return 31;
 645
 646         case PIPE_CAP_ENDIANNESS:
 647                 return PIPE_ENDIAN_LITTLE;
 648
 649         case PIPE_CAP_VENDOR_ID:
 650                 return ATI_VENDOR_ID;
 651         case PIPE_CAP_DEVICE_ID:
 652                 return sscreen->b.info.pci_id;
 653         case PIPE_CAP_VIDEO_MEMORY:
 654                 return sscreen->b.info.vram_size >> 20;
 655         case PIPE_CAP_PCI_GROUP:
 656                 return sscreen->b.info.pci_domain;
 657         case PIPE_CAP_PCI_BUS:
 658                 return sscreen->b.info.pci_bus;
 659         case PIPE_CAP_PCI_DEVICE:
 660                 return sscreen->b.info.pci_dev;
 661         case PIPE_CAP_PCI_FUNCTION:
 662                 return sscreen->b.info.pci_func;
 663         }
 664         return 0;
 665 }
 666
 667 static int si_get_shader_param(struct pipe_screen* pscreen,
 668                                enum pipe_shader_type shader,
 669                                enum pipe_shader_cap param)
 670 {
 671         struct si_screen *sscreen = (struct si_screen *)pscreen;
 672
 673         switch(shader)
 674         {
 675         case PIPE_SHADER_FRAGMENT:
 676         case PIPE_SHADER_VERTEX:
 677         case PIPE_SHADER_GEOMETRY:
 678         case PIPE_SHADER_TESS_CTRL:
 679         case PIPE_SHADER_TESS_EVAL:
 680                 break;
 681         case PIPE_SHADER_COMPUTE:
 682                 switch (param) {
 683                 case PIPE_SHADER_CAP_PREFERRED_IR:
 684                         return PIPE_SHADER_IR_NATIVE;
 685
 686                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 687                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 688
 689                         if (si_have_tgsi_compute(sscreen))
 690                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 691
 692                         return ir;
 693                 }
 694
 695                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 696                         uint64_t max_const_buffer_size;
 697                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 698                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 699                                 &max_const_buffer_size);
 700                         return MIN2(max_const_buffer_size, INT_MAX);
 701                 }
 702                 default:
 703                         /* If compute shaders don't require a special value
 704                          * for this cap, we can return the same value we
 705                          * do for other shader types. */
 706                         break;
 707                 }
 708                 break;
 709         default:
 710                 return 0;
 711         }
 712
 713         switch (param) {
 714         /* Shader limits. */
 715         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 716         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 717         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 718         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 719         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 720                 return 16384;
 721         case PIPE_SHADER_CAP_MAX_INPUTS:
 722                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 723         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 724                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 725         case PIPE_SHADER_CAP_MAX_TEMPS:
 726                 return 256; /* Max native temporaries. */
 727         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 728                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 729         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 730                 return SI_NUM_CONST_BUFFERS;
 731         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 732         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 733                 return SI_NUM_SAMPLERS;
 734         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 735                 return SI_NUM_SHADER_BUFFERS;
 736         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 737                 return SI_NUM_IMAGES;
 738         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 739                 return 32;
 740         case PIPE_SHADER_CAP_PREFERRED_IR:
 741                 if (sscreen->b.debug_flags & DBG_NIR &&
 742                     (shader == PIPE_SHADER_VERTEX ||
 743                      shader == PIPE_SHADER_FRAGMENT))
 744                         return PIPE_SHADER_IR_NIR;
 745                 return PIPE_SHADER_IR_TGSI;
 746         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 747                 return 4;
 748
 749         /* Supported boolean features. */
 750         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 751         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 752         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 753         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 754         case PIPE_SHADER_CAP_INTEGERS:
 755         case PIPE_SHADER_CAP_INT64_ATOMICS:
 756         case PIPE_SHADER_CAP_FP16:
 757         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 758         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 759         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 760         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 761         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 762         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 763                 return 1;
 764
 765         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 766                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 767                 return shader != PIPE_SHADER_GEOMETRY &&
 768                        (sscreen->llvm_has_working_vgpr_indexing ||
 769                         /* TCS and TES load inputs directly from LDS or
 770                          * offchip memory, so indirect indexing is trivial. */
 771                         shader == PIPE_SHADER_TESS_CTRL ||
 772                         shader == PIPE_SHADER_TESS_EVAL);
 773
 774         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 775                 return sscreen->llvm_has_working_vgpr_indexing ||
 776                        /* TCS stores outputs directly to memory. */
 777                        shader == PIPE_SHADER_TESS_CTRL;
 778
 779         /* Unsupported boolean features. */
 780         case PIPE_SHADER_CAP_SUBROUTINES:
 781         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 782                 return 0;
 783         }
 784         return 0;
 785 }
 786
 787 static const struct nir_shader_compiler_options nir_options = {
 788         .vertex_id_zero_based = true,
 789         .lower_scmp = true,
 790         .lower_flrp32 = true,
 791         .lower_fsat = true,
 792         .lower_fdiv = true,
 793         .lower_sub = true,
 794         .lower_pack_snorm_2x16 = true,
 795         .lower_pack_snorm_4x8 = true,
 796         .lower_pack_unorm_2x16 = true,
 797         .lower_pack_unorm_4x8 = true,
 798         .lower_unpack_snorm_2x16 = true,
 799         .lower_unpack_snorm_4x8 = true,
 800         .lower_unpack_unorm_2x16 = true,
 801         .lower_unpack_unorm_4x8 = true,
 802         .lower_extract_byte = true,
 803         .lower_extract_word = true,
 804         .max_unroll_iterations = 32,
 805         .native_integers = true,
 806 };
 807
 808 static const void *
 809 si_get_compiler_options(struct pipe_screen *screen,
 810                         enum pipe_shader_ir ir,
 811                         enum pipe_shader_type shader)
 812 {
 813         assert(ir == PIPE_SHADER_IR_NIR);
 814         return &nir_options;
 815 }
 816
 817 static void si_destroy_screen(struct pipe_screen* pscreen)
 818 {
 819         struct si_screen *sscreen = (struct si_screen *)pscreen;
 820         struct si_shader_part *parts[] = {
 821                 sscreen->vs_prologs,
 822                 sscreen->tcs_epilogs,
 823                 sscreen->gs_prologs,
 824                 sscreen->ps_prologs,
 825                 sscreen->ps_epilogs
 826         };
 827         unsigned i;
 828
 829         if (!sscreen->b.ws->unref(sscreen->b.ws))
 830                 return;
 831
 832         util_queue_destroy(&sscreen->shader_compiler_queue);
 833         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 834
 835         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 836                 if (sscreen->tm[i])
 837                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 838
 839         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 840                 if (sscreen->tm_low_priority[i])
 841                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 842
 843         /* Free shader parts. */
 844         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 845                 while (parts[i]) {
 846                         struct si_shader_part *part = parts[i];
 847
 848                         parts[i] = part->next;
 849                         si_radeon_shader_binary_clean(&part->binary);
 850                         FREE(part);
 851                 }
 852         }
 853         mtx_destroy(&sscreen->shader_parts_mutex);
 854         si_destroy_shader_cache(sscreen);
 855         si_destroy_common_screen(&sscreen->b);
 856 }
 857
 858 static bool si_init_gs_info(struct si_screen *sscreen)
 859 {
 860         switch (sscreen->b.family) {
 861         case CHIP_OLAND:
 862         case CHIP_HAINAN:
 863         case CHIP_KAVERI:
 864         case CHIP_KABINI:
 865         case CHIP_MULLINS:
 866         case CHIP_ICELAND:
 867         case CHIP_CARRIZO:
 868         case CHIP_STONEY:
 869                 sscreen->gs_table_depth = 16;
 870                 return true;
 871         case CHIP_TAHITI:
 872         case CHIP_PITCAIRN:
 873         case CHIP_VERDE:
 874         case CHIP_BONAIRE:
 875         case CHIP_HAWAII:
 876         case CHIP_TONGA:
 877         case CHIP_FIJI:
 878         case CHIP_POLARIS10:
 879         case CHIP_POLARIS11:
 880         case CHIP_POLARIS12:
 881         case CHIP_VEGA10:
 882         case CHIP_RAVEN:
 883                 sscreen->gs_table_depth = 32;
 884                 return true;
 885         default:
 886                 return false;
 887         }
 888 }
 889
 890 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 891 {
 892         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 893         unsigned i;
 894
 895         if (!family)
 896                 return;
 897
 898         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 899                 if (!strcmp(family, si_get_llvm_processor_name(i))) {
 900                         /* Override family and chip_class. */
 901                         sscreen->b.family = sscreen->b.info.family = i;
 902
 903                         if (i >= CHIP_VEGA10)
 904                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 905                         else if (i >= CHIP_TONGA)
 906                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 907                         else if (i >= CHIP_BONAIRE)
 908                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 909                         else
 910                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 911
 912                         /* Don't submit any IBs. */
 913                         setenv("RADEON_NOOP", "1", 1);
 914                         return;
 915                 }
 916         }
 917
 918         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 919         exit(1);
 920 }
 921
 922 static void si_test_vmfault(struct si_screen *sscreen)
 923 {
 924         struct pipe_context *ctx = sscreen->b.aux_context;
 925         struct si_context *sctx = (struct si_context *)ctx;
 926         struct pipe_resource *buf =
 927                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 928
 929         if (!buf) {
 930                 puts("Buffer allocation failed.");
 931                 exit(1);
 932         }
 933
 934         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 935
 936         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
 937                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 938                 ctx->flush(ctx, NULL, 0);
 939                 puts("VM fault test: CP - done.");
 940         }
 941         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
 942                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 943                 ctx->flush(ctx, NULL, 0);
 944                 puts("VM fault test: SDMA - done.");
 945         }
 946         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
 947                 util_test_constant_buffer(ctx, buf);
 948                 puts("VM fault test: Shader - done.");
 949         }
 950         exit(0);
 951 }
 952
 953 static void radeonsi_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 954 {
 955         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 956 }
 957
 958 static void radeonsi_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 959 {
 960         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 961
 962         ac_compute_device_uuid(&rscreen->info, uuid, PIPE_UUID_SIZE);
 963 }
 964
 965 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 966                                            const struct pipe_screen_config *config)
 967 {
 968         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 969         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 970
 971         if (!sscreen) {
 972                 return NULL;
 973         }
 974
 975         /* Set functions first. */
 976         sscreen->b.b.context_create = si_pipe_create_context;
 977         sscreen->b.b.destroy = si_destroy_screen;
 978         sscreen->b.b.get_param = si_get_param;
 979         sscreen->b.b.get_shader_param = si_get_shader_param;
 980         sscreen->b.b.get_compiler_options = si_get_compiler_options;
 981         sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
 982         sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
 983         sscreen->b.b.resource_create = si_resource_create_common;
 984
 985         si_init_screen_state_functions(sscreen);
 986
 987         /* Set these flags in debug_flags early, so that the shader cache takes
 988          * them into account.
 989          */
 990         if (driQueryOptionb(config->options,
 991                             "glsl_correct_derivatives_after_discard"))
 992                 sscreen->b.debug_flags |= DBG_FS_CORRECT_DERIVS_AFTER_KILL;
 993         if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
 994                 sscreen->b.debug_flags |= DBG_SI_SCHED;
 995
 996         if (!si_common_screen_init(&sscreen->b, ws) ||
 997             !si_init_gs_info(sscreen) ||
 998             !si_init_shader_cache(sscreen)) {
 999                 FREE(sscreen);
1000                 return NULL;
1001         }
1002
1003         /* Only enable as many threads as we have target machines, but at most
1004          * the number of CPUs - 1 if there is more than one.
1005          */
1006         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
1007         num_threads = MAX2(1, num_threads - 1);
1008         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1009         num_compiler_threads_lowprio =
1010                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1011
1012         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1013                              32, num_compiler_threads,
1014                              UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1015                 si_destroy_shader_cache(sscreen);
1016                 FREE(sscreen);
1017                 return NULL;
1018         }
1019
1020         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1021                              "si_shader_low",
1022                              32, num_compiler_threads_lowprio,
1023                              UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1024                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1025                si_destroy_shader_cache(sscreen);
1026                FREE(sscreen);
1027                return NULL;
1028         }
1029
1030         si_handle_env_var_force_family(sscreen);
1031
1032         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1033                 si_init_perfcounters(sscreen);
1034
1035         /* Hawaii has a bug with offchip buffers > 256 that can be worked
1036          * around by setting 4K granularity.
1037          */
1038         sscreen->tess_offchip_block_dw_size =
1039                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1040
1041         /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1042          * on SI. */
1043         sscreen->has_clear_state = sscreen->b.chip_class >= CIK;
1044
1045         sscreen->has_distributed_tess =
1046                 sscreen->b.chip_class >= VI &&
1047                 sscreen->b.info.max_se >= 2;
1048
1049         sscreen->has_draw_indirect_multi =
1050                 (sscreen->b.family >= CHIP_POLARIS10) ||
1051                 (sscreen->b.chip_class == VI &&
1052                  sscreen->b.info.pfp_fw_version >= 121 &&
1053                  sscreen->b.info.me_fw_version >= 87) ||
1054                 (sscreen->b.chip_class == CIK &&
1055                  sscreen->b.info.pfp_fw_version >= 211 &&
1056                  sscreen->b.info.me_fw_version >= 173) ||
1057                 (sscreen->b.chip_class == SI &&
1058                  sscreen->b.info.pfp_fw_version >= 79 &&
1059                  sscreen->b.info.me_fw_version >= 142);
1060
1061         sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
1062                                          sscreen->b.info.max_se >= 2 &&
1063                                          !(sscreen->b.debug_flags & DBG_NO_OUT_OF_ORDER);
1064         sscreen->assume_no_z_fights =
1065                 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1066         sscreen->commutative_blend_add =
1067                 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1068         sscreen->clear_db_meta_before_clear =
1069                 driQueryOptionb(config->options, "radeonsi_clear_db_meta_before_clear");
1070         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1071                                             sscreen->b.family <= CHIP_POLARIS12) ||
1072                                            sscreen->b.family == CHIP_VEGA10 ||
1073                                            sscreen->b.family == CHIP_RAVEN;
1074         sscreen->dpbb_allowed = sscreen->b.chip_class >= GFX9 &&
1075                                 !(sscreen->b.debug_flags & DBG_NO_DPBB);
1076         sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1077                                 !(sscreen->b.debug_flags & DBG_NO_DFSM);
1078
1079         /* While it would be nice not to have this flag, we are constrained
1080          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1081          * on GFX9.
1082          */
1083         sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1084
1085         sscreen->b.has_cp_dma = true;
1086         sscreen->b.has_streamout = true;
1087
1088         /* Some chips have RB+ registers, but don't support RB+. Those must
1089          * always disable it.
1090          */
1091         if (sscreen->b.family == CHIP_STONEY ||
1092             sscreen->b.chip_class >= GFX9) {
1093                 sscreen->b.has_rbplus = true;
1094
1095                 sscreen->b.rbplus_allowed =
1096                         !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
1097                         (sscreen->b.family == CHIP_STONEY ||
1098                          sscreen->b.family == CHIP_RAVEN);
1099         }
1100
1101         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1102         sscreen->use_monolithic_shaders =
1103                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
1104
1105         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1106                                             SI_CONTEXT_INV_VMEM_L1;
1107         if (sscreen->b.chip_class <= VI) {
1108                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1109                 sscreen->b.barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1110         }
1111
1112         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1113
1114         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1115                 sscreen->b.debug_flags |= DBG_ALL_SHADERS;
1116
1117         for (i = 0; i < num_compiler_threads; i++)
1118                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1119         for (i = 0; i < num_compiler_threads_lowprio; i++)
1120                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1121
1122         /* Create the auxiliary context. This must be done last. */
1123         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1124
1125         if (sscreen->b.debug_flags & DBG_TEST_DMA)
1126                 si_test_dma(&sscreen->b);
1127
1128         if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
1129                                       DBG_TEST_VMFAULT_SDMA |
1130                                       DBG_TEST_VMFAULT_SHADER))
1131                 si_test_vmfault(sscreen);
1132
1133         return &sscreen->b.b;
1134 }