src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_log.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_suballoc.h"
  34 #include "util/u_tests.h"
  35 #include "util/xmlconfig.h"
  36 #include "vl/vl_decoder.h"
  37 #include "../ddebug/dd_util.h"
  38
  39 #include "compiler/nir/nir.h"
  40
  41 /*
  42  * pipe_context
  43  */
  44 static void si_destroy_context(struct pipe_context *context)
  45 {
  46         struct si_context *sctx = (struct si_context *)context;
  47         int i;
  48
  49         /* Unreference the framebuffer normally to disable related logic
  50          * properly.
  51          */
  52         struct pipe_framebuffer_state fb = {};
  53         if (context->set_framebuffer_state)
  54                 context->set_framebuffer_state(context, &fb);
  55
  56         si_release_all_descriptors(sctx);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_fmask_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  83         if (sctx->custom_blend_eliminate_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87
  88         if (sctx->blitter)
  89                 util_blitter_destroy(sctx->blitter);
  90
  91         si_common_context_cleanup(&sctx->b);
  92
  93         LLVMDisposeTargetMachine(sctx->tm);
  94
  95         si_saved_cs_reference(&sctx->current_saved_cs, NULL);
  96
  97         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
  98         _mesa_hash_table_destroy(sctx->img_handles, NULL);
  99
 100         util_dynarray_fini(&sctx->resident_tex_handles);
 101         util_dynarray_fini(&sctx->resident_img_handles);
 102         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 103         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 104         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 105         FREE(sctx);
 106 }
 107
 108 static enum pipe_reset_status
 109 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 110 {
 111         struct si_context *sctx = (struct si_context *)ctx;
 112
 113         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 114 }
 115
 116 /* Apitrace profiling:
 117  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 118  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 119  *      and remember its number.
 120  *   3) In Mesa, enable queries and performance counters around that draw
 121  *      call and print the results.
 122  *   4) glretrace --benchmark --markers ..
 123  */
 124 static void si_emit_string_marker(struct pipe_context *ctx,
 125                                   const char *string, int len)
 126 {
 127         struct si_context *sctx = (struct si_context *)ctx;
 128
 129         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 130
 131         if (sctx->b.log)
 132                 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
 133 }
 134
 135 static LLVMTargetMachineRef
 136 si_create_llvm_target_machine(struct si_screen *sscreen)
 137 {
 138         const char *triple = "amdgcn--";
 139         char features[256];
 140
 141         snprintf(features, sizeof(features),
 142                  "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
 143                  sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
 144                  sscreen->llvm_has_working_vgpr_indexing ? "" : ",-promote-alloca",
 145                  sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
 146
 147         return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
 148                                        si_get_llvm_processor_name(sscreen->b.family),
 149                                        features,
 150                                        LLVMCodeGenLevelDefault,
 151                                        LLVMRelocDefault,
 152                                        LLVMCodeModelDefault);
 153 }
 154
 155 static void si_set_log_context(struct pipe_context *ctx,
 156                                struct u_log_context *log)
 157 {
 158         struct si_context *sctx = (struct si_context *)ctx;
 159         sctx->b.log = log;
 160
 161         if (log)
 162                 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
 163 }
 164
 165 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 166                                               unsigned flags)
 167 {
 168         struct si_context *sctx = CALLOC_STRUCT(si_context);
 169         struct si_screen* sscreen = (struct si_screen *)screen;
 170         struct radeon_winsys *ws = sscreen->b.ws;
 171         int shader, i;
 172
 173         if (!sctx)
 174                 return NULL;
 175
 176         if (flags & PIPE_CONTEXT_DEBUG)
 177                 sscreen->record_llvm_ir = true; /* racy but not critical */
 178
 179         sctx->b.b.screen = screen; /* this must be set first */
 180         sctx->b.b.priv = NULL;
 181         sctx->b.b.destroy = si_destroy_context;
 182         sctx->b.b.emit_string_marker = si_emit_string_marker;
 183         sctx->b.b.set_log_context = si_set_log_context;
 184         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 185         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 186         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 187
 188         if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
 189                 goto fail;
 190
 191         if (sscreen->b.info.drm_major == 3)
 192                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 193
 194         si_init_blit_functions(sctx);
 195         si_init_compute_functions(sctx);
 196         si_init_cp_dma_functions(sctx);
 197         si_init_debug_functions(sctx);
 198
 199         if (sscreen->b.info.has_hw_decode) {
 200                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 201                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 202         } else {
 203                 sctx->b.b.create_video_codec = vl_create_decoder;
 204                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 205         }
 206
 207         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 208                                        si_context_gfx_flush, sctx);
 209         sctx->b.gfx.flush = si_context_gfx_flush;
 210
 211         /* Border colors. */
 212         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 213                                           sizeof(*sctx->border_color_table));
 214         if (!sctx->border_color_table)
 215                 goto fail;
 216
 217         sctx->border_color_buffer = (struct r600_resource*)
 218                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 219                                    SI_MAX_BORDER_COLORS *
 220                                    sizeof(*sctx->border_color_table));
 221         if (!sctx->border_color_buffer)
 222                 goto fail;
 223
 224         sctx->border_color_map =
 225                 ws->buffer_map(sctx->border_color_buffer->buf,
 226                                NULL, PIPE_TRANSFER_WRITE);
 227         if (!sctx->border_color_map)
 228                 goto fail;
 229
 230         si_init_all_descriptors(sctx);
 231         si_init_state_functions(sctx);
 232         si_init_shader_functions(sctx);
 233         si_init_viewport_functions(sctx);
 234         si_init_ia_multi_vgt_param_table(sctx);
 235
 236         if (sctx->b.chip_class >= CIK)
 237                 cik_init_sdma_functions(sctx);
 238         else
 239                 si_init_dma_functions(sctx);
 240
 241         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 242                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 243
 244         sctx->blitter = util_blitter_create(&sctx->b.b);
 245         if (sctx->blitter == NULL)
 246                 goto fail;
 247         sctx->blitter->draw_rectangle = si_draw_rectangle;
 248
 249         sctx->sample_mask.sample_mask = 0xffff;
 250
 251         /* these must be last */
 252         si_begin_new_cs(sctx);
 253
 254         if (sctx->b.chip_class >= GFX9) {
 255                 sctx->wait_mem_scratch = (struct r600_resource*)
 256                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 257                 if (!sctx->wait_mem_scratch)
 258                         goto fail;
 259
 260                 /* Initialize the memory. */
 261                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 262                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 263                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 264                             S_370_WR_CONFIRM(1) |
 265                             S_370_ENGINE_SEL(V_370_ME));
 266                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 267                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 268                 radeon_emit(cs, sctx->wait_mem_number);
 269         }
 270
 271         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 272          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 273         if (sctx->b.chip_class == CIK) {
 274                 sctx->null_const_buf.buffer =
 275                         si_aligned_buffer_create(screen,
 276                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 277                                                    PIPE_USAGE_DEFAULT, 16,
 278                                                    sctx->screen->b.info.tcc_cache_line_size);
 279                 if (!sctx->null_const_buf.buffer)
 280                         goto fail;
 281                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 282
 283                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 284                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 285                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 286                                                               &sctx->null_const_buf);
 287                         }
 288                 }
 289
 290                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 291                                  &sctx->null_const_buf);
 292                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 293                                  &sctx->null_const_buf);
 294                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 295                                  &sctx->null_const_buf);
 296                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 297                                  &sctx->null_const_buf);
 298                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 299                                  &sctx->null_const_buf);
 300
 301                 /* Clear the NULL constant buffer, because loads should return zeros. */
 302                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 303                                      sctx->null_const_buf.buffer->width0, 0,
 304                                      R600_COHERENCY_SHADER);
 305         }
 306
 307         uint64_t max_threads_per_block;
 308         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 309                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 310                                   &max_threads_per_block);
 311
 312         /* The maximum number of scratch waves. Scratch space isn't divided
 313          * evenly between CUs. The number is only a function of the number of CUs.
 314          * We can decrease the constant to decrease the scratch buffer size.
 315          *
 316          * sctx->scratch_waves must be >= the maximum posible size of
 317          * 1 threadgroup, so that the hw doesn't hang from being unable
 318          * to start any.
 319          *
 320          * The recommended value is 4 per CU at most. Higher numbers don't
 321          * bring much benefit, but they still occupy chip resources (think
 322          * async compute). I've seen ~2% performance difference between 4 and 32.
 323          */
 324         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 325                                    max_threads_per_block / 64);
 326
 327         sctx->tm = si_create_llvm_target_machine(sscreen);
 328
 329         /* Bindless handles. */
 330         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 331                                                     _mesa_key_pointer_equal);
 332         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 333                                                     _mesa_key_pointer_equal);
 334
 335         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 336         util_dynarray_init(&sctx->resident_img_handles, NULL);
 337         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 338         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 339         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 340
 341         return &sctx->b.b;
 342 fail:
 343         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 344         si_destroy_context(&sctx->b.b);
 345         return NULL;
 346 }
 347
 348 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 349                                                    void *priv, unsigned flags)
 350 {
 351         struct si_screen *sscreen = (struct si_screen *)screen;
 352         struct pipe_context *ctx;
 353
 354         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 355                 flags |= PIPE_CONTEXT_DEBUG;
 356
 357         ctx = si_create_context(screen, flags);
 358
 359         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 360                 return ctx;
 361
 362         /* Clover (compute-only) is unsupported.
 363          *
 364          * Since the threaded context creates shader states from the non-driver
 365          * thread, asynchronous compilation is required for create_{shader}_-
 366          * state not to use pipe_context. Debug contexts (ddebug) disable
 367          * asynchronous compilation, so don't use the threaded context with
 368          * those.
 369          */
 370         if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
 371                 return ctx;
 372
 373         /* When shaders are logged to stderr, asynchronous compilation is
 374          * disabled too. */
 375         if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
 376                 return ctx;
 377
 378         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 379                                        si_replace_buffer_storage,
 380                                        &((struct si_context*)ctx)->b.tc);
 381 }
 382
 383 /*
 384  * pipe_screen
 385  */
 386 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 387 {
 388         /* Old kernels disallowed some register writes for SI
 389          * that are used for indirect dispatches. */
 390         return (sscreen->b.chip_class >= CIK ||
 391                 sscreen->b.info.drm_major == 3 ||
 392                 (sscreen->b.info.drm_major == 2 &&
 393                  sscreen->b.info.drm_minor >= 45));
 394 }
 395
 396 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 397 {
 398         struct si_screen *sscreen = (struct si_screen *)pscreen;
 399
 400         switch (param) {
 401         /* Supported features (boolean caps). */
 402         case PIPE_CAP_ACCELERATED:
 403         case PIPE_CAP_TWO_SIDED_STENCIL:
 404         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 405         case PIPE_CAP_ANISOTROPIC_FILTER:
 406         case PIPE_CAP_POINT_SPRITE:
 407         case PIPE_CAP_OCCLUSION_QUERY:
 408         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 409         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 410         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 411         case PIPE_CAP_TEXTURE_SWIZZLE:
 412         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 413         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 414         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 415         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 416         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 417         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 418         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 419         case PIPE_CAP_SM3:
 420         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 421         case PIPE_CAP_PRIMITIVE_RESTART:
 422         case PIPE_CAP_CONDITIONAL_RENDER:
 423         case PIPE_CAP_TEXTURE_BARRIER:
 424         case PIPE_CAP_INDEP_BLEND_ENABLE:
 425         case PIPE_CAP_INDEP_BLEND_FUNC:
 426         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 427         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 428         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 429         case PIPE_CAP_START_INSTANCE:
 430         case PIPE_CAP_NPOT_TEXTURES:
 431         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 432         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 433         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 434         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 435         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 436         case PIPE_CAP_TGSI_INSTANCEID:
 437         case PIPE_CAP_COMPUTE:
 438         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 439         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 440         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 441         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 442         case PIPE_CAP_CUBE_MAP_ARRAY:
 443         case PIPE_CAP_SAMPLE_SHADING:
 444         case PIPE_CAP_DRAW_INDIRECT:
 445         case PIPE_CAP_CLIP_HALFZ:
 446         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 447         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 448         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 449         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 450         case PIPE_CAP_TGSI_TEXCOORD:
 451         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 452         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 453         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 454         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 455         case PIPE_CAP_SHAREABLE_SHADERS:
 456         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 457         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 458         case PIPE_CAP_TEXTURE_QUERY_LOD:
 459         case PIPE_CAP_TEXTURE_GATHER_SM5:
 460         case PIPE_CAP_TGSI_TXQS:
 461         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 462         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 463         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 464         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 465         case PIPE_CAP_INVALIDATE_BUFFER:
 466         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 467         case PIPE_CAP_QUERY_MEMORY_INFO:
 468         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 469         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 470         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 471         case PIPE_CAP_GENERATE_MIPMAP:
 472         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 473         case PIPE_CAP_STRING_MARKER:
 474         case PIPE_CAP_CLEAR_TEXTURE:
 475         case PIPE_CAP_CULL_DISTANCE:
 476         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 477         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 478         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 479         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 480         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 481         case PIPE_CAP_DOUBLES:
 482         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 483         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 484         case PIPE_CAP_BINDLESS_TEXTURE:
 485         case PIPE_CAP_QUERY_TIMESTAMP:
 486         case PIPE_CAP_QUERY_TIME_ELAPSED:
 487         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 488         case PIPE_CAP_QUERY_SO_OVERFLOW:
 489         case PIPE_CAP_MEMOBJ:
 490         case PIPE_CAP_LOAD_CONSTBUF:
 491                 return 1;
 492
 493         case PIPE_CAP_INT64:
 494         case PIPE_CAP_INT64_DIVMOD:
 495         case PIPE_CAP_TGSI_CLOCK:
 496         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 497         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 498                 return 1;
 499
 500         case PIPE_CAP_TGSI_VOTE:
 501                 return HAVE_LLVM >= 0x0400;
 502
 503         case PIPE_CAP_TGSI_BALLOT:
 504                 return HAVE_LLVM >= 0x0500;
 505
 506         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 507                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 508
 509         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 510                 return (sscreen->b.info.drm_major == 2 &&
 511                         sscreen->b.info.drm_minor >= 43) ||
 512                        sscreen->b.info.drm_major == 3;
 513
 514         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 515                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 516                 return sscreen->b.chip_class < CIK ||
 517                        (sscreen->b.info.drm_major == 2 &&
 518                         sscreen->b.info.drm_minor >= 35) ||
 519                        sscreen->b.info.drm_major == 3;
 520
 521         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 522                 return R600_MAP_BUFFER_ALIGNMENT;
 523
 524         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 525         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 526         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 527         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 528         case PIPE_CAP_MAX_VERTEX_STREAMS:
 529         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 530                 return 4;
 531
 532         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 533                 if (sscreen->b.debug_flags & DBG_NIR)
 534                         return 140; /* no geometry and tessellation shaders yet */
 535                 if (si_have_tgsi_compute(sscreen))
 536                         return 450;
 537                 return 420;
 538
 539         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 540                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 541
 542         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 543         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 544         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 545                 /* SI doesn't support unaligned loads.
 546                  * CIK needs DRM 2.50.0 on radeon. */
 547                 return sscreen->b.chip_class == SI ||
 548                        (sscreen->b.info.drm_major == 2 &&
 549                         sscreen->b.info.drm_minor < 50);
 550
 551         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 552                 /* TODO: GFX9 hangs. */
 553                 if (sscreen->b.chip_class >= GFX9)
 554                         return 0;
 555                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 556                  * faults are mitigated in software.
 557                  */
 558                 if (sscreen->b.chip_class >= CIK &&
 559                     sscreen->b.info.drm_major == 3 &&
 560                     sscreen->b.info.drm_minor >= 13)
 561                         return RADEON_SPARSE_PAGE_SIZE;
 562                 return 0;
 563
 564         /* Unsupported features. */
 565         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 566         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 567         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 568         case PIPE_CAP_USER_VERTEX_BUFFERS:
 569         case PIPE_CAP_FAKE_SW_MSAA:
 570         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 571         case PIPE_CAP_VERTEXID_NOBASE:
 572         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 573         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 574         case PIPE_CAP_NATIVE_FENCE_FD:
 575         case PIPE_CAP_TGSI_FS_FBFETCH:
 576         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 577         case PIPE_CAP_UMA:
 578         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 579         case PIPE_CAP_POST_DEPTH_COVERAGE:
 580                 return 0;
 581
 582         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 583                 return si_have_tgsi_compute(sscreen);
 584
 585         case PIPE_CAP_DRAW_PARAMETERS:
 586         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 587         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 588                 return sscreen->has_draw_indirect_multi;
 589
 590         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 591                 return 30;
 592
 593         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 594                 return sscreen->b.chip_class <= VI ?
 595                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 596
 597         /* Stream output. */
 598         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 599         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 600                 return 32*4;
 601
 602         /* Geometry shader output. */
 603         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 604                 return 1024;
 605         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 606                 return 4095;
 607
 608         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 609                 return 2048;
 610
 611         /* Texturing. */
 612         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 613         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 614                 return 15; /* 16384 */
 615         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 616                 /* textures support 8192, but layered rendering supports 2048 */
 617                 return 12;
 618         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 619                 /* textures support 8192, but layered rendering supports 2048 */
 620                 return 2048;
 621
 622         /* Viewports and render targets. */
 623         case PIPE_CAP_MAX_VIEWPORTS:
 624                 return SI_MAX_VIEWPORTS;
 625         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 626         case PIPE_CAP_MAX_RENDER_TARGETS:
 627                 return 8;
 628
 629         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 630         case PIPE_CAP_MIN_TEXEL_OFFSET:
 631                 return -32;
 632
 633         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 634         case PIPE_CAP_MAX_TEXEL_OFFSET:
 635                 return 31;
 636
 637         case PIPE_CAP_ENDIANNESS:
 638                 return PIPE_ENDIAN_LITTLE;
 639
 640         case PIPE_CAP_VENDOR_ID:
 641                 return ATI_VENDOR_ID;
 642         case PIPE_CAP_DEVICE_ID:
 643                 return sscreen->b.info.pci_id;
 644         case PIPE_CAP_VIDEO_MEMORY:
 645                 return sscreen->b.info.vram_size >> 20;
 646         case PIPE_CAP_PCI_GROUP:
 647                 return sscreen->b.info.pci_domain;
 648         case PIPE_CAP_PCI_BUS:
 649                 return sscreen->b.info.pci_bus;
 650         case PIPE_CAP_PCI_DEVICE:
 651                 return sscreen->b.info.pci_dev;
 652         case PIPE_CAP_PCI_FUNCTION:
 653                 return sscreen->b.info.pci_func;
 654         }
 655         return 0;
 656 }
 657
 658 static int si_get_shader_param(struct pipe_screen* pscreen,
 659                                enum pipe_shader_type shader,
 660                                enum pipe_shader_cap param)
 661 {
 662         struct si_screen *sscreen = (struct si_screen *)pscreen;
 663
 664         switch(shader)
 665         {
 666         case PIPE_SHADER_FRAGMENT:
 667         case PIPE_SHADER_VERTEX:
 668         case PIPE_SHADER_GEOMETRY:
 669         case PIPE_SHADER_TESS_CTRL:
 670         case PIPE_SHADER_TESS_EVAL:
 671                 break;
 672         case PIPE_SHADER_COMPUTE:
 673                 switch (param) {
 674                 case PIPE_SHADER_CAP_PREFERRED_IR:
 675                         return PIPE_SHADER_IR_NATIVE;
 676
 677                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 678                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 679
 680                         if (si_have_tgsi_compute(sscreen))
 681                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 682
 683                         return ir;
 684                 }
 685
 686                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 687                         uint64_t max_const_buffer_size;
 688                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 689                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 690                                 &max_const_buffer_size);
 691                         return MIN2(max_const_buffer_size, INT_MAX);
 692                 }
 693                 default:
 694                         /* If compute shaders don't require a special value
 695                          * for this cap, we can return the same value we
 696                          * do for other shader types. */
 697                         break;
 698                 }
 699                 break;
 700         default:
 701                 return 0;
 702         }
 703
 704         switch (param) {
 705         /* Shader limits. */
 706         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 707         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 708         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 709         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 710         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 711                 return 16384;
 712         case PIPE_SHADER_CAP_MAX_INPUTS:
 713                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 714         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 715                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 716         case PIPE_SHADER_CAP_MAX_TEMPS:
 717                 return 256; /* Max native temporaries. */
 718         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 719                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 720         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 721                 return SI_NUM_CONST_BUFFERS;
 722         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 723         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 724                 return SI_NUM_SAMPLERS;
 725         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 726                 return SI_NUM_SHADER_BUFFERS;
 727         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 728                 return SI_NUM_IMAGES;
 729         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 730                 return 32;
 731         case PIPE_SHADER_CAP_PREFERRED_IR:
 732                 if (sscreen->b.debug_flags & DBG_NIR &&
 733                     (shader == PIPE_SHADER_VERTEX ||
 734                      shader == PIPE_SHADER_FRAGMENT))
 735                         return PIPE_SHADER_IR_NIR;
 736                 return PIPE_SHADER_IR_TGSI;
 737         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 738                 return 4;
 739
 740         /* Supported boolean features. */
 741         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 742         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 743         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 744         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 745         case PIPE_SHADER_CAP_INTEGERS:
 746         case PIPE_SHADER_CAP_INT64_ATOMICS:
 747         case PIPE_SHADER_CAP_FP16:
 748         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 749         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 750         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 751         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 752         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 753         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 754                 return 1;
 755
 756         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 757                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 758                 return shader != PIPE_SHADER_GEOMETRY &&
 759                        (sscreen->llvm_has_working_vgpr_indexing ||
 760                         /* TCS and TES load inputs directly from LDS or
 761                          * offchip memory, so indirect indexing is trivial. */
 762                         shader == PIPE_SHADER_TESS_CTRL ||
 763                         shader == PIPE_SHADER_TESS_EVAL);
 764
 765         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 766                 return sscreen->llvm_has_working_vgpr_indexing ||
 767                        /* TCS stores outputs directly to memory. */
 768                        shader == PIPE_SHADER_TESS_CTRL;
 769
 770         /* Unsupported boolean features. */
 771         case PIPE_SHADER_CAP_SUBROUTINES:
 772         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 773                 return 0;
 774         }
 775         return 0;
 776 }
 777
 778 static const struct nir_shader_compiler_options nir_options = {
 779         .vertex_id_zero_based = true,
 780         .lower_scmp = true,
 781         .lower_flrp32 = true,
 782         .lower_fsat = true,
 783         .lower_fdiv = true,
 784         .lower_sub = true,
 785         .lower_pack_snorm_2x16 = true,
 786         .lower_pack_snorm_4x8 = true,
 787         .lower_pack_unorm_2x16 = true,
 788         .lower_pack_unorm_4x8 = true,
 789         .lower_unpack_snorm_2x16 = true,
 790         .lower_unpack_snorm_4x8 = true,
 791         .lower_unpack_unorm_2x16 = true,
 792         .lower_unpack_unorm_4x8 = true,
 793         .lower_extract_byte = true,
 794         .lower_extract_word = true,
 795         .max_unroll_iterations = 32,
 796         .native_integers = true,
 797 };
 798
 799 static const void *
 800 si_get_compiler_options(struct pipe_screen *screen,
 801                         enum pipe_shader_ir ir,
 802                         enum pipe_shader_type shader)
 803 {
 804         assert(ir == PIPE_SHADER_IR_NIR);
 805         return &nir_options;
 806 }
 807
 808 static void si_destroy_screen(struct pipe_screen* pscreen)
 809 {
 810         struct si_screen *sscreen = (struct si_screen *)pscreen;
 811         struct si_shader_part *parts[] = {
 812                 sscreen->vs_prologs,
 813                 sscreen->tcs_epilogs,
 814                 sscreen->gs_prologs,
 815                 sscreen->ps_prologs,
 816                 sscreen->ps_epilogs
 817         };
 818         unsigned i;
 819
 820         if (!sscreen->b.ws->unref(sscreen->b.ws))
 821                 return;
 822
 823         util_queue_destroy(&sscreen->shader_compiler_queue);
 824         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 825
 826         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 827                 if (sscreen->tm[i])
 828                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 829
 830         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 831                 if (sscreen->tm_low_priority[i])
 832                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 833
 834         /* Free shader parts. */
 835         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 836                 while (parts[i]) {
 837                         struct si_shader_part *part = parts[i];
 838
 839                         parts[i] = part->next;
 840                         si_radeon_shader_binary_clean(&part->binary);
 841                         FREE(part);
 842                 }
 843         }
 844         mtx_destroy(&sscreen->shader_parts_mutex);
 845         si_destroy_shader_cache(sscreen);
 846         si_destroy_common_screen(&sscreen->b);
 847 }
 848
 849 static bool si_init_gs_info(struct si_screen *sscreen)
 850 {
 851         switch (sscreen->b.family) {
 852         case CHIP_OLAND:
 853         case CHIP_HAINAN:
 854         case CHIP_KAVERI:
 855         case CHIP_KABINI:
 856         case CHIP_MULLINS:
 857         case CHIP_ICELAND:
 858         case CHIP_CARRIZO:
 859         case CHIP_STONEY:
 860                 sscreen->gs_table_depth = 16;
 861                 return true;
 862         case CHIP_TAHITI:
 863         case CHIP_PITCAIRN:
 864         case CHIP_VERDE:
 865         case CHIP_BONAIRE:
 866         case CHIP_HAWAII:
 867         case CHIP_TONGA:
 868         case CHIP_FIJI:
 869         case CHIP_POLARIS10:
 870         case CHIP_POLARIS11:
 871         case CHIP_POLARIS12:
 872         case CHIP_VEGA10:
 873         case CHIP_RAVEN:
 874                 sscreen->gs_table_depth = 32;
 875                 return true;
 876         default:
 877                 return false;
 878         }
 879 }
 880
 881 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 882 {
 883         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 884         unsigned i;
 885
 886         if (!family)
 887                 return;
 888
 889         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 890                 if (!strcmp(family, si_get_llvm_processor_name(i))) {
 891                         /* Override family and chip_class. */
 892                         sscreen->b.family = sscreen->b.info.family = i;
 893
 894                         if (i >= CHIP_VEGA10)
 895                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 896                         else if (i >= CHIP_TONGA)
 897                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 898                         else if (i >= CHIP_BONAIRE)
 899                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 900                         else
 901                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 902
 903                         /* Don't submit any IBs. */
 904                         setenv("RADEON_NOOP", "1", 1);
 905                         return;
 906                 }
 907         }
 908
 909         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 910         exit(1);
 911 }
 912
 913 static void si_test_vmfault(struct si_screen *sscreen)
 914 {
 915         struct pipe_context *ctx = sscreen->b.aux_context;
 916         struct si_context *sctx = (struct si_context *)ctx;
 917         struct pipe_resource *buf =
 918                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 919
 920         if (!buf) {
 921                 puts("Buffer allocation failed.");
 922                 exit(1);
 923         }
 924
 925         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 926
 927         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
 928                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 929                 ctx->flush(ctx, NULL, 0);
 930                 puts("VM fault test: CP - done.");
 931         }
 932         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
 933                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 934                 ctx->flush(ctx, NULL, 0);
 935                 puts("VM fault test: SDMA - done.");
 936         }
 937         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
 938                 util_test_constant_buffer(ctx, buf);
 939                 puts("VM fault test: Shader - done.");
 940         }
 941         exit(0);
 942 }
 943
 944 static void radeonsi_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 945 {
 946         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 947 }
 948
 949 static void radeonsi_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 950 {
 951         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 952
 953         ac_compute_device_uuid(&rscreen->info, uuid, PIPE_UUID_SIZE);
 954 }
 955
 956 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 957                                            const struct pipe_screen_config *config)
 958 {
 959         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 960         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 961
 962         if (!sscreen) {
 963                 return NULL;
 964         }
 965
 966         /* Set functions first. */
 967         sscreen->b.b.context_create = si_pipe_create_context;
 968         sscreen->b.b.destroy = si_destroy_screen;
 969         sscreen->b.b.get_param = si_get_param;
 970         sscreen->b.b.get_shader_param = si_get_shader_param;
 971         sscreen->b.b.get_compiler_options = si_get_compiler_options;
 972         sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
 973         sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
 974         sscreen->b.b.resource_create = si_resource_create_common;
 975
 976         si_init_screen_state_functions(sscreen);
 977
 978         /* Set these flags in debug_flags early, so that the shader cache takes
 979          * them into account.
 980          */
 981         if (driQueryOptionb(config->options,
 982                             "glsl_correct_derivatives_after_discard"))
 983                 sscreen->b.debug_flags |= DBG_FS_CORRECT_DERIVS_AFTER_KILL;
 984         if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
 985                 sscreen->b.debug_flags |= DBG_SI_SCHED;
 986
 987         if (!si_common_screen_init(&sscreen->b, ws) ||
 988             !si_init_gs_info(sscreen) ||
 989             !si_init_shader_cache(sscreen)) {
 990                 FREE(sscreen);
 991                 return NULL;
 992         }
 993
 994         /* Only enable as many threads as we have target machines, but at most
 995          * the number of CPUs - 1 if there is more than one.
 996          */
 997         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
 998         num_threads = MAX2(1, num_threads - 1);
 999         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1000         num_compiler_threads_lowprio =
1001                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1002
1003         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1004                              32, num_compiler_threads,
1005                              UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1006                 si_destroy_shader_cache(sscreen);
1007                 FREE(sscreen);
1008                 return NULL;
1009         }
1010
1011         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1012                              "si_shader_low",
1013                              32, num_compiler_threads_lowprio,
1014                              UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1015                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1016                si_destroy_shader_cache(sscreen);
1017                FREE(sscreen);
1018                return NULL;
1019         }
1020
1021         si_handle_env_var_force_family(sscreen);
1022
1023         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1024                 si_init_perfcounters(sscreen);
1025
1026         /* Hawaii has a bug with offchip buffers > 256 that can be worked
1027          * around by setting 4K granularity.
1028          */
1029         sscreen->tess_offchip_block_dw_size =
1030                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1031
1032         /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1033          * on SI. */
1034         sscreen->has_clear_state = sscreen->b.chip_class >= CIK;
1035
1036         sscreen->has_distributed_tess =
1037                 sscreen->b.chip_class >= VI &&
1038                 sscreen->b.info.max_se >= 2;
1039
1040         sscreen->has_draw_indirect_multi =
1041                 (sscreen->b.family >= CHIP_POLARIS10) ||
1042                 (sscreen->b.chip_class == VI &&
1043                  sscreen->b.info.pfp_fw_version >= 121 &&
1044                  sscreen->b.info.me_fw_version >= 87) ||
1045                 (sscreen->b.chip_class == CIK &&
1046                  sscreen->b.info.pfp_fw_version >= 211 &&
1047                  sscreen->b.info.me_fw_version >= 173) ||
1048                 (sscreen->b.chip_class == SI &&
1049                  sscreen->b.info.pfp_fw_version >= 79 &&
1050                  sscreen->b.info.me_fw_version >= 142);
1051
1052         sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
1053                                          sscreen->b.info.max_se >= 2 &&
1054                                          !(sscreen->b.debug_flags & DBG_NO_OUT_OF_ORDER);
1055         sscreen->assume_no_z_fights =
1056                 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1057         sscreen->commutative_blend_add =
1058                 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1059         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1060                                             sscreen->b.family <= CHIP_POLARIS12) ||
1061                                            sscreen->b.family == CHIP_VEGA10 ||
1062                                            sscreen->b.family == CHIP_RAVEN;
1063         sscreen->dpbb_allowed = sscreen->b.chip_class >= GFX9 &&
1064                                 !(sscreen->b.debug_flags & DBG_NO_DPBB);
1065         sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1066                                 !(sscreen->b.debug_flags & DBG_NO_DFSM);
1067
1068         /* While it would be nice not to have this flag, we are constrained
1069          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1070          * on GFX9.
1071          */
1072         sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1073
1074         sscreen->b.has_cp_dma = true;
1075         sscreen->b.has_streamout = true;
1076
1077         /* Some chips have RB+ registers, but don't support RB+. Those must
1078          * always disable it.
1079          */
1080         if (sscreen->b.family == CHIP_STONEY ||
1081             sscreen->b.chip_class >= GFX9) {
1082                 sscreen->b.has_rbplus = true;
1083
1084                 sscreen->b.rbplus_allowed =
1085                         !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
1086                         (sscreen->b.family == CHIP_STONEY ||
1087                          sscreen->b.family == CHIP_RAVEN);
1088         }
1089
1090         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1091         sscreen->use_monolithic_shaders =
1092                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
1093
1094         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1095                                             SI_CONTEXT_INV_VMEM_L1;
1096         if (sscreen->b.chip_class <= VI) {
1097                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1098                 sscreen->b.barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1099         }
1100
1101         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1102
1103         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1104                 sscreen->b.debug_flags |= DBG_ALL_SHADERS;
1105
1106         for (i = 0; i < num_compiler_threads; i++)
1107                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1108         for (i = 0; i < num_compiler_threads_lowprio; i++)
1109                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1110
1111         /* Create the auxiliary context. This must be done last. */
1112         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1113
1114         if (sscreen->b.debug_flags & DBG_TEST_DMA)
1115                 si_test_dma(&sscreen->b);
1116
1117         if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
1118                                       DBG_TEST_VMFAULT_SDMA |
1119                                       DBG_TEST_VMFAULT_SHADER))
1120                 si_test_vmfault(sscreen);
1121
1122         return &sscreen->b.b;
1123 }