src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_transfer.h"
  35 #include "util/u_surface.h"
  36 #include "util/u_pack_color.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_inlines.h"
  39 #include "util/u_simple_shaders.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "si_pipe.h"
  46 #include "radeon/radeon_uvd.h"
  47 #include "sid.h"
  48 #include "si_resource.h"
  49 #include "si_pipe.h"
  50 #include "si_state.h"
  51 #include "../radeon/r600_cs.h"
  52
  53 /*
  54  * pipe_context
  55  */
  56 void si_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
  57               unsigned flags)
  58 {
  59         struct si_context *sctx = (struct si_context *)ctx;
  60         struct pipe_query *render_cond = NULL;
  61         boolean render_cond_cond = FALSE;
  62         unsigned render_cond_mode = 0;
  63
  64         if (fence) {
  65                 *fence = sctx->b.ws->cs_create_fence(sctx->b.rings.gfx.cs);
  66         }
  67
  68         /* Disable render condition. */
  69         if (sctx->b.current_render_cond) {
  70                 render_cond = sctx->b.current_render_cond;
  71                 render_cond_cond = sctx->b.current_render_cond_cond;
  72                 render_cond_mode = sctx->b.current_render_cond_mode;
  73                 ctx->render_condition(ctx, NULL, FALSE, 0);
  74         }
  75
  76         si_context_flush(sctx, flags);
  77
  78         /* Re-enable render condition. */
  79         if (render_cond) {
  80                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  81         }
  82 }
  83
  84 static void si_flush_from_st(struct pipe_context *ctx,
  85                              struct pipe_fence_handle **fence,
  86                              unsigned flags)
  87 {
  88         si_flush(ctx, fence,
  89                  flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
  90 }
  91
  92 static void si_flush_from_winsys(void *ctx, unsigned flags)
  93 {
  94         si_flush((struct pipe_context*)ctx, NULL, flags);
  95 }
  96
  97 static void si_destroy_context(struct pipe_context *context)
  98 {
  99         struct si_context *sctx = (struct si_context *)context;
 100
 101         si_release_all_descriptors(sctx);
 102
 103         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
 104         r600_resource_reference(&sctx->border_color_table, NULL);
 105
 106         if (sctx->dummy_pixel_shader) {
 107                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 108         }
 109         for (int i = 0; i < 8; i++) {
 110                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
 111                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
 112                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
 113         }
 114         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
 115         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
 116         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
 117         util_unreference_framebuffer_state(&sctx->framebuffer);
 118
 119         util_blitter_destroy(sctx->blitter);
 120
 121         r600_common_context_cleanup(&sctx->b);
 122         FREE(sctx);
 123 }
 124
 125 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
 126 {
 127         struct si_context *sctx = CALLOC_STRUCT(si_context);
 128         struct si_screen* sscreen = (struct si_screen *)screen;
 129         int shader, i;
 130
 131         if (sctx == NULL)
 132                 return NULL;
 133
 134         sctx->b.b.screen = screen; /* this must be set first */
 135         sctx->b.b.priv = priv;
 136         sctx->b.b.destroy = si_destroy_context;
 137         sctx->b.b.flush = si_flush_from_st;
 138         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 139
 140         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 141                 goto fail;
 142
 143         si_init_blit_functions(sctx);
 144         si_init_compute_functions(sctx);
 145
 146         if (sscreen->b.info.has_uvd) {
 147                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 148                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 149         } else {
 150                 sctx->b.b.create_video_codec = vl_create_decoder;
 151                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 152         }
 153
 154         sctx->b.rings.gfx.cs = sctx->b.ws->cs_create(sctx->b.ws, RING_GFX, NULL);
 155         sctx->b.rings.gfx.flush = si_flush_from_winsys;
 156
 157         si_init_all_descriptors(sctx);
 158
 159         /* Initialize cache_flush. */
 160         sctx->cache_flush = si_atom_cache_flush;
 161         sctx->atoms.cache_flush = &sctx->cache_flush;
 162
 163         sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
 164
 165         switch (sctx->b.chip_class) {
 166         case SI:
 167         case CIK:
 168                 si_init_state_functions(sctx);
 169                 si_init_config(sctx);
 170                 break;
 171         default:
 172                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 173                 goto fail;
 174         }
 175
 176         sctx->b.ws->cs_set_flush_callback(sctx->b.rings.gfx.cs, si_flush_from_winsys, sctx);
 177
 178         sctx->blitter = util_blitter_create(&sctx->b.b);
 179         if (sctx->blitter == NULL)
 180                 goto fail;
 181
 182         sctx->dummy_pixel_shader =
 183                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 184                                                      TGSI_SEMANTIC_GENERIC,
 185                                                      TGSI_INTERPOLATE_CONSTANT);
 186         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 187
 188         /* these must be last */
 189         si_begin_new_cs(sctx);
 190         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 191
 192         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 193          * with a NULL buffer). We need to use a dummy buffer instead. */
 194         if (sctx->b.chip_class == CIK) {
 195                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 196                                                                  PIPE_USAGE_STATIC, 16);
 197                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 198
 199                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 200                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 201                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 202                                                               &sctx->null_const_buf);
 203                         }
 204                 }
 205
 206                 /* Clear the NULL constant buffer, because loads should return zeros. */
 207                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 208                                      sctx->null_const_buf.buffer->width0, 0);
 209         }
 210
 211         return &sctx->b.b;
 212 fail:
 213         si_destroy_context(&sctx->b.b);
 214         return NULL;
 215 }
 216
 217 /*
 218  * pipe_screen
 219  */
 220
 221 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 222 {
 223         struct si_screen *sscreen = (struct si_screen *)pscreen;
 224
 225         switch (param) {
 226         /* Supported features (boolean caps). */
 227         case PIPE_CAP_TWO_SIDED_STENCIL:
 228         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 229         case PIPE_CAP_ANISOTROPIC_FILTER:
 230         case PIPE_CAP_POINT_SPRITE:
 231         case PIPE_CAP_OCCLUSION_QUERY:
 232         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 233         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 234         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 235         case PIPE_CAP_TEXTURE_SWIZZLE:
 236         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 237         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 238         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 239         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 240         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 241         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 242         case PIPE_CAP_SM3:
 243         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 244         case PIPE_CAP_PRIMITIVE_RESTART:
 245         case PIPE_CAP_CONDITIONAL_RENDER:
 246         case PIPE_CAP_TEXTURE_BARRIER:
 247         case PIPE_CAP_INDEP_BLEND_ENABLE:
 248         case PIPE_CAP_INDEP_BLEND_FUNC:
 249         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 250         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 251         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 252         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 253         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 254         case PIPE_CAP_USER_INDEX_BUFFERS:
 255         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 256         case PIPE_CAP_START_INSTANCE:
 257         case PIPE_CAP_NPOT_TEXTURES:
 258         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 259         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 260         case PIPE_CAP_TGSI_INSTANCEID:
 261         case PIPE_CAP_COMPUTE:
 262         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 263         case PIPE_CAP_TGSI_VS_LAYER:
 264         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 265                 return 1;
 266
 267         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 268                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 269                 return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
 270                                                sscreen->b.info.drm_minor >= 35);
 271
 272         case PIPE_CAP_TGSI_TEXCOORD:
 273                 return 0;
 274
 275         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 276                 return 64;
 277
 278         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 279                 return 256;
 280
 281         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 282                 return 140;
 283
 284         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 285                 return 1;
 286         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 287                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 288
 289         /* Unsupported features. */
 290         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 291         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 292         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 293         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 294         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 295         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 296         case PIPE_CAP_USER_VERTEX_BUFFERS:
 297         case PIPE_CAP_CUBE_MAP_ARRAY:
 298                 return 0;
 299
 300         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 301                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 302
 303         /* Stream output. */
 304         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 305                 return sscreen->b.has_streamout ? 4 : 0;
 306         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 307                 return sscreen->b.has_streamout ? 1 : 0;
 308         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 309         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 310                 return sscreen->b.has_streamout ? 32*4 : 0;
 311
 312         /* Texturing. */
 313         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 314         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 315         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 316                         return 15;
 317         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 318                 return 16384;
 319         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 320                 return 32;
 321
 322         /* Render targets. */
 323         case PIPE_CAP_MAX_RENDER_TARGETS:
 324                 return 8;
 325
 326         case PIPE_CAP_MAX_VIEWPORTS:
 327                 return 1;
 328
 329         /* Timer queries, present when the clock frequency is non zero. */
 330         case PIPE_CAP_QUERY_TIMESTAMP:
 331         case PIPE_CAP_QUERY_TIME_ELAPSED:
 332                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 333
 334         case PIPE_CAP_MIN_TEXEL_OFFSET:
 335                 return -8;
 336
 337         case PIPE_CAP_MAX_TEXEL_OFFSET:
 338                 return 7;
 339         case PIPE_CAP_ENDIANNESS:
 340                 return PIPE_ENDIAN_LITTLE;
 341         }
 342         return 0;
 343 }
 344
 345 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 346 {
 347         switch(shader)
 348         {
 349         case PIPE_SHADER_FRAGMENT:
 350         case PIPE_SHADER_VERTEX:
 351                 break;
 352         case PIPE_SHADER_GEOMETRY:
 353                 /* TODO: support and enable geometry programs */
 354                 return 0;
 355         case PIPE_SHADER_COMPUTE:
 356                 switch (param) {
 357                 case PIPE_SHADER_CAP_PREFERRED_IR:
 358                         return PIPE_SHADER_IR_LLVM;
 359                 default:
 360                         return 0;
 361                 }
 362         default:
 363                 /* TODO: support tessellation */
 364                 return 0;
 365         }
 366
 367         switch (param) {
 368         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 369         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 370         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 371         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 372                 return 16384;
 373         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 374                 return 32;
 375         case PIPE_SHADER_CAP_MAX_INPUTS:
 376                 return 32;
 377         case PIPE_SHADER_CAP_MAX_TEMPS:
 378                 return 256; /* Max native temporaries. */
 379         case PIPE_SHADER_CAP_MAX_ADDRS:
 380                 /* FIXME Isn't this equal to TEMPS? */
 381                 return 1; /* Max native address registers */
 382         case PIPE_SHADER_CAP_MAX_CONSTS:
 383                 return 4096; /* actually only memory limits this */
 384         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 385                 return NUM_PIPE_CONST_BUFFERS;
 386         case PIPE_SHADER_CAP_MAX_PREDS:
 387                 return 0; /* FIXME */
 388         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 389                 return 1;
 390         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 391                 return 0;
 392         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 393         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 394         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 395         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 396                 return 1;
 397         case PIPE_SHADER_CAP_INTEGERS:
 398                 return 1;
 399         case PIPE_SHADER_CAP_SUBROUTINES:
 400                 return 0;
 401         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 402         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 403                 return 16;
 404         case PIPE_SHADER_CAP_PREFERRED_IR:
 405                 return PIPE_SHADER_IR_TGSI;
 406         }
 407         return 0;
 408 }
 409
 410 static void si_destroy_screen(struct pipe_screen* pscreen)
 411 {
 412         struct si_screen *sscreen = (struct si_screen *)pscreen;
 413
 414         if (sscreen == NULL)
 415                 return;
 416
 417         if (!radeon_winsys_unref(sscreen->b.ws))
 418                 return;
 419
 420         r600_destroy_common_screen(&sscreen->b);
 421 }
 422
 423 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 424 {
 425         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 426         if (sscreen == NULL) {
 427                 return NULL;
 428         }
 429
 430         /* Set functions first. */
 431         sscreen->b.b.context_create = si_create_context;
 432         sscreen->b.b.destroy = si_destroy_screen;
 433         sscreen->b.b.get_param = si_get_param;
 434         sscreen->b.b.get_shader_param = si_get_shader_param;
 435         sscreen->b.b.is_format_supported = si_is_format_supported;
 436
 437         if (!r600_common_screen_init(&sscreen->b, ws)) {
 438                 FREE(sscreen);
 439                 return NULL;
 440         }
 441
 442         sscreen->b.has_cp_dma = true;
 443         sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 444
 445         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 446                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 447
 448         /* Create the auxiliary context. This must be done last. */
 449         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 450
 451         return &sscreen->b.b;
 452 }