src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "vl/vl_decoder.h"
  34 #include "../ddebug/dd_util.h"
  35
  36 #define SI_LLVM_DEFAULT_FEATURES \
  37         "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals"
  38
  39 /*
  40  * pipe_context
  41  */
  42 static void si_destroy_context(struct pipe_context *context)
  43 {
  44         struct si_context *sctx = (struct si_context *)context;
  45         int i;
  46
  47         /* Unreference the framebuffer normally to disable related logic
  48          * properly.
  49          */
  50         struct pipe_framebuffer_state fb = {};
  51         context->set_framebuffer_state(context, &fb);
  52
  53         si_release_all_descriptors(sctx);
  54
  55         if (sctx->ce_suballocator)
  56                 u_suballocator_destroy(sctx->ce_suballocator);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  83         if (sctx->custom_blend_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87
  88         if (sctx->blitter)
  89                 util_blitter_destroy(sctx->blitter);
  90
  91         r600_common_context_cleanup(&sctx->b);
  92
  93         LLVMDisposeTargetMachine(sctx->tm);
  94
  95         r600_resource_reference(&sctx->trace_buf, NULL);
  96         r600_resource_reference(&sctx->last_trace_buf, NULL);
  97         radeon_clear_saved_cs(&sctx->last_gfx);
  98
  99         FREE(sctx);
 100 }
 101
 102 static enum pipe_reset_status
 103 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 104 {
 105         struct si_context *sctx = (struct si_context *)ctx;
 106
 107         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 108 }
 109
 110 /* Apitrace profiling:
 111  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 112  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 113  *      and remember its number.
 114  *   3) In Mesa, enable queries and performance counters around that draw
 115  *      call and print the results.
 116  *   4) glretrace --benchmark --markers ..
 117  */
 118 static void si_emit_string_marker(struct pipe_context *ctx,
 119                                   const char *string, int len)
 120 {
 121         struct si_context *sctx = (struct si_context *)ctx;
 122
 123         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 124 }
 125
 126 static LLVMTargetMachineRef
 127 si_create_llvm_target_machine(struct si_screen *sscreen)
 128 {
 129         const char *triple = "amdgcn--";
 130
 131         return LLVMCreateTargetMachine(radeon_llvm_get_r600_target(triple), triple,
 132                                        r600_get_llvm_processor_name(sscreen->b.family),
 133 #if HAVE_LLVM >= 0x0308
 134                                        sscreen->b.debug_flags & DBG_SI_SCHED ?
 135                                                SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
 136 #endif
 137                                                SI_LLVM_DEFAULT_FEATURES,
 138                                        LLVMCodeGenLevelDefault,
 139                                        LLVMRelocDefault,
 140                                        LLVMCodeModelDefault);
 141 }
 142
 143 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 144                                               void *priv, unsigned flags)
 145 {
 146         struct si_context *sctx = CALLOC_STRUCT(si_context);
 147         struct si_screen* sscreen = (struct si_screen *)screen;
 148         struct radeon_winsys *ws = sscreen->b.ws;
 149         int shader, i;
 150
 151         if (!sctx)
 152                 return NULL;
 153
 154         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 155                 flags |= PIPE_CONTEXT_DEBUG;
 156
 157         if (flags & PIPE_CONTEXT_DEBUG)
 158                 sscreen->record_llvm_ir = true; /* racy but not critical */
 159
 160         sctx->b.b.screen = screen; /* this must be set first */
 161         sctx->b.b.priv = priv;
 162         sctx->b.b.destroy = si_destroy_context;
 163         sctx->b.b.emit_string_marker = si_emit_string_marker;
 164         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 165         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 166         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 167
 168         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 169                 goto fail;
 170
 171         if (sscreen->b.info.drm_major == 3)
 172                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 173
 174         si_init_blit_functions(sctx);
 175         si_init_compute_functions(sctx);
 176         si_init_cp_dma_functions(sctx);
 177         si_init_debug_functions(sctx);
 178
 179         if (sscreen->b.info.has_uvd) {
 180                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 181                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 182         } else {
 183                 sctx->b.b.create_video_codec = vl_create_decoder;
 184                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 185         }
 186
 187         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 188                                        si_context_gfx_flush, sctx);
 189
 190         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
 191                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 192                 if (!sctx->ce_ib)
 193                         goto fail;
 194
 195                 if (ws->cs_add_const_preamble_ib) {
 196                         sctx->ce_preamble_ib =
 197                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 198
 199                         if (!sctx->ce_preamble_ib)
 200                                 goto fail;
 201                 }
 202
 203                 sctx->ce_suballocator =
 204                                 u_suballocator_create(&sctx->b.b, 1024 * 1024,
 205                                                       PIPE_BIND_CUSTOM,
 206                                                       PIPE_USAGE_DEFAULT, false);
 207                 if (!sctx->ce_suballocator)
 208                         goto fail;
 209         }
 210
 211         sctx->b.gfx.flush = si_context_gfx_flush;
 212
 213         /* Border colors. */
 214         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 215                                           sizeof(*sctx->border_color_table));
 216         if (!sctx->border_color_table)
 217                 goto fail;
 218
 219         sctx->border_color_buffer = (struct r600_resource*)
 220                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 221                                    SI_MAX_BORDER_COLORS *
 222                                    sizeof(*sctx->border_color_table));
 223         if (!sctx->border_color_buffer)
 224                 goto fail;
 225
 226         sctx->border_color_map =
 227                 ws->buffer_map(sctx->border_color_buffer->buf,
 228                                NULL, PIPE_TRANSFER_WRITE);
 229         if (!sctx->border_color_map)
 230                 goto fail;
 231
 232         si_init_all_descriptors(sctx);
 233         si_init_state_functions(sctx);
 234         si_init_shader_functions(sctx);
 235
 236         if (sctx->b.chip_class >= CIK)
 237                 cik_init_sdma_functions(sctx);
 238         else
 239                 si_init_dma_functions(sctx);
 240
 241         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 242                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 243
 244         sctx->blitter = util_blitter_create(&sctx->b.b);
 245         if (sctx->blitter == NULL)
 246                 goto fail;
 247         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 248
 249         sctx->sample_mask.sample_mask = 0xffff;
 250
 251         /* these must be last */
 252         si_begin_new_cs(sctx);
 253         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 254
 255         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 256          * with a NULL buffer). We need to use a dummy buffer instead. */
 257         if (sctx->b.chip_class == CIK) {
 258                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 259                                                                  PIPE_USAGE_DEFAULT, 16);
 260                 if (!sctx->null_const_buf.buffer)
 261                         goto fail;
 262                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 263
 264                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 265                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 266                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 267                                                               &sctx->null_const_buf);
 268                         }
 269                 }
 270
 271                 /* Clear the NULL constant buffer, because loads should return zeros. */
 272                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 273                                      sctx->null_const_buf.buffer->width0, 0,
 274                                      R600_COHERENCY_SHADER);
 275         }
 276
 277         uint64_t max_threads_per_block;
 278         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 279                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 280                                   &max_threads_per_block);
 281
 282         /* The maximum number of scratch waves. Scratch space isn't divided
 283          * evenly between CUs. The number is only a function of the number of CUs.
 284          * We can decrease the constant to decrease the scratch buffer size.
 285          *
 286          * sctx->scratch_waves must be >= the maximum posible size of
 287          * 1 threadgroup, so that the hw doesn't hang from being unable
 288          * to start any.
 289          *
 290          * The recommended value is 4 per CU at most. Higher numbers don't
 291          * bring much benefit, but they still occupy chip resources (think
 292          * async compute). I've seen ~2% performance difference between 4 and 32.
 293          */
 294         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 295                                    max_threads_per_block / 64);
 296
 297         sctx->tm = si_create_llvm_target_machine(sscreen);
 298
 299         return &sctx->b.b;
 300 fail:
 301         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 302         si_destroy_context(&sctx->b.b);
 303         return NULL;
 304 }
 305
 306 /*
 307  * pipe_screen
 308  */
 309
 310 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 311 {
 312         struct si_screen *sscreen = (struct si_screen *)pscreen;
 313
 314         switch (param) {
 315         /* Supported features (boolean caps). */
 316         case PIPE_CAP_TWO_SIDED_STENCIL:
 317         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 318         case PIPE_CAP_ANISOTROPIC_FILTER:
 319         case PIPE_CAP_POINT_SPRITE:
 320         case PIPE_CAP_OCCLUSION_QUERY:
 321         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 322         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 323         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 324         case PIPE_CAP_TEXTURE_SWIZZLE:
 325         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 326         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 327         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 328         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 329         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 330         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 331         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 332         case PIPE_CAP_SM3:
 333         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 334         case PIPE_CAP_PRIMITIVE_RESTART:
 335         case PIPE_CAP_CONDITIONAL_RENDER:
 336         case PIPE_CAP_TEXTURE_BARRIER:
 337         case PIPE_CAP_INDEP_BLEND_ENABLE:
 338         case PIPE_CAP_INDEP_BLEND_FUNC:
 339         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 340         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 341         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 342         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 343         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 344         case PIPE_CAP_USER_INDEX_BUFFERS:
 345         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 346         case PIPE_CAP_START_INSTANCE:
 347         case PIPE_CAP_NPOT_TEXTURES:
 348         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 349         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 350         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 351         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 352         case PIPE_CAP_TGSI_INSTANCEID:
 353         case PIPE_CAP_COMPUTE:
 354         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 355         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 356         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 357         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 358         case PIPE_CAP_CUBE_MAP_ARRAY:
 359         case PIPE_CAP_SAMPLE_SHADING:
 360         case PIPE_CAP_DRAW_INDIRECT:
 361         case PIPE_CAP_CLIP_HALFZ:
 362         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 363         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 364         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 365         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 366         case PIPE_CAP_TGSI_TEXCOORD:
 367         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 368         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 369         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 370         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 371         case PIPE_CAP_SHAREABLE_SHADERS:
 372         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 373         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 374         case PIPE_CAP_TEXTURE_QUERY_LOD:
 375         case PIPE_CAP_TEXTURE_GATHER_SM5:
 376         case PIPE_CAP_TGSI_TXQS:
 377         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 378         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 379         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 380         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 381         case PIPE_CAP_INVALIDATE_BUFFER:
 382         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 383         case PIPE_CAP_QUERY_MEMORY_INFO:
 384         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 385         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 386         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 387         case PIPE_CAP_GENERATE_MIPMAP:
 388         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 389         case PIPE_CAP_STRING_MARKER:
 390                 return 1;
 391
 392         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 393                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 394
 395         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 396                 return (sscreen->b.info.drm_major == 2 &&
 397                         sscreen->b.info.drm_minor >= 43) ||
 398                        sscreen->b.info.drm_major == 3;
 399
 400         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 401                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 402                 return sscreen->b.chip_class < CIK ||
 403                        (sscreen->b.info.drm_major == 2 &&
 404                         sscreen->b.info.drm_minor >= 35) ||
 405                        sscreen->b.info.drm_major == 3;
 406
 407         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 408                 return R600_MAP_BUFFER_ALIGNMENT;
 409
 410         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 411         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 412         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 413                 return 4;
 414         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 415                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 416
 417         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 418                 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
 419                                               PIPE_SHADER_CAP_SUPPORTED_IRS) &
 420                     (1 << PIPE_SHADER_IR_TGSI))
 421                         return 430;
 422                 return HAVE_LLVM >= 0x0309 ? 420 :
 423                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 424
 425         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 426                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 427
 428         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 429                 return 0;
 430
 431         /* Unsupported features. */
 432         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 433         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 434         case PIPE_CAP_USER_VERTEX_BUFFERS:
 435         case PIPE_CAP_FAKE_SW_MSAA:
 436         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 437         case PIPE_CAP_VERTEXID_NOBASE:
 438         case PIPE_CAP_CLEAR_TEXTURE:
 439         case PIPE_CAP_DRAW_PARAMETERS:
 440         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 441         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 442         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 443         case PIPE_CAP_CULL_DISTANCE:
 444         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 445         case PIPE_CAP_TGSI_VOTE:
 446         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 447                 return 0;
 448
 449         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 450                 return 30;
 451
 452         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 453                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 454
 455         /* Stream output. */
 456         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 457                 return sscreen->b.has_streamout ? 4 : 0;
 458         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 459                 return sscreen->b.has_streamout ? 1 : 0;
 460         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 461         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 462                 return sscreen->b.has_streamout ? 32*4 : 0;
 463
 464         /* Geometry shader output. */
 465         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 466                 return 1024;
 467         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 468                 return 4095;
 469         case PIPE_CAP_MAX_VERTEX_STREAMS:
 470                 return 4;
 471
 472         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 473                 return 2048;
 474
 475         /* Texturing. */
 476         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 477         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 478                 return 15; /* 16384 */
 479         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 480                 /* textures support 8192, but layered rendering supports 2048 */
 481                 return 12;
 482         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 483                 /* textures support 8192, but layered rendering supports 2048 */
 484                 return 2048;
 485
 486         /* Render targets. */
 487         case PIPE_CAP_MAX_RENDER_TARGETS:
 488                 return 8;
 489
 490         case PIPE_CAP_MAX_VIEWPORTS:
 491                 return R600_MAX_VIEWPORTS;
 492         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 493                 return 8;
 494
 495         /* Timer queries, present when the clock frequency is non zero. */
 496         case PIPE_CAP_QUERY_TIMESTAMP:
 497         case PIPE_CAP_QUERY_TIME_ELAPSED:
 498                 return sscreen->b.info.clock_crystal_freq != 0;
 499
 500         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 501         case PIPE_CAP_MIN_TEXEL_OFFSET:
 502                 return -32;
 503
 504         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 505         case PIPE_CAP_MAX_TEXEL_OFFSET:
 506                 return 31;
 507
 508         case PIPE_CAP_ENDIANNESS:
 509                 return PIPE_ENDIAN_LITTLE;
 510
 511         case PIPE_CAP_VENDOR_ID:
 512                 return ATI_VENDOR_ID;
 513         case PIPE_CAP_DEVICE_ID:
 514                 return sscreen->b.info.pci_id;
 515         case PIPE_CAP_ACCELERATED:
 516                 return 1;
 517         case PIPE_CAP_VIDEO_MEMORY:
 518                 return sscreen->b.info.vram_size >> 20;
 519         case PIPE_CAP_UMA:
 520                 return 0;
 521         case PIPE_CAP_PCI_GROUP:
 522                 return sscreen->b.info.pci_domain;
 523         case PIPE_CAP_PCI_BUS:
 524                 return sscreen->b.info.pci_bus;
 525         case PIPE_CAP_PCI_DEVICE:
 526                 return sscreen->b.info.pci_dev;
 527         case PIPE_CAP_PCI_FUNCTION:
 528                 return sscreen->b.info.pci_func;
 529         }
 530         return 0;
 531 }
 532
 533 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 534 {
 535         struct si_screen *sscreen = (struct si_screen *)pscreen;
 536
 537         switch(shader)
 538         {
 539         case PIPE_SHADER_FRAGMENT:
 540         case PIPE_SHADER_VERTEX:
 541         case PIPE_SHADER_GEOMETRY:
 542                 break;
 543         case PIPE_SHADER_TESS_CTRL:
 544         case PIPE_SHADER_TESS_EVAL:
 545                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 546                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 547                         return 0;
 548                 break;
 549         case PIPE_SHADER_COMPUTE:
 550                 switch (param) {
 551                 case PIPE_SHADER_CAP_PREFERRED_IR:
 552                         return PIPE_SHADER_IR_NATIVE;
 553
 554                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 555                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 556
 557                         /* Old kernels disallowed some register writes for SI
 558                          * that are used for indirect dispatches. */
 559                         if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
 560                                                    sscreen->b.info.drm_major == 3 ||
 561                                                    (sscreen->b.info.drm_major == 2 &&
 562                                                     sscreen->b.info.drm_minor >= 45)))
 563                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 564
 565                         return ir;
 566                 }
 567                 case PIPE_SHADER_CAP_DOUBLES:
 568                         return HAVE_LLVM >= 0x0307;
 569
 570                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 571                         uint64_t max_const_buffer_size;
 572                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 573                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 574                                 &max_const_buffer_size);
 575                         return MIN2(max_const_buffer_size, INT_MAX);
 576                 }
 577                 default:
 578                         /* If compute shaders don't require a special value
 579                          * for this cap, we can return the same value we
 580                          * do for other shader types. */
 581                         break;
 582                 }
 583                 break;
 584         default:
 585                 return 0;
 586         }
 587
 588         switch (param) {
 589         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 590         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 591         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 592         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 593                 return 16384;
 594         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 595                 return 32;
 596         case PIPE_SHADER_CAP_MAX_INPUTS:
 597                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 598         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 599                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 600         case PIPE_SHADER_CAP_MAX_TEMPS:
 601                 return 256; /* Max native temporaries. */
 602         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 603                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 604         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 605                 return SI_NUM_CONST_BUFFERS;
 606         case PIPE_SHADER_CAP_MAX_PREDS:
 607                 return 0; /* FIXME */
 608         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 609                 return 1;
 610         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 611                 return 1;
 612         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 613                 /* Indirection of geometry shader input dimension is not
 614                  * handled yet
 615                  */
 616                 return shader != PIPE_SHADER_GEOMETRY;
 617         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 618         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 619         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 620                 return 1;
 621         case PIPE_SHADER_CAP_INTEGERS:
 622                 return 1;
 623         case PIPE_SHADER_CAP_SUBROUTINES:
 624                 return 0;
 625         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 626         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 627                 return SI_NUM_SAMPLERS;
 628         case PIPE_SHADER_CAP_PREFERRED_IR:
 629                 return PIPE_SHADER_IR_TGSI;
 630         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 631                 return 0;
 632         case PIPE_SHADER_CAP_DOUBLES:
 633                 return HAVE_LLVM >= 0x0307;
 634         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 635         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 636                 return 0;
 637         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 638         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 639                 return 1;
 640         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 641                 return 32;
 642         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 643                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 644         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 645                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 646         }
 647         return 0;
 648 }
 649
 650 static void si_destroy_screen(struct pipe_screen* pscreen)
 651 {
 652         struct si_screen *sscreen = (struct si_screen *)pscreen;
 653         struct si_shader_part *parts[] = {
 654                 sscreen->vs_prologs,
 655                 sscreen->vs_epilogs,
 656                 sscreen->tcs_epilogs,
 657                 sscreen->ps_prologs,
 658                 sscreen->ps_epilogs
 659         };
 660         unsigned i;
 661
 662         if (!sscreen)
 663                 return;
 664
 665         if (!sscreen->b.ws->unref(sscreen->b.ws))
 666                 return;
 667
 668         if (util_queue_is_initialized(&sscreen->shader_compiler_queue))
 669                 util_queue_destroy(&sscreen->shader_compiler_queue);
 670
 671         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 672                 if (sscreen->tm[i])
 673                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 674
 675         /* Free shader parts. */
 676         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 677                 while (parts[i]) {
 678                         struct si_shader_part *part = parts[i];
 679
 680                         parts[i] = part->next;
 681                         radeon_shader_binary_clean(&part->binary);
 682                         FREE(part);
 683                 }
 684         }
 685         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 686         si_destroy_shader_cache(sscreen);
 687         r600_destroy_common_screen(&sscreen->b);
 688 }
 689
 690 static bool si_init_gs_info(struct si_screen *sscreen)
 691 {
 692         switch (sscreen->b.family) {
 693         case CHIP_OLAND:
 694         case CHIP_HAINAN:
 695         case CHIP_KAVERI:
 696         case CHIP_KABINI:
 697         case CHIP_MULLINS:
 698         case CHIP_ICELAND:
 699         case CHIP_CARRIZO:
 700         case CHIP_STONEY:
 701                 sscreen->gs_table_depth = 16;
 702                 return true;
 703         case CHIP_TAHITI:
 704         case CHIP_PITCAIRN:
 705         case CHIP_VERDE:
 706         case CHIP_BONAIRE:
 707         case CHIP_HAWAII:
 708         case CHIP_TONGA:
 709         case CHIP_FIJI:
 710         case CHIP_POLARIS10:
 711         case CHIP_POLARIS11:
 712                 sscreen->gs_table_depth = 32;
 713                 return true;
 714         default:
 715                 return false;
 716         }
 717 }
 718
 719 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 720 {
 721         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 722         unsigned num_cpus, num_compiler_threads, i;
 723
 724         if (!sscreen) {
 725                 return NULL;
 726         }
 727
 728         /* Set functions first. */
 729         sscreen->b.b.context_create = si_create_context;
 730         sscreen->b.b.destroy = si_destroy_screen;
 731         sscreen->b.b.get_param = si_get_param;
 732         sscreen->b.b.get_shader_param = si_get_shader_param;
 733         sscreen->b.b.resource_create = r600_resource_create_common;
 734
 735         si_init_screen_state_functions(sscreen);
 736
 737         if (!r600_common_screen_init(&sscreen->b, ws) ||
 738             !si_init_gs_info(sscreen) ||
 739             !si_init_shader_cache(sscreen)) {
 740                 FREE(sscreen);
 741                 return NULL;
 742         }
 743
 744         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 745                 si_init_perfcounters(sscreen);
 746
 747         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 748          * around by setting 4K granularity.
 749          */
 750         sscreen->tess_offchip_block_dw_size =
 751                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
 752
 753         sscreen->has_distributed_tess =
 754                 sscreen->b.chip_class >= VI &&
 755                 sscreen->b.info.max_se >= 2;
 756
 757         sscreen->b.has_cp_dma = true;
 758         sscreen->b.has_streamout = true;
 759         pipe_mutex_init(sscreen->shader_parts_mutex);
 760         sscreen->use_monolithic_shaders =
 761                 HAVE_LLVM < 0x0308 ||
 762                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 763
 764         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
 765                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 766
 767         /* Only enable as many threads as we have target machines and CPUs. */
 768         num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 769         num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
 770
 771         for (i = 0; i < num_compiler_threads; i++)
 772                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 773
 774         util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 775                         32, num_compiler_threads);
 776
 777         /* Create the auxiliary context. This must be done last. */
 778         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 779
 780         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 781                 r600_test_dma(&sscreen->b);
 782
 783         return &sscreen->b.b;
 784 }