src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_table, NULL);
  48         r600_resource_reference(&sctx->scratch_buffer, NULL);
  49         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  50
  51         si_pm4_free_state(sctx, sctx->init_config, ~0);
  52         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  53                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  54
  55         if (sctx->pstipple_sampler_state)
  56                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  57         if (sctx->dummy_pixel_shader)
  58                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  59         if (sctx->fixed_func_tcs_shader)
  60                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader);
  61         if (sctx->custom_dsa_flush)
  62                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  63         if (sctx->custom_blend_resolve)
  64                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  65         if (sctx->custom_blend_decompress)
  66                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  67         if (sctx->custom_blend_fastclear)
  68                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  69         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  70
  71         if (sctx->blitter)
  72                 util_blitter_destroy(sctx->blitter);
  73
  74         si_pm4_cleanup(sctx);
  75
  76         r600_common_context_cleanup(&sctx->b);
  77
  78 #if HAVE_LLVM >= 0x0306
  79         LLVMDisposeTargetMachine(sctx->tm);
  80 #endif
  81
  82         r600_resource_reference(&sctx->trace_buf, NULL);
  83         r600_resource_reference(&sctx->last_trace_buf, NULL);
  84         free(sctx->last_ib);
  85         FREE(sctx);
  86 }
  87
  88 static enum pipe_reset_status
  89 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  90 {
  91         struct si_context *sctx = (struct si_context *)ctx;
  92
  93         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  94 }
  95
  96 static struct pipe_context *si_create_context(struct pipe_screen *screen,
  97                                               void *priv, unsigned flags)
  98 {
  99         struct si_context *sctx = CALLOC_STRUCT(si_context);
 100         struct si_screen* sscreen = (struct si_screen *)screen;
 101         struct radeon_winsys *ws = sscreen->b.ws;
 102         LLVMTargetRef r600_target;
 103 #if HAVE_LLVM >= 0x0306
 104         const char *triple = "amdgcn--";
 105 #endif
 106         int shader, i;
 107
 108         if (sctx == NULL)
 109                 return NULL;
 110
 111         sctx->b.b.screen = screen; /* this must be set first */
 112         sctx->b.b.priv = priv;
 113         sctx->b.b.destroy = si_destroy_context;
 114         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 115         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 116         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 117
 118         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 119                 goto fail;
 120
 121         if (sscreen->b.info.drm_major == 3)
 122                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 123
 124         si_init_blit_functions(sctx);
 125         si_init_compute_functions(sctx);
 126         si_init_cp_dma_functions(sctx);
 127         si_init_debug_functions(sctx);
 128
 129         if (sscreen->b.info.has_uvd) {
 130                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 131                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 132         } else {
 133                 sctx->b.b.create_video_codec = vl_create_decoder;
 134                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 135         }
 136
 137         sctx->b.rings.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 138                                              sctx, sscreen->b.trace_bo ?
 139                                                 sscreen->b.trace_bo->cs_buf : NULL);
 140         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 141
 142         si_init_all_descriptors(sctx);
 143         si_init_state_functions(sctx);
 144         si_init_shader_functions(sctx);
 145
 146         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 147                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 148
 149         sctx->blitter = util_blitter_create(&sctx->b.b);
 150         if (sctx->blitter == NULL)
 151                 goto fail;
 152         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 153
 154         sctx->sample_mask.sample_mask = 0xffff;
 155
 156         /* these must be last */
 157         si_begin_new_cs(sctx);
 158         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 159
 160         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 161          * with a NULL buffer). We need to use a dummy buffer instead. */
 162         if (sctx->b.chip_class == CIK) {
 163                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 164                                                                  PIPE_USAGE_DEFAULT, 16);
 165                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 166
 167                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 168                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 169                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 170                                                               &sctx->null_const_buf);
 171                         }
 172                 }
 173
 174                 /* Clear the NULL constant buffer, because loads should return zeros. */
 175                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 176                                      sctx->null_const_buf.buffer->width0, 0, false);
 177         }
 178
 179         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 180          * this for non-cs shaders.  Using the wrong value here can result in
 181          * GPU lockups, but the maximum value seems to always work.
 182          */
 183         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 184
 185 #if HAVE_LLVM >= 0x0306
 186         /* Initialize LLVM TargetMachine */
 187         r600_target = radeon_llvm_get_r600_target(triple);
 188         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 189                                            r600_get_llvm_processor_name(sscreen->b.family),
 190                                            sctx->b.chip_class >= VI ?
 191                                                    "+DumpCode" :
 192                                                    "+DumpCode,+vgpr-spilling",
 193                                            LLVMCodeGenLevelDefault,
 194                                            LLVMRelocDefault,
 195                                            LLVMCodeModelDefault);
 196 #endif
 197
 198         return &sctx->b.b;
 199 fail:
 200         si_destroy_context(&sctx->b.b);
 201         return NULL;
 202 }
 203
 204 /*
 205  * pipe_screen
 206  */
 207
 208 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 209 {
 210         struct si_screen *sscreen = (struct si_screen *)pscreen;
 211
 212         switch (param) {
 213         /* Supported features (boolean caps). */
 214         case PIPE_CAP_TWO_SIDED_STENCIL:
 215         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 216         case PIPE_CAP_ANISOTROPIC_FILTER:
 217         case PIPE_CAP_POINT_SPRITE:
 218         case PIPE_CAP_OCCLUSION_QUERY:
 219         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 220         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 221         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 222         case PIPE_CAP_TEXTURE_SWIZZLE:
 223         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 224         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 225         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 226         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 227         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 228         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 229         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 230         case PIPE_CAP_SM3:
 231         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 232         case PIPE_CAP_PRIMITIVE_RESTART:
 233         case PIPE_CAP_CONDITIONAL_RENDER:
 234         case PIPE_CAP_TEXTURE_BARRIER:
 235         case PIPE_CAP_INDEP_BLEND_ENABLE:
 236         case PIPE_CAP_INDEP_BLEND_FUNC:
 237         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 238         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 239         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 240         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 241         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 242         case PIPE_CAP_USER_INDEX_BUFFERS:
 243         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 244         case PIPE_CAP_START_INSTANCE:
 245         case PIPE_CAP_NPOT_TEXTURES:
 246         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 247         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 248         case PIPE_CAP_TGSI_INSTANCEID:
 249         case PIPE_CAP_COMPUTE:
 250         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 251         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 252         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 253         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 254         case PIPE_CAP_CUBE_MAP_ARRAY:
 255         case PIPE_CAP_SAMPLE_SHADING:
 256         case PIPE_CAP_DRAW_INDIRECT:
 257         case PIPE_CAP_CLIP_HALFZ:
 258         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 259         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 260         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 261         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 262         case PIPE_CAP_TGSI_TEXCOORD:
 263         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 264         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 265         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 266         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 267         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 268                 return 1;
 269
 270         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 271                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 272
 273         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 274                 return (sscreen->b.info.drm_major == 2 &&
 275                         sscreen->b.info.drm_minor >= 43) ||
 276                        sscreen->b.info.drm_major == 3;
 277
 278         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 279                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 280                 return sscreen->b.chip_class < CIK ||
 281                        (sscreen->b.info.drm_major == 2 &&
 282                         sscreen->b.info.drm_minor >= 35) ||
 283                        sscreen->b.info.drm_major == 3;
 284
 285         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 286                 return R600_MAP_BUFFER_ALIGNMENT;
 287
 288         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 289         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 290                 return 4;
 291
 292         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 293                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 294
 295         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 296                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 297
 298         case PIPE_CAP_TEXTURE_QUERY_LOD:
 299         case PIPE_CAP_TEXTURE_GATHER_SM5:
 300                 return HAVE_LLVM >= 0x0305;
 301         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 302                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 303
 304         /* Unsupported features. */
 305         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 306         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 307         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 308         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 309         case PIPE_CAP_USER_VERTEX_BUFFERS:
 310         case PIPE_CAP_FAKE_SW_MSAA:
 311         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 312         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 313         case PIPE_CAP_VERTEXID_NOBASE:
 314                 return 0;
 315
 316         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 317                 return 30;
 318
 319         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 320                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 321
 322         /* Stream output. */
 323         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 324                 return sscreen->b.has_streamout ? 4 : 0;
 325         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 326                 return sscreen->b.has_streamout ? 1 : 0;
 327         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 328         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 329                 return sscreen->b.has_streamout ? 32*4 : 0;
 330
 331         /* Geometry shader output. */
 332         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 333                 return 1024;
 334         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 335                 return 4095;
 336         case PIPE_CAP_MAX_VERTEX_STREAMS:
 337                 return 4;
 338
 339         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 340                 return 2048;
 341
 342         /* Texturing. */
 343         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 344         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 345                 return 15; /* 16384 */
 346         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 347                 /* textures support 8192, but layered rendering supports 2048 */
 348                 return 12;
 349         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 350                 /* textures support 8192, but layered rendering supports 2048 */
 351                 return 2048;
 352
 353         /* Render targets. */
 354         case PIPE_CAP_MAX_RENDER_TARGETS:
 355                 return 8;
 356
 357         case PIPE_CAP_MAX_VIEWPORTS:
 358                 return SI_MAX_VIEWPORTS;
 359
 360         /* Timer queries, present when the clock frequency is non zero. */
 361         case PIPE_CAP_QUERY_TIMESTAMP:
 362         case PIPE_CAP_QUERY_TIME_ELAPSED:
 363                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 364
 365         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 366         case PIPE_CAP_MIN_TEXEL_OFFSET:
 367                 return -32;
 368
 369         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 370         case PIPE_CAP_MAX_TEXEL_OFFSET:
 371                 return 31;
 372
 373         case PIPE_CAP_ENDIANNESS:
 374                 return PIPE_ENDIAN_LITTLE;
 375
 376         case PIPE_CAP_VENDOR_ID:
 377                 return 0x1002;
 378         case PIPE_CAP_DEVICE_ID:
 379                 return sscreen->b.info.pci_id;
 380         case PIPE_CAP_ACCELERATED:
 381                 return 1;
 382         case PIPE_CAP_VIDEO_MEMORY:
 383                 return sscreen->b.info.vram_size >> 20;
 384         case PIPE_CAP_UMA:
 385                 return 0;
 386         }
 387         return 0;
 388 }
 389
 390 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 391 {
 392         switch(shader)
 393         {
 394         case PIPE_SHADER_FRAGMENT:
 395         case PIPE_SHADER_VERTEX:
 396         case PIPE_SHADER_GEOMETRY:
 397                 break;
 398         case PIPE_SHADER_TESS_CTRL:
 399         case PIPE_SHADER_TESS_EVAL:
 400                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 401                 if (HAVE_LLVM < 0x0306 ||
 402                     (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
 403                         return 0;
 404                 break;
 405         case PIPE_SHADER_COMPUTE:
 406                 switch (param) {
 407                 case PIPE_SHADER_CAP_PREFERRED_IR:
 408 #if HAVE_LLVM < 0x0306
 409                         return PIPE_SHADER_IR_LLVM;
 410 #else
 411                         return PIPE_SHADER_IR_NATIVE;
 412 #endif
 413                 case PIPE_SHADER_CAP_DOUBLES:
 414                         return HAVE_LLVM >= 0x0307;
 415
 416                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 417                         uint64_t max_const_buffer_size;
 418                         pscreen->get_compute_param(pscreen,
 419                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 420                                 &max_const_buffer_size);
 421                         return max_const_buffer_size;
 422                 }
 423                 default:
 424                         /* If compute shaders don't require a special value
 425                          * for this cap, we can return the same value we
 426                          * do for other shader types. */
 427                         break;
 428                 }
 429                 break;
 430         default:
 431                 return 0;
 432         }
 433
 434         switch (param) {
 435         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 436         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 437         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 438         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 439                 return 16384;
 440         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 441                 return 32;
 442         case PIPE_SHADER_CAP_MAX_INPUTS:
 443                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 444         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 445                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 446         case PIPE_SHADER_CAP_MAX_TEMPS:
 447                 return 256; /* Max native temporaries. */
 448         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 449                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 450         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 451                 return SI_NUM_USER_CONST_BUFFERS;
 452         case PIPE_SHADER_CAP_MAX_PREDS:
 453                 return 0; /* FIXME */
 454         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 455                 return 1;
 456         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 457                 return 1;
 458         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 459                 /* Indirection of geometry shader input dimension is not
 460                  * handled yet
 461                  */
 462                 return shader != PIPE_SHADER_GEOMETRY;
 463         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 464         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 465         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 466                 return 1;
 467         case PIPE_SHADER_CAP_INTEGERS:
 468                 return 1;
 469         case PIPE_SHADER_CAP_SUBROUTINES:
 470                 return 0;
 471         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 472         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 473                 return 16;
 474         case PIPE_SHADER_CAP_PREFERRED_IR:
 475                 return PIPE_SHADER_IR_TGSI;
 476         case PIPE_SHADER_CAP_DOUBLES:
 477                 return HAVE_LLVM >= 0x0307;
 478         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 479         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 480                 return 0;
 481         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 482         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 483                 return 1;
 484         }
 485         return 0;
 486 }
 487
 488 static void si_destroy_screen(struct pipe_screen* pscreen)
 489 {
 490         struct si_screen *sscreen = (struct si_screen *)pscreen;
 491
 492         if (sscreen == NULL)
 493                 return;
 494
 495         if (!sscreen->b.ws->unref(sscreen->b.ws))
 496                 return;
 497
 498         r600_destroy_common_screen(&sscreen->b);
 499 }
 500
 501 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 502
 503 /* Initialize pipe config. This is especially important for GPUs
 504  * with 16 pipes and more where it's initialized incorrectly by
 505  * the TILING_CONFIG ioctl. */
 506 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 507 {
 508         unsigned mode2d;
 509
 510         /* This is okay, because there can be no 2D tiling without
 511          * the tile mode array, so we won't need the pipe config.
 512          * Return "success".
 513          */
 514         if (!sscreen->b.info.si_tile_mode_array_valid)
 515                 return true;
 516
 517         /* The same index is used for the 2D mode on CIK too. */
 518         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 519
 520         switch (G_009910_PIPE_CONFIG(mode2d)) {
 521         case V_02803C_ADDR_SURF_P2:
 522                 sscreen->b.tiling_info.num_channels = 2;
 523                 break;
 524         case V_02803C_X_ADDR_SURF_P4_8X16:
 525         case V_02803C_X_ADDR_SURF_P4_16X16:
 526         case V_02803C_X_ADDR_SURF_P4_16X32:
 527         case V_02803C_X_ADDR_SURF_P4_32X32:
 528                 sscreen->b.tiling_info.num_channels = 4;
 529                 break;
 530         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 531         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 532         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 533         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 534         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 535         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 536         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 537                 sscreen->b.tiling_info.num_channels = 8;
 538                 break;
 539         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 540         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 541                 sscreen->b.tiling_info.num_channels = 16;
 542                 break;
 543         default:
 544                 assert(0);
 545                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 546                         G_009910_PIPE_CONFIG(mode2d));
 547                 return false;
 548         }
 549         return true;
 550 }
 551
 552 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 553 {
 554         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 555
 556         if (sscreen == NULL) {
 557                 return NULL;
 558         }
 559
 560         /* Set functions first. */
 561         sscreen->b.b.context_create = si_create_context;
 562         sscreen->b.b.destroy = si_destroy_screen;
 563         sscreen->b.b.get_param = si_get_param;
 564         sscreen->b.b.get_shader_param = si_get_shader_param;
 565         sscreen->b.b.is_format_supported = si_is_format_supported;
 566         sscreen->b.b.resource_create = r600_resource_create_common;
 567
 568         if (!r600_common_screen_init(&sscreen->b, ws) ||
 569             !si_initialize_pipe_config(sscreen)) {
 570                 FREE(sscreen);
 571                 return NULL;
 572         }
 573
 574         sscreen->b.has_cp_dma = true;
 575         sscreen->b.has_streamout = true;
 576
 577         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 578                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 579
 580         /* Create the auxiliary context. This must be done last. */
 581         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 582
 583         return &sscreen->b.b;
 584 }