src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "vl/vl_decoder.h"
  33
  34 /*
  35  * pipe_context
  36  */
  37 static void si_destroy_context(struct pipe_context *context)
  38 {
  39         struct si_context *sctx = (struct si_context *)context;
  40         int i;
  41
  42         si_release_all_descriptors(sctx);
  43
  44         pipe_resource_reference(&sctx->esgs_ring, NULL);
  45         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  46         pipe_resource_reference(&sctx->tf_ring, NULL);
  47         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  48         r600_resource_reference(&sctx->border_color_buffer, NULL);
  49         free(sctx->border_color_table);
  50         r600_resource_reference(&sctx->scratch_buffer, NULL);
  51         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  52
  53         si_pm4_free_state(sctx, sctx->init_config, ~0);
  54         if (sctx->init_config_gs_rings)
  55                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  56         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  57                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  58
  59         if (sctx->pstipple_sampler_state)
  60                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  61         if (sctx->fixed_func_tcs_shader.cso)
  62                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  63         if (sctx->custom_dsa_flush)
  64                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  65         if (sctx->custom_blend_resolve)
  66                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  67         if (sctx->custom_blend_decompress)
  68                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  69         if (sctx->custom_blend_fastclear)
  70                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  71         if (sctx->custom_blend_dcc_decompress)
  72                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  73         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  74
  75         if (sctx->blitter)
  76                 util_blitter_destroy(sctx->blitter);
  77
  78         r600_common_context_cleanup(&sctx->b);
  79
  80         LLVMDisposeTargetMachine(sctx->tm);
  81
  82         r600_resource_reference(&sctx->trace_buf, NULL);
  83         r600_resource_reference(&sctx->last_trace_buf, NULL);
  84         free(sctx->last_ib);
  85         if (sctx->last_bo_list) {
  86                 for (i = 0; i < sctx->last_bo_count; i++)
  87                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  88                 free(sctx->last_bo_list);
  89         }
  90         FREE(sctx);
  91 }
  92
  93 static enum pipe_reset_status
  94 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  95 {
  96         struct si_context *sctx = (struct si_context *)ctx;
  97
  98         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  99 }
 100
 101 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 102                                               void *priv, unsigned flags)
 103 {
 104         struct si_context *sctx = CALLOC_STRUCT(si_context);
 105         struct si_screen* sscreen = (struct si_screen *)screen;
 106         struct radeon_winsys *ws = sscreen->b.ws;
 107         LLVMTargetRef r600_target;
 108         const char *triple = "amdgcn--";
 109         int shader, i;
 110
 111         if (!sctx)
 112                 return NULL;
 113
 114         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 115                 flags |= PIPE_CONTEXT_DEBUG;
 116
 117         sctx->b.b.screen = screen; /* this must be set first */
 118         sctx->b.b.priv = priv;
 119         sctx->b.b.destroy = si_destroy_context;
 120         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 121         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 122         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 123
 124         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 125                 goto fail;
 126
 127         if (sscreen->b.info.drm_major == 3)
 128                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 129
 130         si_init_blit_functions(sctx);
 131         si_init_compute_functions(sctx);
 132         si_init_cp_dma_functions(sctx);
 133         si_init_debug_functions(sctx);
 134
 135         if (sscreen->b.info.has_uvd) {
 136                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 137                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 138         } else {
 139                 sctx->b.b.create_video_codec = vl_create_decoder;
 140                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 141         }
 142
 143         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 144                                        sctx, sscreen->b.trace_bo ?
 145                                                sscreen->b.trace_bo->buf : NULL);
 146         sctx->b.gfx.flush = si_context_gfx_flush;
 147
 148         /* Border colors. */
 149         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 150                                           sizeof(*sctx->border_color_table));
 151         if (!sctx->border_color_table)
 152                 goto fail;
 153
 154         sctx->border_color_buffer = (struct r600_resource*)
 155                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 156                                    SI_MAX_BORDER_COLORS *
 157                                    sizeof(*sctx->border_color_table));
 158         if (!sctx->border_color_buffer)
 159                 goto fail;
 160
 161         sctx->border_color_map =
 162                 ws->buffer_map(sctx->border_color_buffer->buf,
 163                                NULL, PIPE_TRANSFER_WRITE);
 164         if (!sctx->border_color_map)
 165                 goto fail;
 166
 167         si_init_all_descriptors(sctx);
 168         si_init_state_functions(sctx);
 169         si_init_shader_functions(sctx);
 170
 171         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 172                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 173
 174         sctx->blitter = util_blitter_create(&sctx->b.b);
 175         if (sctx->blitter == NULL)
 176                 goto fail;
 177         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 178
 179         sctx->sample_mask.sample_mask = 0xffff;
 180
 181         /* these must be last */
 182         si_begin_new_cs(sctx);
 183         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 184
 185         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 186          * with a NULL buffer). We need to use a dummy buffer instead. */
 187         if (sctx->b.chip_class == CIK) {
 188                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 189                                                                  PIPE_USAGE_DEFAULT, 16);
 190                 if (!sctx->null_const_buf.buffer)
 191                         goto fail;
 192                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 193
 194                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 195                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 196                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 197                                                               &sctx->null_const_buf);
 198                         }
 199                 }
 200
 201                 /* Clear the NULL constant buffer, because loads should return zeros. */
 202                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 203                                      sctx->null_const_buf.buffer->width0, 0, false);
 204         }
 205
 206         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 207          * this for non-cs shaders.  Using the wrong value here can result in
 208          * GPU lockups, but the maximum value seems to always work.
 209          */
 210         sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
 211
 212         /* Initialize LLVM TargetMachine */
 213         r600_target = radeon_llvm_get_r600_target(triple);
 214         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 215                                            r600_get_llvm_processor_name(sscreen->b.family),
 216 #if HAVE_LLVM >= 0x0308
 217                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 218                                                 "+DumpCode,+vgpr-spilling,+si-scheduler" :
 219 #endif
 220                                                 "+DumpCode,+vgpr-spilling",
 221                                            LLVMCodeGenLevelDefault,
 222                                            LLVMRelocDefault,
 223                                            LLVMCodeModelDefault);
 224
 225         return &sctx->b.b;
 226 fail:
 227         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 228         si_destroy_context(&sctx->b.b);
 229         return NULL;
 230 }
 231
 232 /*
 233  * pipe_screen
 234  */
 235
 236 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 237 {
 238         struct si_screen *sscreen = (struct si_screen *)pscreen;
 239
 240         switch (param) {
 241         /* Supported features (boolean caps). */
 242         case PIPE_CAP_TWO_SIDED_STENCIL:
 243         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 244         case PIPE_CAP_ANISOTROPIC_FILTER:
 245         case PIPE_CAP_POINT_SPRITE:
 246         case PIPE_CAP_OCCLUSION_QUERY:
 247         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 248         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 249         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 250         case PIPE_CAP_TEXTURE_SWIZZLE:
 251         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 252         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 253         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 254         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 255         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 256         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 257         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 258         case PIPE_CAP_SM3:
 259         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 260         case PIPE_CAP_PRIMITIVE_RESTART:
 261         case PIPE_CAP_CONDITIONAL_RENDER:
 262         case PIPE_CAP_TEXTURE_BARRIER:
 263         case PIPE_CAP_INDEP_BLEND_ENABLE:
 264         case PIPE_CAP_INDEP_BLEND_FUNC:
 265         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 266         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 267         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 268         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 269         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 270         case PIPE_CAP_USER_INDEX_BUFFERS:
 271         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 272         case PIPE_CAP_START_INSTANCE:
 273         case PIPE_CAP_NPOT_TEXTURES:
 274         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 275         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 276         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 277         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 278         case PIPE_CAP_TGSI_INSTANCEID:
 279         case PIPE_CAP_COMPUTE:
 280         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 281         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 282         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 283         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 284         case PIPE_CAP_CUBE_MAP_ARRAY:
 285         case PIPE_CAP_SAMPLE_SHADING:
 286         case PIPE_CAP_DRAW_INDIRECT:
 287         case PIPE_CAP_CLIP_HALFZ:
 288         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 289         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 290         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 291         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 292         case PIPE_CAP_TGSI_TEXCOORD:
 293         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 294         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 295         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 296         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 297         case PIPE_CAP_SHAREABLE_SHADERS:
 298         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 299         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 300         case PIPE_CAP_TEXTURE_QUERY_LOD:
 301         case PIPE_CAP_TEXTURE_GATHER_SM5:
 302         case PIPE_CAP_TGSI_TXQS:
 303         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 304         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 305         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 306         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 307         case PIPE_CAP_INVALIDATE_BUFFER:
 308         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 309         case PIPE_CAP_QUERY_MEMORY_INFO:
 310         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 311                 return 1;
 312
 313         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 314                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 315
 316         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 317                 return (sscreen->b.info.drm_major == 2 &&
 318                         sscreen->b.info.drm_minor >= 43) ||
 319                        sscreen->b.info.drm_major == 3;
 320
 321         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 322                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 323                 return sscreen->b.chip_class < CIK ||
 324                        (sscreen->b.info.drm_major == 2 &&
 325                         sscreen->b.info.drm_minor >= 35) ||
 326                        sscreen->b.info.drm_major == 3;
 327
 328         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 329                 return R600_MAP_BUFFER_ALIGNMENT;
 330
 331         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 332         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 333         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 334                 return 4;
 335
 336         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 337                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 338
 339         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 340                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 341
 342         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 343                 return 0;
 344
 345         /* Unsupported features. */
 346         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 347         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 348         case PIPE_CAP_USER_VERTEX_BUFFERS:
 349         case PIPE_CAP_FAKE_SW_MSAA:
 350         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 351         case PIPE_CAP_VERTEXID_NOBASE:
 352         case PIPE_CAP_CLEAR_TEXTURE:
 353         case PIPE_CAP_DRAW_PARAMETERS:
 354         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 355         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 356         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 357         case PIPE_CAP_GENERATE_MIPMAP:
 358         case PIPE_CAP_STRING_MARKER:
 359         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 360                 return 0;
 361
 362         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 363                 return 30;
 364
 365         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 366                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 367
 368         /* Stream output. */
 369         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 370                 return sscreen->b.has_streamout ? 4 : 0;
 371         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 372                 return sscreen->b.has_streamout ? 1 : 0;
 373         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 374         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 375                 return sscreen->b.has_streamout ? 32*4 : 0;
 376
 377         /* Geometry shader output. */
 378         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 379                 return 1024;
 380         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 381                 return 4095;
 382         case PIPE_CAP_MAX_VERTEX_STREAMS:
 383                 return 4;
 384
 385         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 386                 return 2048;
 387
 388         /* Texturing. */
 389         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 390         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 391                 return 15; /* 16384 */
 392         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 393                 /* textures support 8192, but layered rendering supports 2048 */
 394                 return 12;
 395         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 396                 /* textures support 8192, but layered rendering supports 2048 */
 397                 return 2048;
 398
 399         /* Render targets. */
 400         case PIPE_CAP_MAX_RENDER_TARGETS:
 401                 return 8;
 402
 403         case PIPE_CAP_MAX_VIEWPORTS:
 404                 return SI_MAX_VIEWPORTS;
 405
 406         /* Timer queries, present when the clock frequency is non zero. */
 407         case PIPE_CAP_QUERY_TIMESTAMP:
 408         case PIPE_CAP_QUERY_TIME_ELAPSED:
 409                 return sscreen->b.info.clock_crystal_freq != 0;
 410
 411         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 412         case PIPE_CAP_MIN_TEXEL_OFFSET:
 413                 return -32;
 414
 415         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 416         case PIPE_CAP_MAX_TEXEL_OFFSET:
 417                 return 31;
 418
 419         case PIPE_CAP_ENDIANNESS:
 420                 return PIPE_ENDIAN_LITTLE;
 421
 422         case PIPE_CAP_VENDOR_ID:
 423                 return ATI_VENDOR_ID;
 424         case PIPE_CAP_DEVICE_ID:
 425                 return sscreen->b.info.pci_id;
 426         case PIPE_CAP_ACCELERATED:
 427                 return 1;
 428         case PIPE_CAP_VIDEO_MEMORY:
 429                 return sscreen->b.info.vram_size >> 20;
 430         case PIPE_CAP_UMA:
 431                 return 0;
 432         case PIPE_CAP_PCI_GROUP:
 433                 return sscreen->b.info.pci_domain;
 434         case PIPE_CAP_PCI_BUS:
 435                 return sscreen->b.info.pci_bus;
 436         case PIPE_CAP_PCI_DEVICE:
 437                 return sscreen->b.info.pci_dev;
 438         case PIPE_CAP_PCI_FUNCTION:
 439                 return sscreen->b.info.pci_func;
 440         }
 441         return 0;
 442 }
 443
 444 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 445 {
 446         switch(shader)
 447         {
 448         case PIPE_SHADER_FRAGMENT:
 449         case PIPE_SHADER_VERTEX:
 450         case PIPE_SHADER_GEOMETRY:
 451                 break;
 452         case PIPE_SHADER_TESS_CTRL:
 453         case PIPE_SHADER_TESS_EVAL:
 454                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 455                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 456                         return 0;
 457                 break;
 458         case PIPE_SHADER_COMPUTE:
 459                 switch (param) {
 460                 case PIPE_SHADER_CAP_PREFERRED_IR:
 461                         return PIPE_SHADER_IR_NATIVE;
 462
 463                 case PIPE_SHADER_CAP_SUPPORTED_IRS:
 464                         return 0;
 465
 466                 case PIPE_SHADER_CAP_DOUBLES:
 467                         return HAVE_LLVM >= 0x0307;
 468
 469                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 470                         uint64_t max_const_buffer_size;
 471                         pscreen->get_compute_param(pscreen,
 472                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 473                                 &max_const_buffer_size);
 474                         return max_const_buffer_size;
 475                 }
 476                 default:
 477                         /* If compute shaders don't require a special value
 478                          * for this cap, we can return the same value we
 479                          * do for other shader types. */
 480                         break;
 481                 }
 482                 break;
 483         default:
 484                 return 0;
 485         }
 486
 487         switch (param) {
 488         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 489         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 490         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 491         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 492                 return 16384;
 493         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 494                 return 32;
 495         case PIPE_SHADER_CAP_MAX_INPUTS:
 496                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 497         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 498                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 499         case PIPE_SHADER_CAP_MAX_TEMPS:
 500                 return 256; /* Max native temporaries. */
 501         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 502                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 503         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 504                 return SI_NUM_USER_CONST_BUFFERS;
 505         case PIPE_SHADER_CAP_MAX_PREDS:
 506                 return 0; /* FIXME */
 507         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 508                 return 1;
 509         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 510                 return 1;
 511         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 512                 /* Indirection of geometry shader input dimension is not
 513                  * handled yet
 514                  */
 515                 return shader != PIPE_SHADER_GEOMETRY;
 516         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 517         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 518         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 519                 return 1;
 520         case PIPE_SHADER_CAP_INTEGERS:
 521                 return 1;
 522         case PIPE_SHADER_CAP_SUBROUTINES:
 523                 return 0;
 524         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 525         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 526                 return 16;
 527         case PIPE_SHADER_CAP_PREFERRED_IR:
 528                 return PIPE_SHADER_IR_TGSI;
 529         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 530                 return 0;
 531         case PIPE_SHADER_CAP_DOUBLES:
 532                 return HAVE_LLVM >= 0x0307;
 533         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 534         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 535                 return 0;
 536         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 537         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 538                 return 1;
 539         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 540                 return 32;
 541         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 542         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 543                 return 0;
 544         }
 545         return 0;
 546 }
 547
 548 static void si_destroy_screen(struct pipe_screen* pscreen)
 549 {
 550         struct si_screen *sscreen = (struct si_screen *)pscreen;
 551         struct si_shader_part *parts[] = {
 552                 sscreen->vs_prologs,
 553                 sscreen->vs_epilogs,
 554                 sscreen->tcs_epilogs,
 555                 sscreen->ps_prologs,
 556                 sscreen->ps_epilogs
 557         };
 558         unsigned i;
 559
 560         if (!sscreen)
 561                 return;
 562
 563         if (!sscreen->b.ws->unref(sscreen->b.ws))
 564                 return;
 565
 566         /* Free shader parts. */
 567         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 568                 while (parts[i]) {
 569                         struct si_shader_part *part = parts[i];
 570
 571                         parts[i] = part->next;
 572                         radeon_shader_binary_clean(&part->binary);
 573                         FREE(part);
 574                 }
 575         }
 576         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 577         si_destroy_shader_cache(sscreen);
 578         r600_destroy_common_screen(&sscreen->b);
 579 }
 580
 581 static bool si_init_gs_info(struct si_screen *sscreen)
 582 {
 583         switch (sscreen->b.family) {
 584         case CHIP_OLAND:
 585         case CHIP_HAINAN:
 586         case CHIP_KAVERI:
 587         case CHIP_KABINI:
 588         case CHIP_MULLINS:
 589         case CHIP_ICELAND:
 590         case CHIP_CARRIZO:
 591         case CHIP_STONEY:
 592                 sscreen->gs_table_depth = 16;
 593                 return true;
 594         case CHIP_TAHITI:
 595         case CHIP_PITCAIRN:
 596         case CHIP_VERDE:
 597         case CHIP_BONAIRE:
 598         case CHIP_HAWAII:
 599         case CHIP_TONGA:
 600         case CHIP_FIJI:
 601                 sscreen->gs_table_depth = 32;
 602                 return true;
 603         default:
 604                 return false;
 605         }
 606 }
 607
 608 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 609 {
 610         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 611
 612         if (!sscreen) {
 613                 return NULL;
 614         }
 615
 616         /* Set functions first. */
 617         sscreen->b.b.context_create = si_create_context;
 618         sscreen->b.b.destroy = si_destroy_screen;
 619         sscreen->b.b.get_param = si_get_param;
 620         sscreen->b.b.get_shader_param = si_get_shader_param;
 621         sscreen->b.b.is_format_supported = si_is_format_supported;
 622         sscreen->b.b.resource_create = r600_resource_create_common;
 623
 624         si_init_screen_state_functions(sscreen);
 625
 626         if (!r600_common_screen_init(&sscreen->b, ws) ||
 627             !si_init_gs_info(sscreen) ||
 628             !si_init_shader_cache(sscreen)) {
 629                 FREE(sscreen);
 630                 return NULL;
 631         }
 632
 633         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 634                 si_init_perfcounters(sscreen);
 635
 636         sscreen->b.has_cp_dma = true;
 637         sscreen->b.has_streamout = true;
 638         pipe_mutex_init(sscreen->shader_parts_mutex);
 639         sscreen->use_monolithic_shaders =
 640                 HAVE_LLVM < 0x0308 ||
 641                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 642
 643         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 644                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 645
 646         /* Create the auxiliary context. This must be done last. */
 647         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 648
 649         return &sscreen->b.b;
 650 }