2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
31 #include "ac_llvm_util.h"
32 #include "radeon/radeon_uvd.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
44 static const struct debug_named_value debug_options
[] = {
45 /* Shader logging options: */
46 { "vs", DBG(VS
), "Print vertex shaders" },
47 { "ps", DBG(PS
), "Print pixel shaders" },
48 { "gs", DBG(GS
), "Print geometry shaders" },
49 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
50 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
51 { "cs", DBG(CS
), "Print compute shaders" },
52 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
53 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
54 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
55 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
57 /* Shader compiler options the shader cache should be aware of: */
58 { "unsafemath", DBG(UNSAFE_MATH
), "Enable unsafe math shader optimizations" },
59 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
61 /* Shader compiler options (with no effect on the shader cache): */
62 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
63 { "nir", DBG(NIR
), "Enable experimental NIR shaders" },
64 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
65 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
67 /* Information logging options: */
68 { "info", DBG(INFO
), "Print driver information" },
69 { "tex", DBG(TEX
), "Print texture info" },
70 { "compute", DBG(COMPUTE
), "Print compute info" },
71 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
74 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
75 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
76 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
77 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
78 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
79 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
81 /* 3D engine options: */
82 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
83 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
84 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
85 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
86 { "dpbb", DBG(DPBB
), "Enable DPBB." },
87 { "dfsm", DBG(DFSM
), "Enable DFSM." },
88 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
89 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
90 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
91 { "notiling", DBG(NO_TILING
), "Disable tiling" },
92 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
93 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
94 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
95 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
96 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
99 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
100 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
101 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
102 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
104 DEBUG_NAMED_VALUE_END
/* must be last */
107 static void si_init_compiler(struct si_screen
*sscreen
,
108 struct ac_llvm_compiler
*compiler
)
110 enum ac_target_machine_options tm_options
=
111 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
112 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
113 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
114 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
115 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0);
118 ac_init_llvm_compiler(compiler
, true, sscreen
->info
.family
, tm_options
);
119 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
122 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
124 ac_destroy_llvm_passes(compiler
->passes
);
125 ac_destroy_llvm_compiler(compiler
);
131 static void si_destroy_context(struct pipe_context
*context
)
133 struct si_context
*sctx
= (struct si_context
*)context
;
136 /* Unreference the framebuffer normally to disable related logic
139 struct pipe_framebuffer_state fb
= {};
140 if (context
->set_framebuffer_state
)
141 context
->set_framebuffer_state(context
, &fb
);
143 si_release_all_descriptors(sctx
);
145 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
146 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
147 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
148 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
149 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
150 free(sctx
->border_color_table
);
151 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
152 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
153 r600_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
155 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
156 if (sctx
->init_config_gs_rings
)
157 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
158 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
159 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
161 if (sctx
->fixed_func_tcs_shader
.cso
)
162 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
163 if (sctx
->custom_dsa_flush
)
164 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
165 if (sctx
->custom_blend_resolve
)
166 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
167 if (sctx
->custom_blend_fmask_decompress
)
168 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
169 if (sctx
->custom_blend_eliminate_fastclear
)
170 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
171 if (sctx
->custom_blend_dcc_decompress
)
172 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
173 if (sctx
->vs_blit_pos
)
174 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
175 if (sctx
->vs_blit_pos_layered
)
176 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
177 if (sctx
->vs_blit_color
)
178 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
179 if (sctx
->vs_blit_color_layered
)
180 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
181 if (sctx
->vs_blit_texcoord
)
182 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
185 util_blitter_destroy(sctx
->blitter
);
187 /* Release DCC stats. */
188 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
189 assert(!sctx
->dcc_stats
[i
].query_active
);
191 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
192 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
193 sctx
->b
.destroy_query(&sctx
->b
,
194 sctx
->dcc_stats
[i
].ps_stats
[j
]);
196 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
199 if (sctx
->query_result_shader
)
200 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
203 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
205 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
207 sctx
->ws
->ctx_destroy(sctx
->ctx
);
209 if (sctx
->b
.stream_uploader
)
210 u_upload_destroy(sctx
->b
.stream_uploader
);
211 if (sctx
->b
.const_uploader
)
212 u_upload_destroy(sctx
->b
.const_uploader
);
213 if (sctx
->cached_gtt_allocator
)
214 u_upload_destroy(sctx
->cached_gtt_allocator
);
216 slab_destroy_child(&sctx
->pool_transfers
);
217 slab_destroy_child(&sctx
->pool_transfers_unsync
);
219 if (sctx
->allocator_zeroed_memory
)
220 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
222 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
223 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
224 r600_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
226 si_destroy_compiler(&sctx
->compiler
);
228 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
230 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
231 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
233 util_dynarray_fini(&sctx
->resident_tex_handles
);
234 util_dynarray_fini(&sctx
->resident_img_handles
);
235 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
236 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
237 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
241 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
243 struct si_context
*sctx
= (struct si_context
*)ctx
;
245 if (sctx
->screen
->info
.has_gpu_reset_status_query
)
246 return sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
248 if (sctx
->screen
->info
.has_gpu_reset_counter_query
) {
249 unsigned latest
= sctx
->ws
->query_value(sctx
->ws
,
250 RADEON_GPU_RESET_COUNTER
);
252 if (sctx
->gpu_reset_counter
== latest
)
253 return PIPE_NO_RESET
;
255 sctx
->gpu_reset_counter
= latest
;
256 return PIPE_UNKNOWN_CONTEXT_RESET
;
259 return PIPE_NO_RESET
;
262 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
263 const struct pipe_device_reset_callback
*cb
)
265 struct si_context
*sctx
= (struct si_context
*)ctx
;
268 sctx
->device_reset_callback
= *cb
;
270 memset(&sctx
->device_reset_callback
, 0,
271 sizeof(sctx
->device_reset_callback
));
274 bool si_check_device_reset(struct si_context
*sctx
)
276 enum pipe_reset_status status
;
278 if (!sctx
->device_reset_callback
.reset
)
281 if (!sctx
->b
.get_device_reset_status
)
284 status
= sctx
->b
.get_device_reset_status(&sctx
->b
);
285 if (status
== PIPE_NO_RESET
)
288 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
292 /* Apitrace profiling:
293 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
294 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
295 * and remember its number.
296 * 3) In Mesa, enable queries and performance counters around that draw
297 * call and print the results.
298 * 4) glretrace --benchmark --markers ..
300 static void si_emit_string_marker(struct pipe_context
*ctx
,
301 const char *string
, int len
)
303 struct si_context
*sctx
= (struct si_context
*)ctx
;
305 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
308 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
311 static void si_set_debug_callback(struct pipe_context
*ctx
,
312 const struct pipe_debug_callback
*cb
)
314 struct si_context
*sctx
= (struct si_context
*)ctx
;
315 struct si_screen
*screen
= sctx
->screen
;
317 util_queue_finish(&screen
->shader_compiler_queue
);
318 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
323 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
326 static void si_set_log_context(struct pipe_context
*ctx
,
327 struct u_log_context
*log
)
329 struct si_context
*sctx
= (struct si_context
*)ctx
;
333 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
336 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
339 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
340 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
341 struct radeon_winsys
*ws
= sscreen
->ws
;
347 if (flags
& PIPE_CONTEXT_DEBUG
)
348 sscreen
->record_llvm_ir
= true; /* racy but not critical */
350 sctx
->b
.screen
= screen
; /* this must be set first */
352 sctx
->b
.destroy
= si_destroy_context
;
353 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
354 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
355 sctx
->b
.set_log_context
= si_set_log_context
;
356 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
357 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
359 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
360 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
362 sctx
->ws
= sscreen
->ws
;
363 sctx
->family
= sscreen
->info
.family
;
364 sctx
->chip_class
= sscreen
->info
.chip_class
;
366 if (sscreen
->info
.has_gpu_reset_counter_query
) {
367 sctx
->gpu_reset_counter
=
368 sctx
->ws
->query_value(sctx
->ws
, RADEON_GPU_RESET_COUNTER
);
371 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
372 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
374 si_init_context_texture_functions(sctx
);
375 si_init_query_functions(sctx
);
377 if (sctx
->chip_class
== CIK
||
378 sctx
->chip_class
== VI
||
379 sctx
->chip_class
== GFX9
) {
380 sctx
->eop_bug_scratch
= r600_resource(
381 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
382 16 * sscreen
->info
.num_render_backends
));
383 if (!sctx
->eop_bug_scratch
)
387 sctx
->allocator_zeroed_memory
=
388 u_suballocator_create(&sctx
->b
, sscreen
->info
.gart_page_size
,
389 0, PIPE_USAGE_DEFAULT
, 0, true);
390 if (!sctx
->allocator_zeroed_memory
)
393 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
394 0, PIPE_USAGE_STREAM
,
395 SI_RESOURCE_FLAG_READ_ONLY
);
396 if (!sctx
->b
.stream_uploader
)
399 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 128 * 1024,
400 0, PIPE_USAGE_DEFAULT
,
401 SI_RESOURCE_FLAG_32BIT
|
402 (sscreen
->cpdma_prefetch_writes_memory
?
403 0 : SI_RESOURCE_FLAG_READ_ONLY
));
404 if (!sctx
->b
.const_uploader
)
407 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
408 0, PIPE_USAGE_STAGING
, 0);
409 if (!sctx
->cached_gtt_allocator
)
412 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
416 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
417 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
418 (void*)si_flush_dma_cs
,
422 si_init_buffer_functions(sctx
);
423 si_init_clear_functions(sctx
);
424 si_init_blit_functions(sctx
);
425 si_init_compute_functions(sctx
);
426 si_init_cp_dma_functions(sctx
);
427 si_init_debug_functions(sctx
);
428 si_init_msaa_functions(sctx
);
429 si_init_streamout_functions(sctx
);
431 if (sscreen
->info
.has_hw_decode
) {
432 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
433 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
435 sctx
->b
.create_video_codec
= vl_create_decoder
;
436 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
439 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
, RING_GFX
,
440 (void*)si_flush_gfx_cs
, sctx
);
443 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
444 sizeof(*sctx
->border_color_table
));
445 if (!sctx
->border_color_table
)
448 sctx
->border_color_buffer
= r600_resource(
449 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
450 SI_MAX_BORDER_COLORS
*
451 sizeof(*sctx
->border_color_table
)));
452 if (!sctx
->border_color_buffer
)
455 sctx
->border_color_map
=
456 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
457 NULL
, PIPE_TRANSFER_WRITE
);
458 if (!sctx
->border_color_map
)
461 si_init_all_descriptors(sctx
);
462 si_init_fence_functions(sctx
);
463 si_init_state_functions(sctx
);
464 si_init_shader_functions(sctx
);
465 si_init_viewport_functions(sctx
);
466 si_init_ia_multi_vgt_param_table(sctx
);
468 if (sctx
->chip_class
>= CIK
)
469 cik_init_sdma_functions(sctx
);
471 si_init_dma_functions(sctx
);
473 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
474 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
476 sctx
->blitter
= util_blitter_create(&sctx
->b
);
477 if (sctx
->blitter
== NULL
)
479 sctx
->blitter
->draw_rectangle
= si_draw_rectangle
;
480 sctx
->blitter
->skip_viewport_restore
= true;
482 sctx
->sample_mask
= 0xffff;
484 if (sctx
->chip_class
>= GFX9
) {
485 sctx
->wait_mem_scratch
= r600_resource(
486 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 4));
487 if (!sctx
->wait_mem_scratch
)
490 /* Initialize the memory. */
491 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
492 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
493 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
494 S_370_WR_CONFIRM(1) |
495 S_370_ENGINE_SEL(V_370_ME
));
496 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
);
497 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
>> 32);
498 radeon_emit(cs
, sctx
->wait_mem_number
);
499 radeon_add_to_buffer_list(sctx
, cs
, sctx
->wait_mem_scratch
,
500 RADEON_USAGE_WRITE
, RADEON_PRIO_FENCE
);
503 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
504 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
505 if (sctx
->chip_class
== CIK
) {
506 sctx
->null_const_buf
.buffer
=
507 pipe_aligned_buffer_create(screen
,
508 SI_RESOURCE_FLAG_32BIT
,
509 PIPE_USAGE_DEFAULT
, 16,
510 sctx
->screen
->info
.tcc_cache_line_size
);
511 if (!sctx
->null_const_buf
.buffer
)
513 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
515 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
516 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
517 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
518 &sctx
->null_const_buf
);
522 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
523 &sctx
->null_const_buf
);
524 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
525 &sctx
->null_const_buf
);
526 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
527 &sctx
->null_const_buf
);
528 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
529 &sctx
->null_const_buf
);
530 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
531 &sctx
->null_const_buf
);
533 /* Clear the NULL constant buffer, because loads should return zeros. */
534 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
535 sctx
->null_const_buf
.buffer
->width0
, 0,
536 SI_COHERENCY_SHADER
);
539 uint64_t max_threads_per_block
;
540 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
541 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
542 &max_threads_per_block
);
544 /* The maximum number of scratch waves. Scratch space isn't divided
545 * evenly between CUs. The number is only a function of the number of CUs.
546 * We can decrease the constant to decrease the scratch buffer size.
548 * sctx->scratch_waves must be >= the maximum posible size of
549 * 1 threadgroup, so that the hw doesn't hang from being unable
552 * The recommended value is 4 per CU at most. Higher numbers don't
553 * bring much benefit, but they still occupy chip resources (think
554 * async compute). I've seen ~2% performance difference between 4 and 32.
556 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
557 max_threads_per_block
/ 64);
559 si_init_compiler(sscreen
, &sctx
->compiler
);
561 /* Bindless handles. */
562 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
563 _mesa_key_pointer_equal
);
564 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
565 _mesa_key_pointer_equal
);
567 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
568 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
569 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
570 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
571 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
573 /* this must be last */
574 si_begin_new_gfx_cs(sctx
);
577 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
578 si_destroy_context(&sctx
->b
);
582 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
583 void *priv
, unsigned flags
)
585 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
586 struct pipe_context
*ctx
;
588 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
589 flags
|= PIPE_CONTEXT_DEBUG
;
591 ctx
= si_create_context(screen
, flags
);
593 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
596 /* Clover (compute-only) is unsupported. */
597 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
600 /* When shaders are logged to stderr, asynchronous compilation is
602 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
605 /* Use asynchronous flushes only on amdgpu, since the radeon
606 * implementation for fence_server_sync is incomplete. */
607 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
608 si_replace_buffer_storage
,
609 sscreen
->info
.drm_major
>= 3 ? si_create_fence
: NULL
,
610 &((struct si_context
*)ctx
)->tc
);
616 static void si_destroy_screen(struct pipe_screen
* pscreen
)
618 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
619 struct si_shader_part
*parts
[] = {
621 sscreen
->tcs_epilogs
,
628 if (!sscreen
->ws
->unref(sscreen
->ws
))
631 util_queue_destroy(&sscreen
->shader_compiler_queue
);
632 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
634 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
635 si_destroy_compiler(&sscreen
->compiler
[i
]);
637 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
638 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
640 /* Free shader parts. */
641 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
643 struct si_shader_part
*part
= parts
[i
];
645 parts
[i
] = part
->next
;
646 ac_shader_binary_clean(&part
->binary
);
650 mtx_destroy(&sscreen
->shader_parts_mutex
);
651 si_destroy_shader_cache(sscreen
);
653 si_perfcounters_destroy(sscreen
);
654 si_gpu_load_kill_thread(sscreen
);
656 mtx_destroy(&sscreen
->gpu_load_mutex
);
657 mtx_destroy(&sscreen
->aux_context_lock
);
658 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
660 slab_destroy_parent(&sscreen
->pool_transfers
);
662 disk_cache_destroy(sscreen
->disk_shader_cache
);
663 sscreen
->ws
->destroy(sscreen
->ws
);
667 static void si_init_gs_info(struct si_screen
*sscreen
)
669 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
670 sscreen
->info
.family
);
673 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
675 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
681 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
682 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
683 /* Override family and chip_class. */
684 sscreen
->info
.family
= i
;
686 if (i
>= CHIP_VEGA10
)
687 sscreen
->info
.chip_class
= GFX9
;
688 else if (i
>= CHIP_TONGA
)
689 sscreen
->info
.chip_class
= VI
;
690 else if (i
>= CHIP_BONAIRE
)
691 sscreen
->info
.chip_class
= CIK
;
693 sscreen
->info
.chip_class
= SI
;
695 /* Don't submit any IBs. */
696 setenv("RADEON_NOOP", "1", 1);
701 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
705 static void si_test_vmfault(struct si_screen
*sscreen
)
707 struct pipe_context
*ctx
= sscreen
->aux_context
;
708 struct si_context
*sctx
= (struct si_context
*)ctx
;
709 struct pipe_resource
*buf
=
710 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
713 puts("Buffer allocation failed.");
717 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
719 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
720 si_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0);
721 ctx
->flush(ctx
, NULL
, 0);
722 puts("VM fault test: CP - done.");
724 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
725 sctx
->dma_clear_buffer(sctx
, buf
, 0, 4, 0);
726 ctx
->flush(ctx
, NULL
, 0);
727 puts("VM fault test: SDMA - done.");
729 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
730 util_test_constant_buffer(ctx
, buf
);
731 puts("VM fault test: Shader - done.");
736 static void si_disk_cache_create(struct si_screen
*sscreen
)
738 /* Don't use the cache if shader dumping is enabled. */
739 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
742 uint32_t mesa_timestamp
;
743 if (disk_cache_get_function_timestamp(si_disk_cache_create
,
747 uint32_t llvm_timestamp
;
749 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
,
751 res
= asprintf(×tamp_str
, "%u_%u",
752 mesa_timestamp
, llvm_timestamp
);
756 /* These flags affect shader compilation. */
757 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
761 uint64_t shader_debug_flags
= sscreen
->debug_flags
&
764 /* Add the high bits of 32-bit addresses, which affects
765 * how 32-bit addresses are expanded to 64 bits.
767 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
768 shader_debug_flags
|= (uint64_t)sscreen
->info
.address32_hi
<< 32;
770 sscreen
->disk_shader_cache
=
771 disk_cache_create(si_get_family_name(sscreen
),
779 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
,
780 const struct pipe_screen_config
*config
)
782 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
783 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
, i
;
790 ws
->query_info(ws
, &sscreen
->info
);
792 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
795 /* Set functions first. */
796 sscreen
->b
.context_create
= si_pipe_create_context
;
797 sscreen
->b
.destroy
= si_destroy_screen
;
799 si_init_screen_get_functions(sscreen
);
800 si_init_screen_buffer_functions(sscreen
);
801 si_init_screen_fence_functions(sscreen
);
802 si_init_screen_state_functions(sscreen
);
803 si_init_screen_texture_functions(sscreen
);
804 si_init_screen_query_functions(sscreen
);
806 /* Set these flags in debug_flags early, so that the shader cache takes
809 if (driQueryOptionb(config
->options
,
810 "glsl_correct_derivatives_after_discard"))
811 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
812 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
813 sscreen
->debug_flags
|= DBG(SI_SCHED
);
816 if (sscreen
->debug_flags
& DBG(INFO
))
817 ac_print_gpu_info(&sscreen
->info
);
819 slab_create_parent(&sscreen
->pool_transfers
,
820 sizeof(struct si_transfer
), 64);
822 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
823 if (sscreen
->force_aniso
>= 0) {
824 printf("radeonsi: Forcing anisotropy filter to %ix\n",
825 /* round down to a power of two */
826 1 << util_logbase2(sscreen
->force_aniso
));
829 (void) mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
830 (void) mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
832 si_init_gs_info(sscreen
);
833 if (!si_init_shader_cache(sscreen
)) {
838 si_disk_cache_create(sscreen
);
840 /* Determine the number of shader compiler threads. */
841 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
843 if (hw_threads
>= 12) {
844 num_comp_hi_threads
= hw_threads
* 3 / 4;
845 num_comp_lo_threads
= hw_threads
/ 3;
846 } else if (hw_threads
>= 6) {
847 num_comp_hi_threads
= hw_threads
- 2;
848 num_comp_lo_threads
= hw_threads
/ 2;
849 } else if (hw_threads
>= 2) {
850 num_comp_hi_threads
= hw_threads
- 1;
851 num_comp_lo_threads
= hw_threads
/ 2;
853 num_comp_hi_threads
= 1;
854 num_comp_lo_threads
= 1;
857 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
858 ARRAY_SIZE(sscreen
->compiler
));
859 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
860 ARRAY_SIZE(sscreen
->compiler_lowp
));
862 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "sh",
863 64, num_comp_hi_threads
,
864 UTIL_QUEUE_INIT_RESIZE_IF_FULL
)) {
865 si_destroy_shader_cache(sscreen
);
870 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
872 64, num_comp_lo_threads
,
873 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
874 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
875 si_destroy_shader_cache(sscreen
);
880 si_handle_env_var_force_family(sscreen
);
882 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
883 si_init_perfcounters(sscreen
);
885 /* Determine tessellation ring info. */
886 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= CIK
&&
887 sscreen
->info
.family
!= CHIP_CARRIZO
&&
888 sscreen
->info
.family
!= CHIP_STONEY
;
889 /* This must be one less than the maximum number due to a hw limitation.
890 * Various hardware bugs in SI, CIK, and GFX9 need this.
892 unsigned max_offchip_buffers_per_se
;
894 /* Only certain chips can use the maximum value. */
895 if (sscreen
->info
.family
== CHIP_VEGA12
)
896 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
898 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
900 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
901 sscreen
->info
.max_se
;
902 unsigned offchip_granularity
;
904 /* Hawaii has a bug with offchip buffers > 256 that can be worked
905 * around by setting 4K granularity.
907 if (sscreen
->info
.family
== CHIP_HAWAII
) {
908 sscreen
->tess_offchip_block_dw_size
= 4096;
909 offchip_granularity
= V_03093C_X_4K_DWORDS
;
911 sscreen
->tess_offchip_block_dw_size
= 8192;
912 offchip_granularity
= V_03093C_X_8K_DWORDS
;
915 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
916 assert(((sscreen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
917 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
918 sscreen
->tess_offchip_block_dw_size
* 4;
920 if (sscreen
->info
.chip_class
>= CIK
) {
921 if (sscreen
->info
.chip_class
>= VI
)
922 --max_offchip_buffers
;
923 sscreen
->vgt_hs_offchip_param
=
924 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
925 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
927 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
928 sscreen
->vgt_hs_offchip_param
=
929 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
932 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
934 sscreen
->has_clear_state
= sscreen
->info
.chip_class
>= CIK
;
936 sscreen
->has_distributed_tess
=
937 sscreen
->info
.chip_class
>= VI
&&
938 sscreen
->info
.max_se
>= 2;
940 sscreen
->has_draw_indirect_multi
=
941 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
942 (sscreen
->info
.chip_class
== VI
&&
943 sscreen
->info
.pfp_fw_version
>= 121 &&
944 sscreen
->info
.me_fw_version
>= 87) ||
945 (sscreen
->info
.chip_class
== CIK
&&
946 sscreen
->info
.pfp_fw_version
>= 211 &&
947 sscreen
->info
.me_fw_version
>= 173) ||
948 (sscreen
->info
.chip_class
== SI
&&
949 sscreen
->info
.pfp_fw_version
>= 79 &&
950 sscreen
->info
.me_fw_version
>= 142);
952 sscreen
->has_out_of_order_rast
= sscreen
->info
.chip_class
>= VI
&&
953 sscreen
->info
.max_se
>= 2 &&
954 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
955 sscreen
->assume_no_z_fights
=
956 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
957 sscreen
->commutative_blend_add
=
958 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
959 sscreen
->clear_db_cache_before_clear
=
960 driQueryOptionb(config
->options
, "radeonsi_clear_db_cache_before_clear");
961 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->info
.family
>= CHIP_POLARIS10
&&
962 sscreen
->info
.family
<= CHIP_POLARIS12
) ||
963 sscreen
->info
.family
== CHIP_VEGA10
||
964 sscreen
->info
.family
== CHIP_RAVEN
;
965 sscreen
->has_ls_vgpr_init_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
966 sscreen
->info
.family
== CHIP_RAVEN
;
968 if (sscreen
->debug_flags
& DBG(DPBB
)) {
969 sscreen
->dpbb_allowed
= true;
971 /* Only enable primitive binning on Raven by default. */
972 /* TODO: Investigate if binning is profitable on Vega12. */
973 sscreen
->dpbb_allowed
= sscreen
->info
.family
== CHIP_RAVEN
&&
974 !(sscreen
->debug_flags
& DBG(NO_DPBB
));
977 if (sscreen
->debug_flags
& DBG(DFSM
)) {
978 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
;
980 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
&&
981 !(sscreen
->debug_flags
& DBG(NO_DFSM
));
984 /* While it would be nice not to have this flag, we are constrained
985 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
988 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
<= VI
;
990 /* Some chips have RB+ registers, but don't support RB+. Those must
993 if (sscreen
->info
.family
== CHIP_STONEY
||
994 sscreen
->info
.chip_class
>= GFX9
) {
995 sscreen
->has_rbplus
= true;
997 sscreen
->rbplus_allowed
=
998 !(sscreen
->debug_flags
& DBG(NO_RB_PLUS
)) &&
999 (sscreen
->info
.family
== CHIP_STONEY
||
1000 sscreen
->info
.family
== CHIP_VEGA12
||
1001 sscreen
->info
.family
== CHIP_RAVEN
);
1004 sscreen
->dcc_msaa_allowed
=
1005 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1007 sscreen
->cpdma_prefetch_writes_memory
= sscreen
->info
.chip_class
<= VI
;
1009 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1010 sscreen
->use_monolithic_shaders
=
1011 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1013 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
1014 SI_CONTEXT_INV_VMEM_L1
;
1015 if (sscreen
->info
.chip_class
<= VI
) {
1016 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_GLOBAL_L2
;
1017 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1020 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1021 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1028 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1030 * s >= z >= c (ignoring this only wastes memory)
1035 * Only MSAA color and depth buffers are overriden.
1037 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1038 const char *eqaa
= debug_get_option("EQAA", NULL
);
1041 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1042 sscreen
->eqaa_force_coverage_samples
= s
;
1043 sscreen
->eqaa_force_z_samples
= z
;
1044 sscreen
->eqaa_force_color_samples
= f
;
1048 for (i
= 0; i
< num_comp_hi_threads
; i
++)
1049 si_init_compiler(sscreen
, &sscreen
->compiler
[i
]);
1050 for (i
= 0; i
< num_comp_lo_threads
; i
++)
1051 si_init_compiler(sscreen
, &sscreen
->compiler_lowp
[i
]);
1053 /* Create the auxiliary context. This must be done last. */
1054 sscreen
->aux_context
= si_create_context(&sscreen
->b
, 0);
1056 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1057 si_test_dma(sscreen
);
1059 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1060 DBG(TEST_VMFAULT_SDMA
) |
1061 DBG(TEST_VMFAULT_SHADER
)))
1062 si_test_vmfault(sscreen
);