src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "vl/vl_decoder.h"
  34 #include "../ddebug/dd_util.h"
  35
  36 #define SI_LLVM_DEFAULT_FEATURES \
  37         "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals"
  38
  39 /*
  40  * pipe_context
  41  */
  42 static void si_destroy_context(struct pipe_context *context)
  43 {
  44         struct si_context *sctx = (struct si_context *)context;
  45         int i;
  46
  47         /* Unreference the framebuffer normally to disable related logic
  48          * properly.
  49          */
  50         struct pipe_framebuffer_state fb = {};
  51         context->set_framebuffer_state(context, &fb);
  52
  53         si_release_all_descriptors(sctx);
  54
  55         if (sctx->ce_suballocator)
  56                 u_suballocator_destroy(sctx->ce_suballocator);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67
  68         si_pm4_free_state(sctx, sctx->init_config, ~0);
  69         if (sctx->init_config_gs_rings)
  70                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  71         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  72                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  73
  74         if (sctx->fixed_func_tcs_shader.cso)
  75                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  76         if (sctx->custom_dsa_flush)
  77                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  78         if (sctx->custom_blend_resolve)
  79                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  80         if (sctx->custom_blend_decompress)
  81                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  82         if (sctx->custom_blend_fastclear)
  83                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  84         if (sctx->custom_blend_dcc_decompress)
  85                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  86
  87         if (sctx->blitter)
  88                 util_blitter_destroy(sctx->blitter);
  89
  90         r600_common_context_cleanup(&sctx->b);
  91
  92         LLVMDisposeTargetMachine(sctx->tm);
  93
  94         r600_resource_reference(&sctx->trace_buf, NULL);
  95         r600_resource_reference(&sctx->last_trace_buf, NULL);
  96         radeon_clear_saved_cs(&sctx->last_gfx);
  97
  98         FREE(sctx);
  99 }
 100
 101 static enum pipe_reset_status
 102 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 103 {
 104         struct si_context *sctx = (struct si_context *)ctx;
 105
 106         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 107 }
 108
 109 /* Apitrace profiling:
 110  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 111  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 112  *      and remember its number.
 113  *   3) In Mesa, enable queries and performance counters around that draw
 114  *      call and print the results.
 115  *   4) glretrace --benchmark --markers ..
 116  */
 117 static void si_emit_string_marker(struct pipe_context *ctx,
 118                                   const char *string, int len)
 119 {
 120         struct si_context *sctx = (struct si_context *)ctx;
 121
 122         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 123 }
 124
 125 static LLVMTargetMachineRef
 126 si_create_llvm_target_machine(struct si_screen *sscreen)
 127 {
 128         const char *triple = "amdgcn--";
 129
 130         return LLVMCreateTargetMachine(radeon_llvm_get_r600_target(triple), triple,
 131                                        r600_get_llvm_processor_name(sscreen->b.family),
 132 #if HAVE_LLVM >= 0x0308
 133                                        sscreen->b.debug_flags & DBG_SI_SCHED ?
 134                                                SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
 135 #endif
 136                                                SI_LLVM_DEFAULT_FEATURES,
 137                                        LLVMCodeGenLevelDefault,
 138                                        LLVMRelocDefault,
 139                                        LLVMCodeModelDefault);
 140 }
 141
 142 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 143                                               void *priv, unsigned flags)
 144 {
 145         struct si_context *sctx = CALLOC_STRUCT(si_context);
 146         struct si_screen* sscreen = (struct si_screen *)screen;
 147         struct radeon_winsys *ws = sscreen->b.ws;
 148         int shader, i;
 149
 150         if (!sctx)
 151                 return NULL;
 152
 153         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 154                 flags |= PIPE_CONTEXT_DEBUG;
 155
 156         if (flags & PIPE_CONTEXT_DEBUG)
 157                 sscreen->record_llvm_ir = true; /* racy but not critical */
 158
 159         sctx->b.b.screen = screen; /* this must be set first */
 160         sctx->b.b.priv = priv;
 161         sctx->b.b.destroy = si_destroy_context;
 162         sctx->b.b.emit_string_marker = si_emit_string_marker;
 163         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 164         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 165         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 166
 167         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 168                 goto fail;
 169
 170         if (sscreen->b.info.drm_major == 3)
 171                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 172
 173         si_init_blit_functions(sctx);
 174         si_init_compute_functions(sctx);
 175         si_init_cp_dma_functions(sctx);
 176         si_init_debug_functions(sctx);
 177
 178         if (sscreen->b.info.has_uvd) {
 179                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 180                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 181         } else {
 182                 sctx->b.b.create_video_codec = vl_create_decoder;
 183                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 184         }
 185
 186         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 187                                        si_context_gfx_flush, sctx);
 188
 189         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
 190                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 191                 if (!sctx->ce_ib)
 192                         goto fail;
 193
 194                 if (ws->cs_add_const_preamble_ib) {
 195                         sctx->ce_preamble_ib =
 196                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 197
 198                         if (!sctx->ce_preamble_ib)
 199                                 goto fail;
 200                 }
 201
 202                 sctx->ce_suballocator =
 203                                 u_suballocator_create(&sctx->b.b, 1024 * 1024,
 204                                                       PIPE_BIND_CUSTOM,
 205                                                       PIPE_USAGE_DEFAULT, false);
 206                 if (!sctx->ce_suballocator)
 207                         goto fail;
 208         }
 209
 210         sctx->b.gfx.flush = si_context_gfx_flush;
 211
 212         /* Border colors. */
 213         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 214                                           sizeof(*sctx->border_color_table));
 215         if (!sctx->border_color_table)
 216                 goto fail;
 217
 218         sctx->border_color_buffer = (struct r600_resource*)
 219                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 220                                    SI_MAX_BORDER_COLORS *
 221                                    sizeof(*sctx->border_color_table));
 222         if (!sctx->border_color_buffer)
 223                 goto fail;
 224
 225         sctx->border_color_map =
 226                 ws->buffer_map(sctx->border_color_buffer->buf,
 227                                NULL, PIPE_TRANSFER_WRITE);
 228         if (!sctx->border_color_map)
 229                 goto fail;
 230
 231         si_init_all_descriptors(sctx);
 232         si_init_state_functions(sctx);
 233         si_init_shader_functions(sctx);
 234
 235         if (sctx->b.chip_class >= CIK)
 236                 cik_init_sdma_functions(sctx);
 237         else
 238                 si_init_dma_functions(sctx);
 239
 240         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 241                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 242
 243         sctx->blitter = util_blitter_create(&sctx->b.b);
 244         if (sctx->blitter == NULL)
 245                 goto fail;
 246         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 247
 248         sctx->sample_mask.sample_mask = 0xffff;
 249
 250         /* these must be last */
 251         si_begin_new_cs(sctx);
 252         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 253
 254         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 255          * with a NULL buffer). We need to use a dummy buffer instead. */
 256         if (sctx->b.chip_class == CIK) {
 257                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 258                                                                  PIPE_USAGE_DEFAULT, 16);
 259                 if (!sctx->null_const_buf.buffer)
 260                         goto fail;
 261                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 262
 263                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 264                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 265                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 266                                                               &sctx->null_const_buf);
 267                         }
 268                 }
 269
 270                 /* Clear the NULL constant buffer, because loads should return zeros. */
 271                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 272                                      sctx->null_const_buf.buffer->width0, 0,
 273                                      R600_COHERENCY_SHADER);
 274         }
 275
 276         uint64_t max_threads_per_block;
 277         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 278                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 279                                   &max_threads_per_block);
 280
 281         /* The maximum number of scratch waves. Scratch space isn't divided
 282          * evenly between CUs. The number is only a function of the number of CUs.
 283          * We can decrease the constant to decrease the scratch buffer size.
 284          *
 285          * sctx->scratch_waves must be >= the maximum posible size of
 286          * 1 threadgroup, so that the hw doesn't hang from being unable
 287          * to start any.
 288          *
 289          * The recommended value is 4 per CU at most. Higher numbers don't
 290          * bring much benefit, but they still occupy chip resources (think
 291          * async compute). I've seen ~2% performance difference between 4 and 32.
 292          */
 293         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 294                                    max_threads_per_block / 64);
 295
 296         sctx->tm = si_create_llvm_target_machine(sscreen);
 297
 298         return &sctx->b.b;
 299 fail:
 300         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 301         si_destroy_context(&sctx->b.b);
 302         return NULL;
 303 }
 304
 305 /*
 306  * pipe_screen
 307  */
 308
 309 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 310 {
 311         struct si_screen *sscreen = (struct si_screen *)pscreen;
 312
 313         switch (param) {
 314         /* Supported features (boolean caps). */
 315         case PIPE_CAP_TWO_SIDED_STENCIL:
 316         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 317         case PIPE_CAP_ANISOTROPIC_FILTER:
 318         case PIPE_CAP_POINT_SPRITE:
 319         case PIPE_CAP_OCCLUSION_QUERY:
 320         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 321         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 322         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 323         case PIPE_CAP_TEXTURE_SWIZZLE:
 324         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 325         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 326         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 327         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 328         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 329         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 330         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 331         case PIPE_CAP_SM3:
 332         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 333         case PIPE_CAP_PRIMITIVE_RESTART:
 334         case PIPE_CAP_CONDITIONAL_RENDER:
 335         case PIPE_CAP_TEXTURE_BARRIER:
 336         case PIPE_CAP_INDEP_BLEND_ENABLE:
 337         case PIPE_CAP_INDEP_BLEND_FUNC:
 338         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 339         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 340         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 341         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 342         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 343         case PIPE_CAP_USER_INDEX_BUFFERS:
 344         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 345         case PIPE_CAP_START_INSTANCE:
 346         case PIPE_CAP_NPOT_TEXTURES:
 347         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 348         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 349         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 350         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 351         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 352         case PIPE_CAP_TGSI_INSTANCEID:
 353         case PIPE_CAP_COMPUTE:
 354         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 355         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 356         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 357         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 358         case PIPE_CAP_CUBE_MAP_ARRAY:
 359         case PIPE_CAP_SAMPLE_SHADING:
 360         case PIPE_CAP_DRAW_INDIRECT:
 361         case PIPE_CAP_CLIP_HALFZ:
 362         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 363         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 364         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 365         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 366         case PIPE_CAP_TGSI_TEXCOORD:
 367         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 368         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 369         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 370         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 371         case PIPE_CAP_SHAREABLE_SHADERS:
 372         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 373         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 374         case PIPE_CAP_TEXTURE_QUERY_LOD:
 375         case PIPE_CAP_TEXTURE_GATHER_SM5:
 376         case PIPE_CAP_TGSI_TXQS:
 377         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 378         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 379         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 380         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 381         case PIPE_CAP_INVALIDATE_BUFFER:
 382         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 383         case PIPE_CAP_QUERY_MEMORY_INFO:
 384         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 385         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 386         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 387         case PIPE_CAP_GENERATE_MIPMAP:
 388         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 389         case PIPE_CAP_STRING_MARKER:
 390         case PIPE_CAP_CLEAR_TEXTURE:
 391                 return 1;
 392
 393         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 394                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 395
 396         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 397                 return (sscreen->b.info.drm_major == 2 &&
 398                         sscreen->b.info.drm_minor >= 43) ||
 399                        sscreen->b.info.drm_major == 3;
 400
 401         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 402                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 403                 return sscreen->b.chip_class < CIK ||
 404                        (sscreen->b.info.drm_major == 2 &&
 405                         sscreen->b.info.drm_minor >= 35) ||
 406                        sscreen->b.info.drm_major == 3;
 407
 408         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 409                 return R600_MAP_BUFFER_ALIGNMENT;
 410
 411         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 412         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 413         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 414                 return 4;
 415         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 416                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 417
 418         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 419                 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
 420                                               PIPE_SHADER_CAP_SUPPORTED_IRS) &
 421                     (1 << PIPE_SHADER_IR_TGSI))
 422                         return 430;
 423                 return HAVE_LLVM >= 0x0309 ? 420 :
 424                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 425
 426         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 427                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 428
 429         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 430                 return 0;
 431
 432         /* Unsupported features. */
 433         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 434         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 435         case PIPE_CAP_USER_VERTEX_BUFFERS:
 436         case PIPE_CAP_FAKE_SW_MSAA:
 437         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 438         case PIPE_CAP_VERTEXID_NOBASE:
 439         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 440         case PIPE_CAP_CULL_DISTANCE:
 441         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 442         case PIPE_CAP_TGSI_VOTE:
 443         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 444                 return 0;
 445
 446         case PIPE_CAP_DRAW_PARAMETERS:
 447         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 448         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 449                 return sscreen->has_draw_indirect_multi;
 450
 451         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 452                 return 30;
 453
 454         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 455                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 456
 457         /* Stream output. */
 458         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 459                 return sscreen->b.has_streamout ? 4 : 0;
 460         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 461                 return sscreen->b.has_streamout ? 1 : 0;
 462         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 463         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 464                 return sscreen->b.has_streamout ? 32*4 : 0;
 465
 466         /* Geometry shader output. */
 467         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 468                 return 1024;
 469         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 470                 return 4095;
 471         case PIPE_CAP_MAX_VERTEX_STREAMS:
 472                 return 4;
 473
 474         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 475                 return 2048;
 476
 477         /* Texturing. */
 478         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 479         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 480                 return 15; /* 16384 */
 481         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 482                 /* textures support 8192, but layered rendering supports 2048 */
 483                 return 12;
 484         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 485                 /* textures support 8192, but layered rendering supports 2048 */
 486                 return 2048;
 487
 488         /* Render targets. */
 489         case PIPE_CAP_MAX_RENDER_TARGETS:
 490                 return 8;
 491
 492         case PIPE_CAP_MAX_VIEWPORTS:
 493                 return R600_MAX_VIEWPORTS;
 494         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 495                 return 8;
 496
 497         /* Timer queries, present when the clock frequency is non zero. */
 498         case PIPE_CAP_QUERY_TIMESTAMP:
 499         case PIPE_CAP_QUERY_TIME_ELAPSED:
 500                 return sscreen->b.info.clock_crystal_freq != 0;
 501
 502         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 503         case PIPE_CAP_MIN_TEXEL_OFFSET:
 504                 return -32;
 505
 506         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 507         case PIPE_CAP_MAX_TEXEL_OFFSET:
 508                 return 31;
 509
 510         case PIPE_CAP_ENDIANNESS:
 511                 return PIPE_ENDIAN_LITTLE;
 512
 513         case PIPE_CAP_VENDOR_ID:
 514                 return ATI_VENDOR_ID;
 515         case PIPE_CAP_DEVICE_ID:
 516                 return sscreen->b.info.pci_id;
 517         case PIPE_CAP_ACCELERATED:
 518                 return 1;
 519         case PIPE_CAP_VIDEO_MEMORY:
 520                 return sscreen->b.info.vram_size >> 20;
 521         case PIPE_CAP_UMA:
 522                 return 0;
 523         case PIPE_CAP_PCI_GROUP:
 524                 return sscreen->b.info.pci_domain;
 525         case PIPE_CAP_PCI_BUS:
 526                 return sscreen->b.info.pci_bus;
 527         case PIPE_CAP_PCI_DEVICE:
 528                 return sscreen->b.info.pci_dev;
 529         case PIPE_CAP_PCI_FUNCTION:
 530                 return sscreen->b.info.pci_func;
 531         }
 532         return 0;
 533 }
 534
 535 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 536 {
 537         struct si_screen *sscreen = (struct si_screen *)pscreen;
 538
 539         switch(shader)
 540         {
 541         case PIPE_SHADER_FRAGMENT:
 542         case PIPE_SHADER_VERTEX:
 543         case PIPE_SHADER_GEOMETRY:
 544                 break;
 545         case PIPE_SHADER_TESS_CTRL:
 546         case PIPE_SHADER_TESS_EVAL:
 547                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 548                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 549                         return 0;
 550                 break;
 551         case PIPE_SHADER_COMPUTE:
 552                 switch (param) {
 553                 case PIPE_SHADER_CAP_PREFERRED_IR:
 554                         return PIPE_SHADER_IR_NATIVE;
 555
 556                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 557                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 558
 559                         /* Old kernels disallowed some register writes for SI
 560                          * that are used for indirect dispatches. */
 561                         if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
 562                                                    sscreen->b.info.drm_major == 3 ||
 563                                                    (sscreen->b.info.drm_major == 2 &&
 564                                                     sscreen->b.info.drm_minor >= 45)))
 565                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 566
 567                         return ir;
 568                 }
 569                 case PIPE_SHADER_CAP_DOUBLES:
 570                         return HAVE_LLVM >= 0x0307;
 571
 572                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 573                         uint64_t max_const_buffer_size;
 574                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 575                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 576                                 &max_const_buffer_size);
 577                         return MIN2(max_const_buffer_size, INT_MAX);
 578                 }
 579                 default:
 580                         /* If compute shaders don't require a special value
 581                          * for this cap, we can return the same value we
 582                          * do for other shader types. */
 583                         break;
 584                 }
 585                 break;
 586         default:
 587                 return 0;
 588         }
 589
 590         switch (param) {
 591         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 592         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 593         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 594         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 595                 return 16384;
 596         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 597                 return 32;
 598         case PIPE_SHADER_CAP_MAX_INPUTS:
 599                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 600         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 601                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 602         case PIPE_SHADER_CAP_MAX_TEMPS:
 603                 return 256; /* Max native temporaries. */
 604         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 605                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 606         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 607                 return SI_NUM_CONST_BUFFERS;
 608         case PIPE_SHADER_CAP_MAX_PREDS:
 609                 return 0; /* FIXME */
 610         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 611                 return 1;
 612         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 613                 return 1;
 614         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 615                 /* Indirection of geometry shader input dimension is not
 616                  * handled yet
 617                  */
 618                 return shader != PIPE_SHADER_GEOMETRY;
 619         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 620         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 621         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 622                 return 1;
 623         case PIPE_SHADER_CAP_INTEGERS:
 624                 return 1;
 625         case PIPE_SHADER_CAP_SUBROUTINES:
 626                 return 0;
 627         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 628         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 629                 return SI_NUM_SAMPLERS;
 630         case PIPE_SHADER_CAP_PREFERRED_IR:
 631                 return PIPE_SHADER_IR_TGSI;
 632         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 633                 return 0;
 634         case PIPE_SHADER_CAP_DOUBLES:
 635                 return HAVE_LLVM >= 0x0307;
 636         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 637         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 638                 return 0;
 639         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 640         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 641                 return 1;
 642         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 643                 return 32;
 644         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 645                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 646         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 647                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 648         }
 649         return 0;
 650 }
 651
 652 static void si_destroy_screen(struct pipe_screen* pscreen)
 653 {
 654         struct si_screen *sscreen = (struct si_screen *)pscreen;
 655         struct si_shader_part *parts[] = {
 656                 sscreen->vs_prologs,
 657                 sscreen->vs_epilogs,
 658                 sscreen->tcs_epilogs,
 659                 sscreen->ps_prologs,
 660                 sscreen->ps_epilogs
 661         };
 662         unsigned i;
 663
 664         if (!sscreen)
 665                 return;
 666
 667         if (!sscreen->b.ws->unref(sscreen->b.ws))
 668                 return;
 669
 670         if (util_queue_is_initialized(&sscreen->shader_compiler_queue))
 671                 util_queue_destroy(&sscreen->shader_compiler_queue);
 672
 673         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 674                 if (sscreen->tm[i])
 675                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 676
 677         /* Free shader parts. */
 678         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 679                 while (parts[i]) {
 680                         struct si_shader_part *part = parts[i];
 681
 682                         parts[i] = part->next;
 683                         radeon_shader_binary_clean(&part->binary);
 684                         FREE(part);
 685                 }
 686         }
 687         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 688         si_destroy_shader_cache(sscreen);
 689         r600_destroy_common_screen(&sscreen->b);
 690 }
 691
 692 static bool si_init_gs_info(struct si_screen *sscreen)
 693 {
 694         switch (sscreen->b.family) {
 695         case CHIP_OLAND:
 696         case CHIP_HAINAN:
 697         case CHIP_KAVERI:
 698         case CHIP_KABINI:
 699         case CHIP_MULLINS:
 700         case CHIP_ICELAND:
 701         case CHIP_CARRIZO:
 702         case CHIP_STONEY:
 703                 sscreen->gs_table_depth = 16;
 704                 return true;
 705         case CHIP_TAHITI:
 706         case CHIP_PITCAIRN:
 707         case CHIP_VERDE:
 708         case CHIP_BONAIRE:
 709         case CHIP_HAWAII:
 710         case CHIP_TONGA:
 711         case CHIP_FIJI:
 712         case CHIP_POLARIS10:
 713         case CHIP_POLARIS11:
 714                 sscreen->gs_table_depth = 32;
 715                 return true;
 716         default:
 717                 return false;
 718         }
 719 }
 720
 721 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 722 {
 723         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 724         unsigned i;
 725
 726         if (!family)
 727                 return;
 728
 729         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 730                 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
 731                         /* Override family and chip_class. */
 732                         sscreen->b.family = sscreen->b.info.family = i;
 733
 734                         if (i >= CHIP_TONGA)
 735                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 736                         else if (i >= CHIP_BONAIRE)
 737                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 738                         else
 739                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 740
 741                         /* Don't submit any IBs. */
 742                         setenv("RADEON_NOOP", "1", 1);
 743                         return;
 744                 }
 745         }
 746
 747         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 748         exit(1);
 749 }
 750
 751 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 752 {
 753         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 754         unsigned num_cpus, num_compiler_threads, i;
 755
 756         if (!sscreen) {
 757                 return NULL;
 758         }
 759
 760         /* Set functions first. */
 761         sscreen->b.b.context_create = si_create_context;
 762         sscreen->b.b.destroy = si_destroy_screen;
 763         sscreen->b.b.get_param = si_get_param;
 764         sscreen->b.b.get_shader_param = si_get_shader_param;
 765         sscreen->b.b.resource_create = r600_resource_create_common;
 766
 767         si_init_screen_state_functions(sscreen);
 768
 769         if (!r600_common_screen_init(&sscreen->b, ws) ||
 770             !si_init_gs_info(sscreen) ||
 771             !si_init_shader_cache(sscreen)) {
 772                 FREE(sscreen);
 773                 return NULL;
 774         }
 775
 776         si_handle_env_var_force_family(sscreen);
 777
 778         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 779                 si_init_perfcounters(sscreen);
 780
 781         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 782          * around by setting 4K granularity.
 783          */
 784         sscreen->tess_offchip_block_dw_size =
 785                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
 786
 787         sscreen->has_distributed_tess =
 788                 sscreen->b.chip_class >= VI &&
 789                 sscreen->b.info.max_se >= 2;
 790
 791         sscreen->has_draw_indirect_multi =
 792                 (sscreen->b.family >= CHIP_POLARIS10) ||
 793                 (sscreen->b.chip_class == VI &&
 794                  sscreen->b.info.pfp_fw_version >= 121 &&
 795                  sscreen->b.info.me_fw_version >= 87) ||
 796                 (sscreen->b.chip_class == CIK &&
 797                  sscreen->b.info.pfp_fw_version >= 211 &&
 798                  sscreen->b.info.me_fw_version >= 173) ||
 799                 (sscreen->b.chip_class == SI &&
 800                  sscreen->b.info.pfp_fw_version >= 121 &&
 801                  sscreen->b.info.me_fw_version >= 87);
 802
 803         sscreen->b.has_cp_dma = true;
 804         sscreen->b.has_streamout = true;
 805         pipe_mutex_init(sscreen->shader_parts_mutex);
 806         sscreen->use_monolithic_shaders =
 807                 HAVE_LLVM < 0x0308 ||
 808                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 809
 810         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
 811                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 812
 813         /* Only enable as many threads as we have target machines and CPUs. */
 814         num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 815         num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
 816
 817         for (i = 0; i < num_compiler_threads; i++)
 818                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 819
 820         util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 821                         32, num_compiler_threads);
 822
 823         /* Create the auxiliary context. This must be done last. */
 824         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 825
 826         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 827                 r600_test_dma(&sscreen->b);
 828
 829         return &sscreen->b.b;
 830 }