src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "vl/vl_decoder.h"
  33
  34 /*
  35  * pipe_context
  36  */
  37 static void si_destroy_context(struct pipe_context *context)
  38 {
  39         struct si_context *sctx = (struct si_context *)context;
  40         int i;
  41
  42         si_release_all_descriptors(sctx);
  43
  44         pipe_resource_reference(&sctx->esgs_ring, NULL);
  45         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  46         pipe_resource_reference(&sctx->tf_ring, NULL);
  47         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  48         r600_resource_reference(&sctx->border_color_buffer, NULL);
  49         free(sctx->border_color_table);
  50         r600_resource_reference(&sctx->scratch_buffer, NULL);
  51         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  52
  53         si_pm4_free_state(sctx, sctx->init_config, ~0);
  54         if (sctx->init_config_gs_rings)
  55                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  56         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  57                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  58
  59         if (sctx->pstipple_sampler_state)
  60                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  61         if (sctx->fixed_func_tcs_shader.cso)
  62                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  63         if (sctx->custom_dsa_flush)
  64                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  65         if (sctx->custom_blend_resolve)
  66                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  67         if (sctx->custom_blend_decompress)
  68                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  69         if (sctx->custom_blend_fastclear)
  70                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  71         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  72
  73         if (sctx->blitter)
  74                 util_blitter_destroy(sctx->blitter);
  75
  76         r600_common_context_cleanup(&sctx->b);
  77
  78         LLVMDisposeTargetMachine(sctx->tm);
  79
  80         r600_resource_reference(&sctx->trace_buf, NULL);
  81         r600_resource_reference(&sctx->last_trace_buf, NULL);
  82         free(sctx->last_ib);
  83         if (sctx->last_bo_list) {
  84                 for (i = 0; i < sctx->last_bo_count; i++)
  85                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  86                 free(sctx->last_bo_list);
  87         }
  88         FREE(sctx);
  89 }
  90
  91 static enum pipe_reset_status
  92 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  93 {
  94         struct si_context *sctx = (struct si_context *)ctx;
  95
  96         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  97 }
  98
  99 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 100                                               void *priv, unsigned flags)
 101 {
 102         struct si_context *sctx = CALLOC_STRUCT(si_context);
 103         struct si_screen* sscreen = (struct si_screen *)screen;
 104         struct radeon_winsys *ws = sscreen->b.ws;
 105         LLVMTargetRef r600_target;
 106         const char *triple = "amdgcn--";
 107         int shader, i;
 108
 109         if (!sctx)
 110                 return NULL;
 111
 112         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 113                 flags |= PIPE_CONTEXT_DEBUG;
 114
 115         sctx->b.b.screen = screen; /* this must be set first */
 116         sctx->b.b.priv = priv;
 117         sctx->b.b.destroy = si_destroy_context;
 118         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 119         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 120         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 121
 122         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 123                 goto fail;
 124
 125         if (sscreen->b.info.drm_major == 3)
 126                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 127
 128         si_init_blit_functions(sctx);
 129         si_init_compute_functions(sctx);
 130         si_init_cp_dma_functions(sctx);
 131         si_init_debug_functions(sctx);
 132
 133         if (sscreen->b.info.has_uvd) {
 134                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 135                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 136         } else {
 137                 sctx->b.b.create_video_codec = vl_create_decoder;
 138                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 139         }
 140
 141         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 142                                        sctx, sscreen->b.trace_bo ?
 143                                                sscreen->b.trace_bo->buf : NULL);
 144         sctx->b.gfx.flush = si_context_gfx_flush;
 145
 146         /* Border colors. */
 147         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 148                                           sizeof(*sctx->border_color_table));
 149         if (!sctx->border_color_table)
 150                 goto fail;
 151
 152         sctx->border_color_buffer = (struct r600_resource*)
 153                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 154                                    SI_MAX_BORDER_COLORS *
 155                                    sizeof(*sctx->border_color_table));
 156         if (!sctx->border_color_buffer)
 157                 goto fail;
 158
 159         sctx->border_color_map =
 160                 ws->buffer_map(sctx->border_color_buffer->buf,
 161                                NULL, PIPE_TRANSFER_WRITE);
 162         if (!sctx->border_color_map)
 163                 goto fail;
 164
 165         si_init_all_descriptors(sctx);
 166         si_init_state_functions(sctx);
 167         si_init_shader_functions(sctx);
 168
 169         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 170                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 171
 172         sctx->blitter = util_blitter_create(&sctx->b.b);
 173         if (sctx->blitter == NULL)
 174                 goto fail;
 175         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 176
 177         sctx->sample_mask.sample_mask = 0xffff;
 178
 179         /* these must be last */
 180         si_begin_new_cs(sctx);
 181         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 182
 183         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 184          * with a NULL buffer). We need to use a dummy buffer instead. */
 185         if (sctx->b.chip_class == CIK) {
 186                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 187                                                                  PIPE_USAGE_DEFAULT, 16);
 188                 if (!sctx->null_const_buf.buffer)
 189                         goto fail;
 190                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 191
 192                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 193                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 194                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 195                                                               &sctx->null_const_buf);
 196                         }
 197                 }
 198
 199                 /* Clear the NULL constant buffer, because loads should return zeros. */
 200                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 201                                      sctx->null_const_buf.buffer->width0, 0, false);
 202         }
 203
 204         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 205          * this for non-cs shaders.  Using the wrong value here can result in
 206          * GPU lockups, but the maximum value seems to always work.
 207          */
 208         sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
 209
 210         /* Initialize LLVM TargetMachine */
 211         r600_target = radeon_llvm_get_r600_target(triple);
 212         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 213                                            r600_get_llvm_processor_name(sscreen->b.family),
 214 #if HAVE_LLVM >= 0x0308
 215                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 216                                                 "+DumpCode,+vgpr-spilling,+si-scheduler" :
 217 #endif
 218                                                 "+DumpCode,+vgpr-spilling",
 219                                            LLVMCodeGenLevelDefault,
 220                                            LLVMRelocDefault,
 221                                            LLVMCodeModelDefault);
 222
 223         return &sctx->b.b;
 224 fail:
 225         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 226         si_destroy_context(&sctx->b.b);
 227         return NULL;
 228 }
 229
 230 /*
 231  * pipe_screen
 232  */
 233
 234 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 235 {
 236         struct si_screen *sscreen = (struct si_screen *)pscreen;
 237
 238         switch (param) {
 239         /* Supported features (boolean caps). */
 240         case PIPE_CAP_TWO_SIDED_STENCIL:
 241         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 242         case PIPE_CAP_ANISOTROPIC_FILTER:
 243         case PIPE_CAP_POINT_SPRITE:
 244         case PIPE_CAP_OCCLUSION_QUERY:
 245         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 246         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 247         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 248         case PIPE_CAP_TEXTURE_SWIZZLE:
 249         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 250         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 251         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 252         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 253         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 254         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 255         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 256         case PIPE_CAP_SM3:
 257         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 258         case PIPE_CAP_PRIMITIVE_RESTART:
 259         case PIPE_CAP_CONDITIONAL_RENDER:
 260         case PIPE_CAP_TEXTURE_BARRIER:
 261         case PIPE_CAP_INDEP_BLEND_ENABLE:
 262         case PIPE_CAP_INDEP_BLEND_FUNC:
 263         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 264         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 265         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 266         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 267         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 268         case PIPE_CAP_USER_INDEX_BUFFERS:
 269         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 270         case PIPE_CAP_START_INSTANCE:
 271         case PIPE_CAP_NPOT_TEXTURES:
 272         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 273         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 274         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 275         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 276         case PIPE_CAP_TGSI_INSTANCEID:
 277         case PIPE_CAP_COMPUTE:
 278         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 279         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 280         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 281         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 282         case PIPE_CAP_CUBE_MAP_ARRAY:
 283         case PIPE_CAP_SAMPLE_SHADING:
 284         case PIPE_CAP_DRAW_INDIRECT:
 285         case PIPE_CAP_CLIP_HALFZ:
 286         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 287         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 288         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 289         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 290         case PIPE_CAP_TGSI_TEXCOORD:
 291         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 292         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 293         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 294         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 295         case PIPE_CAP_SHAREABLE_SHADERS:
 296         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 297         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 298         case PIPE_CAP_TEXTURE_QUERY_LOD:
 299         case PIPE_CAP_TEXTURE_GATHER_SM5:
 300         case PIPE_CAP_TGSI_TXQS:
 301         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 302         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 303         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 304         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 305         case PIPE_CAP_INVALIDATE_BUFFER:
 306         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 307         case PIPE_CAP_QUERY_MEMORY_INFO:
 308         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 309                 return 1;
 310
 311         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 312                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 313
 314         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 315                 return (sscreen->b.info.drm_major == 2 &&
 316                         sscreen->b.info.drm_minor >= 43) ||
 317                        sscreen->b.info.drm_major == 3;
 318
 319         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 320                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 321                 return sscreen->b.chip_class < CIK ||
 322                        (sscreen->b.info.drm_major == 2 &&
 323                         sscreen->b.info.drm_minor >= 35) ||
 324                        sscreen->b.info.drm_major == 3;
 325
 326         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 327                 return R600_MAP_BUFFER_ALIGNMENT;
 328
 329         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 330         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 331         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 332                 return 4;
 333
 334         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 335                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 336
 337         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 338                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 339
 340         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 341                 return 0;
 342
 343         /* Unsupported features. */
 344         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 345         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 346         case PIPE_CAP_USER_VERTEX_BUFFERS:
 347         case PIPE_CAP_FAKE_SW_MSAA:
 348         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 349         case PIPE_CAP_VERTEXID_NOBASE:
 350         case PIPE_CAP_CLEAR_TEXTURE:
 351         case PIPE_CAP_DRAW_PARAMETERS:
 352         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 353         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 354         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 355         case PIPE_CAP_GENERATE_MIPMAP:
 356         case PIPE_CAP_STRING_MARKER:
 357         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 358                 return 0;
 359
 360         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 361                 return 30;
 362
 363         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 364                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 365
 366         /* Stream output. */
 367         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 368                 return sscreen->b.has_streamout ? 4 : 0;
 369         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 370                 return sscreen->b.has_streamout ? 1 : 0;
 371         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 372         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 373                 return sscreen->b.has_streamout ? 32*4 : 0;
 374
 375         /* Geometry shader output. */
 376         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 377                 return 1024;
 378         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 379                 return 4095;
 380         case PIPE_CAP_MAX_VERTEX_STREAMS:
 381                 return 4;
 382
 383         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 384                 return 2048;
 385
 386         /* Texturing. */
 387         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 388         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 389                 return 15; /* 16384 */
 390         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 391                 /* textures support 8192, but layered rendering supports 2048 */
 392                 return 12;
 393         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 394                 /* textures support 8192, but layered rendering supports 2048 */
 395                 return 2048;
 396
 397         /* Render targets. */
 398         case PIPE_CAP_MAX_RENDER_TARGETS:
 399                 return 8;
 400
 401         case PIPE_CAP_MAX_VIEWPORTS:
 402                 return SI_MAX_VIEWPORTS;
 403
 404         /* Timer queries, present when the clock frequency is non zero. */
 405         case PIPE_CAP_QUERY_TIMESTAMP:
 406         case PIPE_CAP_QUERY_TIME_ELAPSED:
 407                 return sscreen->b.info.clock_crystal_freq != 0;
 408
 409         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 410         case PIPE_CAP_MIN_TEXEL_OFFSET:
 411                 return -32;
 412
 413         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 414         case PIPE_CAP_MAX_TEXEL_OFFSET:
 415                 return 31;
 416
 417         case PIPE_CAP_ENDIANNESS:
 418                 return PIPE_ENDIAN_LITTLE;
 419
 420         case PIPE_CAP_VENDOR_ID:
 421                 return 0x1002;
 422         case PIPE_CAP_DEVICE_ID:
 423                 return sscreen->b.info.pci_id;
 424         case PIPE_CAP_ACCELERATED:
 425                 return 1;
 426         case PIPE_CAP_VIDEO_MEMORY:
 427                 return sscreen->b.info.vram_size >> 20;
 428         case PIPE_CAP_UMA:
 429                 return 0;
 430         }
 431         return 0;
 432 }
 433
 434 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 435 {
 436         switch(shader)
 437         {
 438         case PIPE_SHADER_FRAGMENT:
 439         case PIPE_SHADER_VERTEX:
 440         case PIPE_SHADER_GEOMETRY:
 441                 break;
 442         case PIPE_SHADER_TESS_CTRL:
 443         case PIPE_SHADER_TESS_EVAL:
 444                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 445                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 446                         return 0;
 447                 break;
 448         case PIPE_SHADER_COMPUTE:
 449                 switch (param) {
 450                 case PIPE_SHADER_CAP_PREFERRED_IR:
 451                         return PIPE_SHADER_IR_NATIVE;
 452
 453                 case PIPE_SHADER_CAP_SUPPORTED_IRS:
 454                         return 0;
 455
 456                 case PIPE_SHADER_CAP_DOUBLES:
 457                         return HAVE_LLVM >= 0x0307;
 458
 459                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 460                         uint64_t max_const_buffer_size;
 461                         pscreen->get_compute_param(pscreen,
 462                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 463                                 &max_const_buffer_size);
 464                         return max_const_buffer_size;
 465                 }
 466                 default:
 467                         /* If compute shaders don't require a special value
 468                          * for this cap, we can return the same value we
 469                          * do for other shader types. */
 470                         break;
 471                 }
 472                 break;
 473         default:
 474                 return 0;
 475         }
 476
 477         switch (param) {
 478         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 479         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 480         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 481         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 482                 return 16384;
 483         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 484                 return 32;
 485         case PIPE_SHADER_CAP_MAX_INPUTS:
 486                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 487         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 488                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 489         case PIPE_SHADER_CAP_MAX_TEMPS:
 490                 return 256; /* Max native temporaries. */
 491         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 492                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 493         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 494                 return SI_NUM_USER_CONST_BUFFERS;
 495         case PIPE_SHADER_CAP_MAX_PREDS:
 496                 return 0; /* FIXME */
 497         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 498                 return 1;
 499         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 500                 return 1;
 501         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 502                 /* Indirection of geometry shader input dimension is not
 503                  * handled yet
 504                  */
 505                 return shader != PIPE_SHADER_GEOMETRY;
 506         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 507         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 508         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 509                 return 1;
 510         case PIPE_SHADER_CAP_INTEGERS:
 511                 return 1;
 512         case PIPE_SHADER_CAP_SUBROUTINES:
 513                 return 0;
 514         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 515         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 516                 return 16;
 517         case PIPE_SHADER_CAP_PREFERRED_IR:
 518                 return PIPE_SHADER_IR_TGSI;
 519         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 520                 return 0;
 521         case PIPE_SHADER_CAP_DOUBLES:
 522                 return HAVE_LLVM >= 0x0307;
 523         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 524         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 525                 return 0;
 526         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 527         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 528                 return 1;
 529         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 530                 return 32;
 531         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 532         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 533                 return 0;
 534         }
 535         return 0;
 536 }
 537
 538 static void si_destroy_screen(struct pipe_screen* pscreen)
 539 {
 540         struct si_screen *sscreen = (struct si_screen *)pscreen;
 541         struct si_shader_part *parts[] = {
 542                 sscreen->vs_prologs,
 543                 sscreen->vs_epilogs,
 544                 sscreen->tcs_epilogs,
 545                 sscreen->ps_prologs,
 546                 sscreen->ps_epilogs
 547         };
 548         unsigned i;
 549
 550         if (!sscreen)
 551                 return;
 552
 553         if (!sscreen->b.ws->unref(sscreen->b.ws))
 554                 return;
 555
 556         /* Free shader parts. */
 557         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 558                 while (parts[i]) {
 559                         struct si_shader_part *part = parts[i];
 560
 561                         parts[i] = part->next;
 562                         radeon_shader_binary_clean(&part->binary);
 563                         FREE(part);
 564                 }
 565         }
 566         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 567
 568         r600_destroy_common_screen(&sscreen->b);
 569 }
 570
 571 static bool si_init_gs_info(struct si_screen *sscreen)
 572 {
 573         switch (sscreen->b.family) {
 574         case CHIP_OLAND:
 575         case CHIP_HAINAN:
 576         case CHIP_KAVERI:
 577         case CHIP_KABINI:
 578         case CHIP_MULLINS:
 579         case CHIP_ICELAND:
 580         case CHIP_CARRIZO:
 581         case CHIP_STONEY:
 582                 sscreen->gs_table_depth = 16;
 583                 return true;
 584         case CHIP_TAHITI:
 585         case CHIP_PITCAIRN:
 586         case CHIP_VERDE:
 587         case CHIP_BONAIRE:
 588         case CHIP_HAWAII:
 589         case CHIP_TONGA:
 590         case CHIP_FIJI:
 591                 sscreen->gs_table_depth = 32;
 592                 return true;
 593         default:
 594                 return false;
 595         }
 596 }
 597
 598 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 599 {
 600         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 601
 602         if (!sscreen) {
 603                 return NULL;
 604         }
 605
 606         /* Set functions first. */
 607         sscreen->b.b.context_create = si_create_context;
 608         sscreen->b.b.destroy = si_destroy_screen;
 609         sscreen->b.b.get_param = si_get_param;
 610         sscreen->b.b.get_shader_param = si_get_shader_param;
 611         sscreen->b.b.is_format_supported = si_is_format_supported;
 612         sscreen->b.b.resource_create = r600_resource_create_common;
 613
 614         if (!r600_common_screen_init(&sscreen->b, ws) ||
 615             !si_init_gs_info(sscreen)) {
 616                 FREE(sscreen);
 617                 return NULL;
 618         }
 619
 620         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 621                 si_init_perfcounters(sscreen);
 622
 623         sscreen->b.has_cp_dma = true;
 624         sscreen->b.has_streamout = true;
 625         pipe_mutex_init(sscreen->shader_parts_mutex);
 626         sscreen->use_monolithic_shaders =
 627                 HAVE_LLVM < 0x0308 ||
 628                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 629
 630         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 631                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 632
 633         /* Create the auxiliary context. This must be done last. */
 634         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 635
 636         return &sscreen->b.b;
 637 }