src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "util/u_tests.h"
  34 #include "vl/vl_decoder.h"
  35 #include "../ddebug/dd_util.h"
  36
  37 #include "compiler/nir/nir.h"
  38
  39 /*
  40  * pipe_context
  41  */
  42 static void si_destroy_context(struct pipe_context *context)
  43 {
  44         struct si_context *sctx = (struct si_context *)context;
  45         int i;
  46
  47         /* Unreference the framebuffer normally to disable related logic
  48          * properly.
  49          */
  50         struct pipe_framebuffer_state fb = {};
  51         if (context->set_framebuffer_state)
  52                 context->set_framebuffer_state(context, &fb);
  53
  54         si_release_all_descriptors(sctx);
  55
  56         if (sctx->ce_suballocator)
  57                 u_suballocator_destroy(sctx->ce_suballocator);
  58
  59         r600_resource_reference(&sctx->ce_ram_saved_buffer, NULL);
  60         pipe_resource_reference(&sctx->esgs_ring, NULL);
  61         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  62         pipe_resource_reference(&sctx->tf_ring, NULL);
  63         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  64         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  65         r600_resource_reference(&sctx->border_color_buffer, NULL);
  66         free(sctx->border_color_table);
  67         r600_resource_reference(&sctx->scratch_buffer, NULL);
  68         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  69         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  70
  71         si_pm4_free_state(sctx, sctx->init_config, ~0);
  72         if (sctx->init_config_gs_rings)
  73                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  74         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  75                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  76
  77         if (sctx->fixed_func_tcs_shader.cso)
  78                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  79         if (sctx->custom_dsa_flush)
  80                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  81         if (sctx->custom_blend_resolve)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  83         if (sctx->custom_blend_fmask_decompress)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  85         if (sctx->custom_blend_eliminate_fastclear)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  87         if (sctx->custom_blend_dcc_decompress)
  88                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  89
  90         if (sctx->blitter)
  91                 util_blitter_destroy(sctx->blitter);
  92
  93         r600_common_context_cleanup(&sctx->b);
  94
  95         LLVMDisposeTargetMachine(sctx->tm);
  96
  97         r600_resource_reference(&sctx->trace_buf, NULL);
  98         r600_resource_reference(&sctx->last_trace_buf, NULL);
  99         radeon_clear_saved_cs(&sctx->last_gfx);
 100
 101         pb_slabs_deinit(&sctx->bindless_descriptor_slabs);
 102         util_dynarray_fini(&sctx->bindless_descriptors);
 103
 104         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 105         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 106
 107         util_dynarray_fini(&sctx->resident_tex_handles);
 108         util_dynarray_fini(&sctx->resident_img_handles);
 109         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 110         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 111         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 112         FREE(sctx);
 113 }
 114
 115 static enum pipe_reset_status
 116 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 117 {
 118         struct si_context *sctx = (struct si_context *)ctx;
 119
 120         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 121 }
 122
 123 /* Apitrace profiling:
 124  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 125  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 126  *      and remember its number.
 127  *   3) In Mesa, enable queries and performance counters around that draw
 128  *      call and print the results.
 129  *   4) glretrace --benchmark --markers ..
 130  */
 131 static void si_emit_string_marker(struct pipe_context *ctx,
 132                                   const char *string, int len)
 133 {
 134         struct si_context *sctx = (struct si_context *)ctx;
 135
 136         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 137 }
 138
 139 static LLVMTargetMachineRef
 140 si_create_llvm_target_machine(struct si_screen *sscreen)
 141 {
 142         const char *triple = "amdgcn--";
 143         char features[256];
 144
 145         snprintf(features, sizeof(features),
 146                  "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
 147                  sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
 148                  sscreen->llvm_has_working_vgpr_indexing ? "" : ",-promote-alloca",
 149                  sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
 150
 151         return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
 152                                        r600_get_llvm_processor_name(sscreen->b.family),
 153                                        features,
 154                                        LLVMCodeGenLevelDefault,
 155                                        LLVMRelocDefault,
 156                                        LLVMCodeModelDefault);
 157 }
 158
 159 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 160                                               unsigned flags)
 161 {
 162         struct si_context *sctx = CALLOC_STRUCT(si_context);
 163         struct si_screen* sscreen = (struct si_screen *)screen;
 164         struct radeon_winsys *ws = sscreen->b.ws;
 165         int shader, i;
 166
 167         if (!sctx)
 168                 return NULL;
 169
 170         if (flags & PIPE_CONTEXT_DEBUG)
 171                 sscreen->record_llvm_ir = true; /* racy but not critical */
 172
 173         sctx->b.b.screen = screen; /* this must be set first */
 174         sctx->b.b.priv = NULL;
 175         sctx->b.b.destroy = si_destroy_context;
 176         sctx->b.b.emit_string_marker = si_emit_string_marker;
 177         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 178         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 179         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 180
 181         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 182                 goto fail;
 183
 184         if (sscreen->b.info.drm_major == 3)
 185                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 186
 187         si_init_blit_functions(sctx);
 188         si_init_compute_functions(sctx);
 189         si_init_cp_dma_functions(sctx);
 190         si_init_debug_functions(sctx);
 191
 192         if (sscreen->b.info.has_hw_decode) {
 193                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 194                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 195         } else {
 196                 sctx->b.b.create_video_codec = vl_create_decoder;
 197                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 198         }
 199
 200         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 201                                        si_context_gfx_flush, sctx);
 202
 203         /* SI + AMDGPU + CE = GPU hang */
 204         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
 205             sscreen->b.chip_class != SI &&
 206             /* These can't use CE due to a power gating bug in the kernel. */
 207             sscreen->b.family != CHIP_CARRIZO &&
 208             sscreen->b.family != CHIP_STONEY) {
 209                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 210                 if (!sctx->ce_ib)
 211                         goto fail;
 212
 213                 if (ws->cs_add_const_preamble_ib) {
 214                         sctx->ce_preamble_ib =
 215                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 216
 217                         if (!sctx->ce_preamble_ib)
 218                                 goto fail;
 219                 }
 220
 221                 sctx->ce_suballocator =
 222                         u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
 223                                               PIPE_USAGE_DEFAULT,
 224                                               R600_RESOURCE_FLAG_UNMAPPABLE, false);
 225                 if (!sctx->ce_suballocator)
 226                         goto fail;
 227         }
 228
 229         sctx->b.gfx.flush = si_context_gfx_flush;
 230
 231         /* Border colors. */
 232         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 233                                           sizeof(*sctx->border_color_table));
 234         if (!sctx->border_color_table)
 235                 goto fail;
 236
 237         sctx->border_color_buffer = (struct r600_resource*)
 238                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 239                                    SI_MAX_BORDER_COLORS *
 240                                    sizeof(*sctx->border_color_table));
 241         if (!sctx->border_color_buffer)
 242                 goto fail;
 243
 244         sctx->border_color_map =
 245                 ws->buffer_map(sctx->border_color_buffer->buf,
 246                                NULL, PIPE_TRANSFER_WRITE);
 247         if (!sctx->border_color_map)
 248                 goto fail;
 249
 250         si_init_all_descriptors(sctx);
 251         si_init_state_functions(sctx);
 252         si_init_shader_functions(sctx);
 253         si_init_ia_multi_vgt_param_table(sctx);
 254
 255         if (sctx->b.chip_class >= CIK)
 256                 cik_init_sdma_functions(sctx);
 257         else
 258                 si_init_dma_functions(sctx);
 259
 260         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 261                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 262
 263         sctx->blitter = util_blitter_create(&sctx->b.b);
 264         if (sctx->blitter == NULL)
 265                 goto fail;
 266         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 267
 268         sctx->sample_mask.sample_mask = 0xffff;
 269
 270         /* these must be last */
 271         si_begin_new_cs(sctx);
 272
 273         if (sctx->b.chip_class >= GFX9) {
 274                 sctx->wait_mem_scratch = (struct r600_resource*)
 275                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 276                 if (!sctx->wait_mem_scratch)
 277                         goto fail;
 278
 279                 /* Initialize the memory. */
 280                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 281                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 282                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 283                             S_370_WR_CONFIRM(1) |
 284                             S_370_ENGINE_SEL(V_370_ME));
 285                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 286                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 287                 radeon_emit(cs, sctx->wait_mem_number);
 288         }
 289
 290         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 291          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 292         if (sctx->b.chip_class == CIK) {
 293                 sctx->null_const_buf.buffer =
 294                         r600_aligned_buffer_create(screen,
 295                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 296                                                    PIPE_USAGE_DEFAULT, 16,
 297                                                    sctx->screen->b.info.tcc_cache_line_size);
 298                 if (!sctx->null_const_buf.buffer)
 299                         goto fail;
 300                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 301
 302                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 303                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 304                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 305                                                               &sctx->null_const_buf);
 306                         }
 307                 }
 308
 309                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 310                                  &sctx->null_const_buf);
 311                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 312                                  &sctx->null_const_buf);
 313                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 314                                  &sctx->null_const_buf);
 315                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 316                                  &sctx->null_const_buf);
 317                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 318                                  &sctx->null_const_buf);
 319
 320                 /* Clear the NULL constant buffer, because loads should return zeros. */
 321                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 322                                      sctx->null_const_buf.buffer->width0, 0,
 323                                      R600_COHERENCY_SHADER);
 324         }
 325
 326         uint64_t max_threads_per_block;
 327         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 328                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 329                                   &max_threads_per_block);
 330
 331         /* The maximum number of scratch waves. Scratch space isn't divided
 332          * evenly between CUs. The number is only a function of the number of CUs.
 333          * We can decrease the constant to decrease the scratch buffer size.
 334          *
 335          * sctx->scratch_waves must be >= the maximum posible size of
 336          * 1 threadgroup, so that the hw doesn't hang from being unable
 337          * to start any.
 338          *
 339          * The recommended value is 4 per CU at most. Higher numbers don't
 340          * bring much benefit, but they still occupy chip resources (think
 341          * async compute). I've seen ~2% performance difference between 4 and 32.
 342          */
 343         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 344                                    max_threads_per_block / 64);
 345
 346         sctx->tm = si_create_llvm_target_machine(sscreen);
 347
 348         /* Create a slab allocator for all bindless descriptors. */
 349         if (!pb_slabs_init(&sctx->bindless_descriptor_slabs, 6, 6, 1, sctx,
 350                            si_bindless_descriptor_can_reclaim_slab,
 351                            si_bindless_descriptor_slab_alloc,
 352                            si_bindless_descriptor_slab_free))
 353                 goto fail;
 354
 355         util_dynarray_init(&sctx->bindless_descriptors, NULL);
 356
 357         /* Bindless handles. */
 358         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 359                                                     _mesa_key_pointer_equal);
 360         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 361                                                     _mesa_key_pointer_equal);
 362
 363         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 364         util_dynarray_init(&sctx->resident_img_handles, NULL);
 365         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 366         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 367         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 368
 369         return &sctx->b.b;
 370 fail:
 371         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 372         si_destroy_context(&sctx->b.b);
 373         return NULL;
 374 }
 375
 376 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 377                                                    void *priv, unsigned flags)
 378 {
 379         struct si_screen *sscreen = (struct si_screen *)screen;
 380         struct pipe_context *ctx;
 381
 382         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 383                 flags |= PIPE_CONTEXT_DEBUG;
 384
 385         ctx = si_create_context(screen, flags);
 386
 387         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 388                 return ctx;
 389
 390         /* Clover (compute-only) is unsupported.
 391          *
 392          * Since the threaded context creates shader states from the non-driver
 393          * thread, asynchronous compilation is required for create_{shader}_-
 394          * state not to use pipe_context. Debug contexts (ddebug) disable
 395          * asynchronous compilation, so don't use the threaded context with
 396          * those.
 397          */
 398         if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
 399                 return ctx;
 400
 401         /* When shaders are logged to stderr, asynchronous compilation is
 402          * disabled too. */
 403         if (sscreen->b.debug_flags & (DBG_VS | DBG_TCS | DBG_TES | DBG_GS |
 404                                       DBG_PS | DBG_CS))
 405                 return ctx;
 406
 407         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 408                                        r600_replace_buffer_storage,
 409                                        &((struct si_context*)ctx)->b.tc);
 410 }
 411
 412 /*
 413  * pipe_screen
 414  */
 415 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 416 {
 417         /* Old kernels disallowed some register writes for SI
 418          * that are used for indirect dispatches. */
 419         return (sscreen->b.chip_class >= CIK ||
 420                 sscreen->b.info.drm_major == 3 ||
 421                 (sscreen->b.info.drm_major == 2 &&
 422                  sscreen->b.info.drm_minor >= 45));
 423 }
 424
 425 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 426 {
 427         struct si_screen *sscreen = (struct si_screen *)pscreen;
 428
 429         switch (param) {
 430         /* Supported features (boolean caps). */
 431         case PIPE_CAP_ACCELERATED:
 432         case PIPE_CAP_TWO_SIDED_STENCIL:
 433         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 434         case PIPE_CAP_ANISOTROPIC_FILTER:
 435         case PIPE_CAP_POINT_SPRITE:
 436         case PIPE_CAP_OCCLUSION_QUERY:
 437         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 438         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 439         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 440         case PIPE_CAP_TEXTURE_SWIZZLE:
 441         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 442         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 443         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 444         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 445         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 446         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 447         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 448         case PIPE_CAP_SM3:
 449         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 450         case PIPE_CAP_PRIMITIVE_RESTART:
 451         case PIPE_CAP_CONDITIONAL_RENDER:
 452         case PIPE_CAP_TEXTURE_BARRIER:
 453         case PIPE_CAP_INDEP_BLEND_ENABLE:
 454         case PIPE_CAP_INDEP_BLEND_FUNC:
 455         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 456         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 457         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 458         case PIPE_CAP_START_INSTANCE:
 459         case PIPE_CAP_NPOT_TEXTURES:
 460         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 461         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 462         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 463         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 464         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 465         case PIPE_CAP_TGSI_INSTANCEID:
 466         case PIPE_CAP_COMPUTE:
 467         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 468         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 469         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 470         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 471         case PIPE_CAP_CUBE_MAP_ARRAY:
 472         case PIPE_CAP_SAMPLE_SHADING:
 473         case PIPE_CAP_DRAW_INDIRECT:
 474         case PIPE_CAP_CLIP_HALFZ:
 475         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 476         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 477         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 478         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 479         case PIPE_CAP_TGSI_TEXCOORD:
 480         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 481         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 482         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 483         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 484         case PIPE_CAP_SHAREABLE_SHADERS:
 485         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 486         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 487         case PIPE_CAP_TEXTURE_QUERY_LOD:
 488         case PIPE_CAP_TEXTURE_GATHER_SM5:
 489         case PIPE_CAP_TGSI_TXQS:
 490         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 491         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 492         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 493         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 494         case PIPE_CAP_INVALIDATE_BUFFER:
 495         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 496         case PIPE_CAP_QUERY_MEMORY_INFO:
 497         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 498         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 499         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 500         case PIPE_CAP_GENERATE_MIPMAP:
 501         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 502         case PIPE_CAP_STRING_MARKER:
 503         case PIPE_CAP_CLEAR_TEXTURE:
 504         case PIPE_CAP_CULL_DISTANCE:
 505         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 506         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 507         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 508         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 509         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 510         case PIPE_CAP_DOUBLES:
 511         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 512         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 513         case PIPE_CAP_BINDLESS_TEXTURE:
 514         case PIPE_CAP_QUERY_TIMESTAMP:
 515         case PIPE_CAP_QUERY_TIME_ELAPSED:
 516         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 517                 return 1;
 518
 519         case PIPE_CAP_INT64:
 520         case PIPE_CAP_INT64_DIVMOD:
 521         case PIPE_CAP_TGSI_CLOCK:
 522         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 523         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 524                 return 1;
 525
 526         case PIPE_CAP_TGSI_VOTE:
 527                 return HAVE_LLVM >= 0x0400;
 528
 529         case PIPE_CAP_TGSI_BALLOT:
 530                 return HAVE_LLVM >= 0x0500;
 531
 532         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 533                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 534
 535         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 536                 return (sscreen->b.info.drm_major == 2 &&
 537                         sscreen->b.info.drm_minor >= 43) ||
 538                        sscreen->b.info.drm_major == 3;
 539
 540         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 541                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 542                 return sscreen->b.chip_class < CIK ||
 543                        (sscreen->b.info.drm_major == 2 &&
 544                         sscreen->b.info.drm_minor >= 35) ||
 545                        sscreen->b.info.drm_major == 3;
 546
 547         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 548                 return R600_MAP_BUFFER_ALIGNMENT;
 549
 550         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 551         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 552         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 553         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 554         case PIPE_CAP_MAX_VERTEX_STREAMS:
 555         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 556                 return 4;
 557
 558         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 559                 if (sscreen->b.debug_flags & DBG_NIR)
 560                         return 140; /* no geometry and tessellation shaders yet */
 561                 if (si_have_tgsi_compute(sscreen))
 562                         return 450;
 563                 return 420;
 564
 565         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 566                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 567
 568         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 569         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 570         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 571                 /* SI doesn't support unaligned loads.
 572                  * CIK needs DRM 2.50.0 on radeon. */
 573                 return sscreen->b.chip_class == SI ||
 574                        (sscreen->b.info.drm_major == 2 &&
 575                         sscreen->b.info.drm_minor < 50);
 576
 577         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 578                 /* TODO: GFX9 hangs. */
 579                 if (sscreen->b.chip_class >= GFX9)
 580                         return 0;
 581                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 582                  * faults are mitigated in software.
 583                  */
 584                 if (sscreen->b.chip_class >= CIK &&
 585                     sscreen->b.info.drm_major == 3 &&
 586                     sscreen->b.info.drm_minor >= 13)
 587                         return RADEON_SPARSE_PAGE_SIZE;
 588                 return 0;
 589
 590         /* Unsupported features. */
 591         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 592         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 593         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 594         case PIPE_CAP_USER_VERTEX_BUFFERS:
 595         case PIPE_CAP_FAKE_SW_MSAA:
 596         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 597         case PIPE_CAP_VERTEXID_NOBASE:
 598         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 599         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 600         case PIPE_CAP_NATIVE_FENCE_FD:
 601         case PIPE_CAP_TGSI_FS_FBFETCH:
 602         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 603         case PIPE_CAP_UMA:
 604         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 605         case PIPE_CAP_POST_DEPTH_COVERAGE:
 606         case PIPE_CAP_QUERY_SO_OVERFLOW:
 607                 return 0;
 608
 609         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 610                 return si_have_tgsi_compute(sscreen);
 611
 612         case PIPE_CAP_DRAW_PARAMETERS:
 613         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 614         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 615                 return sscreen->has_draw_indirect_multi;
 616
 617         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 618                 return 30;
 619
 620         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 621                 return sscreen->b.chip_class <= VI ?
 622                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 623
 624         /* Stream output. */
 625         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 626         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 627                 return 32*4;
 628
 629         /* Geometry shader output. */
 630         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 631                 return 1024;
 632         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 633                 return 4095;
 634
 635         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 636                 return 2048;
 637
 638         /* Texturing. */
 639         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 640         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 641                 return 15; /* 16384 */
 642         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 643                 /* textures support 8192, but layered rendering supports 2048 */
 644                 return 12;
 645         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 646                 /* textures support 8192, but layered rendering supports 2048 */
 647                 return 2048;
 648
 649         /* Viewports and render targets. */
 650         case PIPE_CAP_MAX_VIEWPORTS:
 651                 return R600_MAX_VIEWPORTS;
 652         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 653         case PIPE_CAP_MAX_RENDER_TARGETS:
 654                 return 8;
 655
 656         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 657         case PIPE_CAP_MIN_TEXEL_OFFSET:
 658                 return -32;
 659
 660         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 661         case PIPE_CAP_MAX_TEXEL_OFFSET:
 662                 return 31;
 663
 664         case PIPE_CAP_ENDIANNESS:
 665                 return PIPE_ENDIAN_LITTLE;
 666
 667         case PIPE_CAP_VENDOR_ID:
 668                 return ATI_VENDOR_ID;
 669         case PIPE_CAP_DEVICE_ID:
 670                 return sscreen->b.info.pci_id;
 671         case PIPE_CAP_VIDEO_MEMORY:
 672                 return sscreen->b.info.vram_size >> 20;
 673         case PIPE_CAP_PCI_GROUP:
 674                 return sscreen->b.info.pci_domain;
 675         case PIPE_CAP_PCI_BUS:
 676                 return sscreen->b.info.pci_bus;
 677         case PIPE_CAP_PCI_DEVICE:
 678                 return sscreen->b.info.pci_dev;
 679         case PIPE_CAP_PCI_FUNCTION:
 680                 return sscreen->b.info.pci_func;
 681         }
 682         return 0;
 683 }
 684
 685 static int si_get_shader_param(struct pipe_screen* pscreen,
 686                                enum pipe_shader_type shader,
 687                                enum pipe_shader_cap param)
 688 {
 689         struct si_screen *sscreen = (struct si_screen *)pscreen;
 690
 691         switch(shader)
 692         {
 693         case PIPE_SHADER_FRAGMENT:
 694         case PIPE_SHADER_VERTEX:
 695         case PIPE_SHADER_GEOMETRY:
 696         case PIPE_SHADER_TESS_CTRL:
 697         case PIPE_SHADER_TESS_EVAL:
 698                 break;
 699         case PIPE_SHADER_COMPUTE:
 700                 switch (param) {
 701                 case PIPE_SHADER_CAP_PREFERRED_IR:
 702                         return PIPE_SHADER_IR_NATIVE;
 703
 704                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 705                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 706
 707                         if (si_have_tgsi_compute(sscreen))
 708                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 709
 710                         return ir;
 711                 }
 712
 713                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 714                         uint64_t max_const_buffer_size;
 715                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 716                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 717                                 &max_const_buffer_size);
 718                         return MIN2(max_const_buffer_size, INT_MAX);
 719                 }
 720                 default:
 721                         /* If compute shaders don't require a special value
 722                          * for this cap, we can return the same value we
 723                          * do for other shader types. */
 724                         break;
 725                 }
 726                 break;
 727         default:
 728                 return 0;
 729         }
 730
 731         switch (param) {
 732         /* Shader limits. */
 733         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 734         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 735         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 736         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 737         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 738                 return 16384;
 739         case PIPE_SHADER_CAP_MAX_INPUTS:
 740                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 741         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 742                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 743         case PIPE_SHADER_CAP_MAX_TEMPS:
 744                 return 256; /* Max native temporaries. */
 745         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 746                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 747         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 748                 return SI_NUM_CONST_BUFFERS;
 749         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 750         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 751                 return SI_NUM_SAMPLERS;
 752         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 753                 return SI_NUM_SHADER_BUFFERS;
 754         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 755                 return SI_NUM_IMAGES;
 756         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 757                 return 32;
 758         case PIPE_SHADER_CAP_PREFERRED_IR:
 759                 if (sscreen->b.debug_flags & DBG_NIR &&
 760                     (shader == PIPE_SHADER_VERTEX ||
 761                      shader == PIPE_SHADER_FRAGMENT))
 762                         return PIPE_SHADER_IR_NIR;
 763                 return PIPE_SHADER_IR_TGSI;
 764         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 765                 return 3;
 766
 767         /* Supported boolean features. */
 768         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 769         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 770         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 771         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 772         case PIPE_SHADER_CAP_INTEGERS:
 773         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 774         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 775         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 776                 return 1;
 777
 778         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 779                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 780                 return shader != PIPE_SHADER_GEOMETRY &&
 781                        (sscreen->llvm_has_working_vgpr_indexing ||
 782                         /* TCS and TES load inputs directly from LDS or
 783                          * offchip memory, so indirect indexing is trivial. */
 784                         shader == PIPE_SHADER_TESS_CTRL ||
 785                         shader == PIPE_SHADER_TESS_EVAL);
 786
 787         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 788                 return sscreen->llvm_has_working_vgpr_indexing ||
 789                        /* TCS stores outputs directly to memory. */
 790                        shader == PIPE_SHADER_TESS_CTRL;
 791
 792         /* Unsupported boolean features. */
 793         case PIPE_SHADER_CAP_SUBROUTINES:
 794         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 795         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 796         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 797                 return 0;
 798         }
 799         return 0;
 800 }
 801
 802 static const struct nir_shader_compiler_options nir_options = {
 803         .vertex_id_zero_based = true,
 804         .lower_scmp = true,
 805         .lower_flrp32 = true,
 806         .lower_fsat = true,
 807         .lower_fdiv = true,
 808         .lower_sub = true,
 809         .lower_pack_snorm_2x16 = true,
 810         .lower_pack_snorm_4x8 = true,
 811         .lower_pack_unorm_2x16 = true,
 812         .lower_pack_unorm_4x8 = true,
 813         .lower_unpack_snorm_2x16 = true,
 814         .lower_unpack_snorm_4x8 = true,
 815         .lower_unpack_unorm_2x16 = true,
 816         .lower_unpack_unorm_4x8 = true,
 817         .lower_extract_byte = true,
 818         .lower_extract_word = true,
 819         .max_unroll_iterations = 32,
 820         .native_integers = true,
 821 };
 822
 823 static const void *
 824 si_get_compiler_options(struct pipe_screen *screen,
 825                         enum pipe_shader_ir ir,
 826                         enum pipe_shader_type shader)
 827 {
 828         assert(ir == PIPE_SHADER_IR_NIR);
 829         return &nir_options;
 830 }
 831
 832 static void si_destroy_screen(struct pipe_screen* pscreen)
 833 {
 834         struct si_screen *sscreen = (struct si_screen *)pscreen;
 835         struct si_shader_part *parts[] = {
 836                 sscreen->vs_prologs,
 837                 sscreen->tcs_epilogs,
 838                 sscreen->gs_prologs,
 839                 sscreen->ps_prologs,
 840                 sscreen->ps_epilogs
 841         };
 842         unsigned i;
 843
 844         if (!sscreen->b.ws->unref(sscreen->b.ws))
 845                 return;
 846
 847         util_queue_destroy(&sscreen->shader_compiler_queue);
 848         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 849
 850         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 851                 if (sscreen->tm[i])
 852                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 853
 854         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 855                 if (sscreen->tm_low_priority[i])
 856                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 857
 858         /* Free shader parts. */
 859         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 860                 while (parts[i]) {
 861                         struct si_shader_part *part = parts[i];
 862
 863                         parts[i] = part->next;
 864                         radeon_shader_binary_clean(&part->binary);
 865                         FREE(part);
 866                 }
 867         }
 868         mtx_destroy(&sscreen->shader_parts_mutex);
 869         si_destroy_shader_cache(sscreen);
 870         r600_destroy_common_screen(&sscreen->b);
 871 }
 872
 873 static bool si_init_gs_info(struct si_screen *sscreen)
 874 {
 875         switch (sscreen->b.family) {
 876         case CHIP_OLAND:
 877         case CHIP_HAINAN:
 878         case CHIP_KAVERI:
 879         case CHIP_KABINI:
 880         case CHIP_MULLINS:
 881         case CHIP_ICELAND:
 882         case CHIP_CARRIZO:
 883         case CHIP_STONEY:
 884                 sscreen->gs_table_depth = 16;
 885                 return true;
 886         case CHIP_TAHITI:
 887         case CHIP_PITCAIRN:
 888         case CHIP_VERDE:
 889         case CHIP_BONAIRE:
 890         case CHIP_HAWAII:
 891         case CHIP_TONGA:
 892         case CHIP_FIJI:
 893         case CHIP_POLARIS10:
 894         case CHIP_POLARIS11:
 895         case CHIP_POLARIS12:
 896         case CHIP_VEGA10:
 897         case CHIP_RAVEN:
 898                 sscreen->gs_table_depth = 32;
 899                 return true;
 900         default:
 901                 return false;
 902         }
 903 }
 904
 905 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 906 {
 907         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 908         unsigned i;
 909
 910         if (!family)
 911                 return;
 912
 913         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 914                 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
 915                         /* Override family and chip_class. */
 916                         sscreen->b.family = sscreen->b.info.family = i;
 917
 918                         if (i >= CHIP_VEGA10)
 919                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 920                         else if (i >= CHIP_TONGA)
 921                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 922                         else if (i >= CHIP_BONAIRE)
 923                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 924                         else
 925                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 926
 927                         /* Don't submit any IBs. */
 928                         setenv("RADEON_NOOP", "1", 1);
 929                         return;
 930                 }
 931         }
 932
 933         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 934         exit(1);
 935 }
 936
 937 static void si_test_vmfault(struct si_screen *sscreen)
 938 {
 939         struct pipe_context *ctx = sscreen->b.aux_context;
 940         struct si_context *sctx = (struct si_context *)ctx;
 941         struct pipe_resource *buf =
 942                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 943
 944         if (!buf) {
 945                 puts("Buffer allocation failed.");
 946                 exit(1);
 947         }
 948
 949         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 950
 951         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
 952                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 953                 ctx->flush(ctx, NULL, 0);
 954                 puts("VM fault test: CP - done.");
 955         }
 956         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
 957                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 958                 ctx->flush(ctx, NULL, 0);
 959                 puts("VM fault test: SDMA - done.");
 960         }
 961         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
 962                 util_test_constant_buffer(ctx, buf);
 963                 puts("VM fault test: Shader - done.");
 964         }
 965         exit(0);
 966 }
 967
 968 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 969                                            unsigned flags)
 970 {
 971         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 972         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 973
 974         if (!sscreen) {
 975                 return NULL;
 976         }
 977
 978         /* Set functions first. */
 979         sscreen->b.b.context_create = si_pipe_create_context;
 980         sscreen->b.b.destroy = si_destroy_screen;
 981         sscreen->b.b.get_param = si_get_param;
 982         sscreen->b.b.get_shader_param = si_get_shader_param;
 983         sscreen->b.b.get_compiler_options = si_get_compiler_options;
 984         sscreen->b.b.resource_create = r600_resource_create_common;
 985
 986         si_init_screen_state_functions(sscreen);
 987
 988         if (!r600_common_screen_init(&sscreen->b, ws, flags) ||
 989             !si_init_gs_info(sscreen) ||
 990             !si_init_shader_cache(sscreen)) {
 991                 FREE(sscreen);
 992                 return NULL;
 993         }
 994
 995         /* Only enable as many threads as we have target machines, but at most
 996          * the number of CPUs - 1 if there is more than one.
 997          */
 998         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
 999         num_threads = MAX2(1, num_threads - 1);
1000         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1001         num_compiler_threads_lowprio =
1002                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1003
1004         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1005                              32, num_compiler_threads,
1006                              UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1007                 si_destroy_shader_cache(sscreen);
1008                 FREE(sscreen);
1009                 return NULL;
1010         }
1011
1012         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1013                              "si_shader_low",
1014                              32, num_compiler_threads_lowprio,
1015                              UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1016                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1017                si_destroy_shader_cache(sscreen);
1018                FREE(sscreen);
1019                return NULL;
1020         }
1021
1022         si_handle_env_var_force_family(sscreen);
1023
1024         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1025                 si_init_perfcounters(sscreen);
1026
1027         /* Hawaii has a bug with offchip buffers > 256 that can be worked
1028          * around by setting 4K granularity.
1029          */
1030         sscreen->tess_offchip_block_dw_size =
1031                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1032
1033         sscreen->has_distributed_tess =
1034                 sscreen->b.chip_class >= VI &&
1035                 sscreen->b.info.max_se >= 2;
1036
1037         sscreen->has_draw_indirect_multi =
1038                 (sscreen->b.family >= CHIP_POLARIS10) ||
1039                 (sscreen->b.chip_class == VI &&
1040                  sscreen->b.info.pfp_fw_version >= 121 &&
1041                  sscreen->b.info.me_fw_version >= 87) ||
1042                 (sscreen->b.chip_class == CIK &&
1043                  sscreen->b.info.pfp_fw_version >= 211 &&
1044                  sscreen->b.info.me_fw_version >= 173) ||
1045                 (sscreen->b.chip_class == SI &&
1046                  sscreen->b.info.pfp_fw_version >= 79 &&
1047                  sscreen->b.info.me_fw_version >= 142);
1048
1049         sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
1050         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1051                                             sscreen->b.family <= CHIP_POLARIS12) ||
1052                                            sscreen->b.family == CHIP_VEGA10 ||
1053                                            sscreen->b.family == CHIP_RAVEN;
1054         /* While it would be nice not to have this flag, we are constrained
1055          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1056          * on GFX9.
1057          */
1058         sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1059
1060         sscreen->b.has_cp_dma = true;
1061         sscreen->b.has_streamout = true;
1062
1063         /* Some chips have RB+ registers, but don't support RB+. Those must
1064          * always disable it.
1065          */
1066         if (sscreen->b.family == CHIP_STONEY ||
1067             sscreen->b.chip_class >= GFX9) {
1068                 sscreen->b.has_rbplus = true;
1069
1070                 sscreen->b.rbplus_allowed =
1071                         !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
1072                         (sscreen->b.family == CHIP_STONEY ||
1073                          sscreen->b.family == CHIP_RAVEN);
1074         }
1075
1076         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1077         sscreen->use_monolithic_shaders =
1078                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
1079
1080         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1081                                             SI_CONTEXT_INV_VMEM_L1;
1082         if (sscreen->b.chip_class <= VI)
1083                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1084
1085         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1086
1087         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1088                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1089
1090         for (i = 0; i < num_compiler_threads; i++)
1091                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1092         for (i = 0; i < num_compiler_threads_lowprio; i++)
1093                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1094
1095         /* Create the auxiliary context. This must be done last. */
1096         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1097
1098         if (sscreen->b.debug_flags & DBG_TEST_DMA)
1099                 r600_test_dma(&sscreen->b);
1100
1101         if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
1102                                       DBG_TEST_VMFAULT_SDMA |
1103                                       DBG_TEST_VMFAULT_SHADER))
1104                 si_test_vmfault(sscreen);
1105
1106         return &sscreen->b.b;
1107 }