2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
26 #include "si_shader_internal.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/hash_table.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_suballoc.h"
34 #include "util/u_tests.h"
35 #include "util/xmlconfig.h"
36 #include "vl/vl_decoder.h"
37 #include "../ddebug/dd_util.h"
39 #include "compiler/nir/nir.h"
44 static void si_destroy_context(struct pipe_context
*context
)
46 struct si_context
*sctx
= (struct si_context
*)context
;
49 /* Unreference the framebuffer normally to disable related logic
52 struct pipe_framebuffer_state fb
= {};
53 if (context
->set_framebuffer_state
)
54 context
->set_framebuffer_state(context
, &fb
);
56 si_release_all_descriptors(sctx
);
58 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
59 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
60 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
61 pipe_resource_reference(&sctx
->tess_offchip_ring
, NULL
);
62 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
63 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
64 free(sctx
->border_color_table
);
65 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
66 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
67 r600_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
69 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
70 if (sctx
->init_config_gs_rings
)
71 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
72 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
73 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
75 if (sctx
->fixed_func_tcs_shader
.cso
)
76 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
.cso
);
77 if (sctx
->custom_dsa_flush
)
78 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
79 if (sctx
->custom_blend_resolve
)
80 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
81 if (sctx
->custom_blend_fmask_decompress
)
82 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fmask_decompress
);
83 if (sctx
->custom_blend_eliminate_fastclear
)
84 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_eliminate_fastclear
);
85 if (sctx
->custom_blend_dcc_decompress
)
86 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_dcc_decompress
);
89 util_blitter_destroy(sctx
->blitter
);
91 r600_common_context_cleanup(&sctx
->b
);
93 LLVMDisposeTargetMachine(sctx
->tm
);
95 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
97 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
98 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
100 util_dynarray_fini(&sctx
->resident_tex_handles
);
101 util_dynarray_fini(&sctx
->resident_img_handles
);
102 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
103 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
104 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
108 static enum pipe_reset_status
109 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
111 struct si_context
*sctx
= (struct si_context
*)ctx
;
113 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
116 /* Apitrace profiling:
117 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
118 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
119 * and remember its number.
120 * 3) In Mesa, enable queries and performance counters around that draw
121 * call and print the results.
122 * 4) glretrace --benchmark --markers ..
124 static void si_emit_string_marker(struct pipe_context
*ctx
,
125 const char *string
, int len
)
127 struct si_context
*sctx
= (struct si_context
*)ctx
;
129 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
132 u_log_printf(sctx
->b
.log
, "\nString marker: %*s\n", len
, string
);
135 static LLVMTargetMachineRef
136 si_create_llvm_target_machine(struct si_screen
*sscreen
)
138 const char *triple
= "amdgcn--";
141 snprintf(features
, sizeof(features
),
142 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
143 sscreen
->b
.chip_class
>= GFX9
? ",+xnack" : ",-xnack",
144 sscreen
->llvm_has_working_vgpr_indexing
? "" : ",-promote-alloca",
145 sscreen
->b
.debug_flags
& DBG_SI_SCHED
? ",+si-scheduler" : "");
147 return LLVMCreateTargetMachine(ac_get_llvm_target(triple
), triple
,
148 r600_get_llvm_processor_name(sscreen
->b
.family
),
150 LLVMCodeGenLevelDefault
,
152 LLVMCodeModelDefault
);
155 static void si_set_log_context(struct pipe_context
*ctx
,
156 struct u_log_context
*log
)
158 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
165 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
168 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
169 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
170 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
176 if (flags
& PIPE_CONTEXT_DEBUG
)
177 sscreen
->record_llvm_ir
= true; /* racy but not critical */
179 sctx
->b
.b
.screen
= screen
; /* this must be set first */
180 sctx
->b
.b
.priv
= NULL
;
181 sctx
->b
.b
.destroy
= si_destroy_context
;
182 sctx
->b
.b
.emit_string_marker
= si_emit_string_marker
;
183 sctx
->b
.b
.set_log_context
= si_set_log_context
;
184 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
185 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
186 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
188 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
, flags
))
191 if (sscreen
->b
.info
.drm_major
== 3)
192 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
194 si_init_blit_functions(sctx
);
195 si_init_compute_functions(sctx
);
196 si_init_cp_dma_functions(sctx
);
197 si_init_debug_functions(sctx
);
199 if (sscreen
->b
.info
.has_hw_decode
) {
200 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
201 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
203 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
204 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
207 sctx
->b
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
,
208 si_context_gfx_flush
, sctx
);
209 sctx
->b
.gfx
.flush
= si_context_gfx_flush
;
212 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
213 sizeof(*sctx
->border_color_table
));
214 if (!sctx
->border_color_table
)
217 sctx
->border_color_buffer
= (struct r600_resource
*)
218 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
219 SI_MAX_BORDER_COLORS
*
220 sizeof(*sctx
->border_color_table
));
221 if (!sctx
->border_color_buffer
)
224 sctx
->border_color_map
=
225 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
226 NULL
, PIPE_TRANSFER_WRITE
);
227 if (!sctx
->border_color_map
)
230 si_init_all_descriptors(sctx
);
231 si_init_state_functions(sctx
);
232 si_init_shader_functions(sctx
);
233 si_init_ia_multi_vgt_param_table(sctx
);
235 if (sctx
->b
.chip_class
>= CIK
)
236 cik_init_sdma_functions(sctx
);
238 si_init_dma_functions(sctx
);
240 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
241 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
243 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
244 if (sctx
->blitter
== NULL
)
246 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
248 sctx
->sample_mask
.sample_mask
= 0xffff;
250 /* these must be last */
251 si_begin_new_cs(sctx
);
253 if (sctx
->b
.chip_class
>= GFX9
) {
254 sctx
->wait_mem_scratch
= (struct r600_resource
*)
255 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 4);
256 if (!sctx
->wait_mem_scratch
)
259 /* Initialize the memory. */
260 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
261 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
262 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
263 S_370_WR_CONFIRM(1) |
264 S_370_ENGINE_SEL(V_370_ME
));
265 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
);
266 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
>> 32);
267 radeon_emit(cs
, sctx
->wait_mem_number
);
270 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
271 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
272 if (sctx
->b
.chip_class
== CIK
) {
273 sctx
->null_const_buf
.buffer
=
274 r600_aligned_buffer_create(screen
,
275 R600_RESOURCE_FLAG_UNMAPPABLE
,
276 PIPE_USAGE_DEFAULT
, 16,
277 sctx
->screen
->b
.info
.tcc_cache_line_size
);
278 if (!sctx
->null_const_buf
.buffer
)
280 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
282 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
283 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
284 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
285 &sctx
->null_const_buf
);
289 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
290 &sctx
->null_const_buf
);
291 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
292 &sctx
->null_const_buf
);
293 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
294 &sctx
->null_const_buf
);
295 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
296 &sctx
->null_const_buf
);
297 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
298 &sctx
->null_const_buf
);
300 /* Clear the NULL constant buffer, because loads should return zeros. */
301 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
302 sctx
->null_const_buf
.buffer
->width0
, 0,
303 R600_COHERENCY_SHADER
);
306 uint64_t max_threads_per_block
;
307 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
308 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
309 &max_threads_per_block
);
311 /* The maximum number of scratch waves. Scratch space isn't divided
312 * evenly between CUs. The number is only a function of the number of CUs.
313 * We can decrease the constant to decrease the scratch buffer size.
315 * sctx->scratch_waves must be >= the maximum posible size of
316 * 1 threadgroup, so that the hw doesn't hang from being unable
319 * The recommended value is 4 per CU at most. Higher numbers don't
320 * bring much benefit, but they still occupy chip resources (think
321 * async compute). I've seen ~2% performance difference between 4 and 32.
323 sctx
->scratch_waves
= MAX2(32 * sscreen
->b
.info
.num_good_compute_units
,
324 max_threads_per_block
/ 64);
326 sctx
->tm
= si_create_llvm_target_machine(sscreen
);
328 /* Bindless handles. */
329 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
330 _mesa_key_pointer_equal
);
331 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
332 _mesa_key_pointer_equal
);
334 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
335 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
336 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
337 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
338 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
342 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
343 si_destroy_context(&sctx
->b
.b
);
347 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
348 void *priv
, unsigned flags
)
350 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
351 struct pipe_context
*ctx
;
353 if (sscreen
->b
.debug_flags
& DBG_CHECK_VM
)
354 flags
|= PIPE_CONTEXT_DEBUG
;
356 ctx
= si_create_context(screen
, flags
);
358 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
361 /* Clover (compute-only) is unsupported.
363 * Since the threaded context creates shader states from the non-driver
364 * thread, asynchronous compilation is required for create_{shader}_-
365 * state not to use pipe_context. Debug contexts (ddebug) disable
366 * asynchronous compilation, so don't use the threaded context with
369 if (flags
& (PIPE_CONTEXT_COMPUTE_ONLY
| PIPE_CONTEXT_DEBUG
))
372 /* When shaders are logged to stderr, asynchronous compilation is
374 if (sscreen
->b
.debug_flags
& DBG_ALL_SHADERS
)
377 return threaded_context_create(ctx
, &sscreen
->b
.pool_transfers
,
378 r600_replace_buffer_storage
,
379 &((struct si_context
*)ctx
)->b
.tc
);
385 static bool si_have_tgsi_compute(struct si_screen
*sscreen
)
387 /* Old kernels disallowed some register writes for SI
388 * that are used for indirect dispatches. */
389 return (sscreen
->b
.chip_class
>= CIK
||
390 sscreen
->b
.info
.drm_major
== 3 ||
391 (sscreen
->b
.info
.drm_major
== 2 &&
392 sscreen
->b
.info
.drm_minor
>= 45));
395 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
397 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
400 /* Supported features (boolean caps). */
401 case PIPE_CAP_ACCELERATED
:
402 case PIPE_CAP_TWO_SIDED_STENCIL
:
403 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
404 case PIPE_CAP_ANISOTROPIC_FILTER
:
405 case PIPE_CAP_POINT_SPRITE
:
406 case PIPE_CAP_OCCLUSION_QUERY
:
407 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
408 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
409 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
410 case PIPE_CAP_TEXTURE_SWIZZLE
:
411 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
412 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
413 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
414 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
415 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
416 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
417 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
419 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
420 case PIPE_CAP_PRIMITIVE_RESTART
:
421 case PIPE_CAP_CONDITIONAL_RENDER
:
422 case PIPE_CAP_TEXTURE_BARRIER
:
423 case PIPE_CAP_INDEP_BLEND_ENABLE
:
424 case PIPE_CAP_INDEP_BLEND_FUNC
:
425 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
426 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
427 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
428 case PIPE_CAP_START_INSTANCE
:
429 case PIPE_CAP_NPOT_TEXTURES
:
430 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
431 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
432 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
433 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
434 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
435 case PIPE_CAP_TGSI_INSTANCEID
:
436 case PIPE_CAP_COMPUTE
:
437 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
438 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
439 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
440 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
441 case PIPE_CAP_CUBE_MAP_ARRAY
:
442 case PIPE_CAP_SAMPLE_SHADING
:
443 case PIPE_CAP_DRAW_INDIRECT
:
444 case PIPE_CAP_CLIP_HALFZ
:
445 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
446 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
447 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
448 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
449 case PIPE_CAP_TGSI_TEXCOORD
:
450 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
451 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
452 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
453 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
454 case PIPE_CAP_SHAREABLE_SHADERS
:
455 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
456 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
457 case PIPE_CAP_TEXTURE_QUERY_LOD
:
458 case PIPE_CAP_TEXTURE_GATHER_SM5
:
459 case PIPE_CAP_TGSI_TXQS
:
460 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
461 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
462 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
463 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
464 case PIPE_CAP_INVALIDATE_BUFFER
:
465 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
466 case PIPE_CAP_QUERY_MEMORY_INFO
:
467 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
468 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
469 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
470 case PIPE_CAP_GENERATE_MIPMAP
:
471 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
472 case PIPE_CAP_STRING_MARKER
:
473 case PIPE_CAP_CLEAR_TEXTURE
:
474 case PIPE_CAP_CULL_DISTANCE
:
475 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
476 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
477 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
478 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
479 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
480 case PIPE_CAP_DOUBLES
:
481 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
482 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
483 case PIPE_CAP_BINDLESS_TEXTURE
:
484 case PIPE_CAP_QUERY_TIMESTAMP
:
485 case PIPE_CAP_QUERY_TIME_ELAPSED
:
486 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
487 case PIPE_CAP_QUERY_SO_OVERFLOW
:
488 case PIPE_CAP_MEMOBJ
:
489 case PIPE_CAP_LOAD_CONSTBUF
:
493 case PIPE_CAP_INT64_DIVMOD
:
494 case PIPE_CAP_TGSI_CLOCK
:
495 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
496 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
499 case PIPE_CAP_TGSI_VOTE
:
500 return HAVE_LLVM
>= 0x0400;
502 case PIPE_CAP_TGSI_BALLOT
:
503 return HAVE_LLVM
>= 0x0500;
505 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
506 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
508 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
509 return (sscreen
->b
.info
.drm_major
== 2 &&
510 sscreen
->b
.info
.drm_minor
>= 43) ||
511 sscreen
->b
.info
.drm_major
== 3;
513 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
514 /* 2D tiling on CIK is supported since DRM 2.35.0 */
515 return sscreen
->b
.chip_class
< CIK
||
516 (sscreen
->b
.info
.drm_major
== 2 &&
517 sscreen
->b
.info
.drm_minor
>= 35) ||
518 sscreen
->b
.info
.drm_major
== 3;
520 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
521 return R600_MAP_BUFFER_ALIGNMENT
;
523 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
524 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
525 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
526 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
527 case PIPE_CAP_MAX_VERTEX_STREAMS
:
528 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
531 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
532 if (sscreen
->b
.debug_flags
& DBG_NIR
)
533 return 140; /* no geometry and tessellation shaders yet */
534 if (si_have_tgsi_compute(sscreen
))
538 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
539 return MIN2(sscreen
->b
.info
.max_alloc_size
, INT_MAX
);
541 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
542 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
543 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
544 /* SI doesn't support unaligned loads.
545 * CIK needs DRM 2.50.0 on radeon. */
546 return sscreen
->b
.chip_class
== SI
||
547 (sscreen
->b
.info
.drm_major
== 2 &&
548 sscreen
->b
.info
.drm_minor
< 50);
550 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
551 /* TODO: GFX9 hangs. */
552 if (sscreen
->b
.chip_class
>= GFX9
)
554 /* Disable on SI due to VM faults in CP DMA. Enable once these
555 * faults are mitigated in software.
557 if (sscreen
->b
.chip_class
>= CIK
&&
558 sscreen
->b
.info
.drm_major
== 3 &&
559 sscreen
->b
.info
.drm_minor
>= 13)
560 return RADEON_SPARSE_PAGE_SIZE
;
563 /* Unsupported features. */
564 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
565 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
566 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
567 case PIPE_CAP_USER_VERTEX_BUFFERS
:
568 case PIPE_CAP_FAKE_SW_MSAA
:
569 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
570 case PIPE_CAP_VERTEXID_NOBASE
:
571 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
572 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
573 case PIPE_CAP_NATIVE_FENCE_FD
:
574 case PIPE_CAP_TGSI_FS_FBFETCH
:
575 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
577 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
578 case PIPE_CAP_POST_DEPTH_COVERAGE
:
581 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
582 return si_have_tgsi_compute(sscreen
);
584 case PIPE_CAP_DRAW_PARAMETERS
:
585 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
586 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
587 return sscreen
->has_draw_indirect_multi
;
589 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
592 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
593 return sscreen
->b
.chip_class
<= VI
?
594 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
597 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
598 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
601 /* Geometry shader output. */
602 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
604 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
607 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
611 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
612 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
613 return 15; /* 16384 */
614 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
615 /* textures support 8192, but layered rendering supports 2048 */
617 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
618 /* textures support 8192, but layered rendering supports 2048 */
621 /* Viewports and render targets. */
622 case PIPE_CAP_MAX_VIEWPORTS
:
623 return R600_MAX_VIEWPORTS
;
624 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
625 case PIPE_CAP_MAX_RENDER_TARGETS
:
628 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
629 case PIPE_CAP_MIN_TEXEL_OFFSET
:
632 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
633 case PIPE_CAP_MAX_TEXEL_OFFSET
:
636 case PIPE_CAP_ENDIANNESS
:
637 return PIPE_ENDIAN_LITTLE
;
639 case PIPE_CAP_VENDOR_ID
:
640 return ATI_VENDOR_ID
;
641 case PIPE_CAP_DEVICE_ID
:
642 return sscreen
->b
.info
.pci_id
;
643 case PIPE_CAP_VIDEO_MEMORY
:
644 return sscreen
->b
.info
.vram_size
>> 20;
645 case PIPE_CAP_PCI_GROUP
:
646 return sscreen
->b
.info
.pci_domain
;
647 case PIPE_CAP_PCI_BUS
:
648 return sscreen
->b
.info
.pci_bus
;
649 case PIPE_CAP_PCI_DEVICE
:
650 return sscreen
->b
.info
.pci_dev
;
651 case PIPE_CAP_PCI_FUNCTION
:
652 return sscreen
->b
.info
.pci_func
;
657 static int si_get_shader_param(struct pipe_screen
* pscreen
,
658 enum pipe_shader_type shader
,
659 enum pipe_shader_cap param
)
661 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
665 case PIPE_SHADER_FRAGMENT
:
666 case PIPE_SHADER_VERTEX
:
667 case PIPE_SHADER_GEOMETRY
:
668 case PIPE_SHADER_TESS_CTRL
:
669 case PIPE_SHADER_TESS_EVAL
:
671 case PIPE_SHADER_COMPUTE
:
673 case PIPE_SHADER_CAP_PREFERRED_IR
:
674 return PIPE_SHADER_IR_NATIVE
;
676 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
677 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
679 if (si_have_tgsi_compute(sscreen
))
680 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
685 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
686 uint64_t max_const_buffer_size
;
687 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
688 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
689 &max_const_buffer_size
);
690 return MIN2(max_const_buffer_size
, INT_MAX
);
693 /* If compute shaders don't require a special value
694 * for this cap, we can return the same value we
695 * do for other shader types. */
705 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
706 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
707 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
708 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
709 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
711 case PIPE_SHADER_CAP_MAX_INPUTS
:
712 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
713 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
714 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
715 case PIPE_SHADER_CAP_MAX_TEMPS
:
716 return 256; /* Max native temporaries. */
717 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
718 return 4096 * sizeof(float[4]); /* actually only memory limits this */
719 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
720 return SI_NUM_CONST_BUFFERS
;
721 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
722 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
723 return SI_NUM_SAMPLERS
;
724 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
725 return SI_NUM_SHADER_BUFFERS
;
726 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
727 return SI_NUM_IMAGES
;
728 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
730 case PIPE_SHADER_CAP_PREFERRED_IR
:
731 if (sscreen
->b
.debug_flags
& DBG_NIR
&&
732 (shader
== PIPE_SHADER_VERTEX
||
733 shader
== PIPE_SHADER_FRAGMENT
))
734 return PIPE_SHADER_IR_NIR
;
735 return PIPE_SHADER_IR_TGSI
;
736 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
739 /* Supported boolean features. */
740 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
741 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
742 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
743 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
744 case PIPE_SHADER_CAP_INTEGERS
:
745 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
746 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
747 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
748 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
751 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
752 /* TODO: Indirect indexing of GS inputs is unimplemented. */
753 return shader
!= PIPE_SHADER_GEOMETRY
&&
754 (sscreen
->llvm_has_working_vgpr_indexing
||
755 /* TCS and TES load inputs directly from LDS or
756 * offchip memory, so indirect indexing is trivial. */
757 shader
== PIPE_SHADER_TESS_CTRL
||
758 shader
== PIPE_SHADER_TESS_EVAL
);
760 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
761 return sscreen
->llvm_has_working_vgpr_indexing
||
762 /* TCS stores outputs directly to memory. */
763 shader
== PIPE_SHADER_TESS_CTRL
;
765 /* Unsupported boolean features. */
766 case PIPE_SHADER_CAP_SUBROUTINES
:
767 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
768 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
774 static const struct nir_shader_compiler_options nir_options
= {
775 .vertex_id_zero_based
= true,
777 .lower_flrp32
= true,
781 .lower_pack_snorm_2x16
= true,
782 .lower_pack_snorm_4x8
= true,
783 .lower_pack_unorm_2x16
= true,
784 .lower_pack_unorm_4x8
= true,
785 .lower_unpack_snorm_2x16
= true,
786 .lower_unpack_snorm_4x8
= true,
787 .lower_unpack_unorm_2x16
= true,
788 .lower_unpack_unorm_4x8
= true,
789 .lower_extract_byte
= true,
790 .lower_extract_word
= true,
791 .max_unroll_iterations
= 32,
792 .native_integers
= true,
796 si_get_compiler_options(struct pipe_screen
*screen
,
797 enum pipe_shader_ir ir
,
798 enum pipe_shader_type shader
)
800 assert(ir
== PIPE_SHADER_IR_NIR
);
804 static void si_destroy_screen(struct pipe_screen
* pscreen
)
806 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
807 struct si_shader_part
*parts
[] = {
809 sscreen
->tcs_epilogs
,
816 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
819 util_queue_destroy(&sscreen
->shader_compiler_queue
);
820 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
822 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm
); i
++)
824 LLVMDisposeTargetMachine(sscreen
->tm
[i
]);
826 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm_low_priority
); i
++)
827 if (sscreen
->tm_low_priority
[i
])
828 LLVMDisposeTargetMachine(sscreen
->tm_low_priority
[i
]);
830 /* Free shader parts. */
831 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
833 struct si_shader_part
*part
= parts
[i
];
835 parts
[i
] = part
->next
;
836 radeon_shader_binary_clean(&part
->binary
);
840 mtx_destroy(&sscreen
->shader_parts_mutex
);
841 si_destroy_shader_cache(sscreen
);
842 r600_destroy_common_screen(&sscreen
->b
);
845 static bool si_init_gs_info(struct si_screen
*sscreen
)
847 switch (sscreen
->b
.family
) {
856 sscreen
->gs_table_depth
= 16;
870 sscreen
->gs_table_depth
= 32;
877 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
879 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
885 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
886 if (!strcmp(family
, r600_get_llvm_processor_name(i
))) {
887 /* Override family and chip_class. */
888 sscreen
->b
.family
= sscreen
->b
.info
.family
= i
;
890 if (i
>= CHIP_VEGA10
)
891 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= GFX9
;
892 else if (i
>= CHIP_TONGA
)
893 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= VI
;
894 else if (i
>= CHIP_BONAIRE
)
895 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= CIK
;
897 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= SI
;
899 /* Don't submit any IBs. */
900 setenv("RADEON_NOOP", "1", 1);
905 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
909 static void si_test_vmfault(struct si_screen
*sscreen
)
911 struct pipe_context
*ctx
= sscreen
->b
.aux_context
;
912 struct si_context
*sctx
= (struct si_context
*)ctx
;
913 struct pipe_resource
*buf
=
914 pipe_buffer_create(&sscreen
->b
.b
, 0, PIPE_USAGE_DEFAULT
, 64);
917 puts("Buffer allocation failed.");
921 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
923 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_CP
) {
924 si_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0);
925 ctx
->flush(ctx
, NULL
, 0);
926 puts("VM fault test: CP - done.");
928 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_SDMA
) {
929 sctx
->b
.dma_clear_buffer(ctx
, buf
, 0, 4, 0);
930 ctx
->flush(ctx
, NULL
, 0);
931 puts("VM fault test: SDMA - done.");
933 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_SHADER
) {
934 util_test_constant_buffer(ctx
, buf
);
935 puts("VM fault test: Shader - done.");
940 static void radeonsi_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
942 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
945 static void radeonsi_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
947 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
949 ac_compute_device_uuid(&rscreen
->info
, uuid
, PIPE_UUID_SIZE
);
952 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
,
953 const struct pipe_screen_config
*config
)
955 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
956 unsigned num_threads
, num_compiler_threads
, num_compiler_threads_lowprio
, i
;
962 /* Set functions first. */
963 sscreen
->b
.b
.context_create
= si_pipe_create_context
;
964 sscreen
->b
.b
.destroy
= si_destroy_screen
;
965 sscreen
->b
.b
.get_param
= si_get_param
;
966 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
967 sscreen
->b
.b
.get_compiler_options
= si_get_compiler_options
;
968 sscreen
->b
.b
.get_device_uuid
= radeonsi_get_device_uuid
;
969 sscreen
->b
.b
.get_driver_uuid
= radeonsi_get_driver_uuid
;
970 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
972 si_init_screen_state_functions(sscreen
);
974 /* Set these flags in debug_flags early, so that the shader cache takes
977 if (driQueryOptionb(config
->options
,
978 "glsl_correct_derivatives_after_discard"))
979 sscreen
->b
.debug_flags
|= DBG_FS_CORRECT_DERIVS_AFTER_KILL
;
980 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
981 sscreen
->b
.debug_flags
|= DBG_SI_SCHED
;
983 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
984 !si_init_gs_info(sscreen
) ||
985 !si_init_shader_cache(sscreen
)) {
990 /* Only enable as many threads as we have target machines, but at most
991 * the number of CPUs - 1 if there is more than one.
993 num_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
994 num_threads
= MAX2(1, num_threads
- 1);
995 num_compiler_threads
= MIN2(num_threads
, ARRAY_SIZE(sscreen
->tm
));
996 num_compiler_threads_lowprio
=
997 MIN2(num_threads
, ARRAY_SIZE(sscreen
->tm_low_priority
));
999 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "si_shader",
1000 32, num_compiler_threads
,
1001 UTIL_QUEUE_INIT_RESIZE_IF_FULL
)) {
1002 si_destroy_shader_cache(sscreen
);
1007 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
1009 32, num_compiler_threads_lowprio
,
1010 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1011 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
1012 si_destroy_shader_cache(sscreen
);
1017 si_handle_env_var_force_family(sscreen
);
1019 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1020 si_init_perfcounters(sscreen
);
1022 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1023 * around by setting 4K granularity.
1025 sscreen
->tess_offchip_block_dw_size
=
1026 sscreen
->b
.family
== CHIP_HAWAII
? 4096 : 8192;
1028 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1030 sscreen
->has_clear_state
= sscreen
->b
.chip_class
>= CIK
;
1032 sscreen
->has_distributed_tess
=
1033 sscreen
->b
.chip_class
>= VI
&&
1034 sscreen
->b
.info
.max_se
>= 2;
1036 sscreen
->has_draw_indirect_multi
=
1037 (sscreen
->b
.family
>= CHIP_POLARIS10
) ||
1038 (sscreen
->b
.chip_class
== VI
&&
1039 sscreen
->b
.info
.pfp_fw_version
>= 121 &&
1040 sscreen
->b
.info
.me_fw_version
>= 87) ||
1041 (sscreen
->b
.chip_class
== CIK
&&
1042 sscreen
->b
.info
.pfp_fw_version
>= 211 &&
1043 sscreen
->b
.info
.me_fw_version
>= 173) ||
1044 (sscreen
->b
.chip_class
== SI
&&
1045 sscreen
->b
.info
.pfp_fw_version
>= 79 &&
1046 sscreen
->b
.info
.me_fw_version
>= 142);
1048 sscreen
->has_ds_bpermute
= sscreen
->b
.chip_class
>= VI
;
1049 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->b
.family
>= CHIP_POLARIS10
&&
1050 sscreen
->b
.family
<= CHIP_POLARIS12
) ||
1051 sscreen
->b
.family
== CHIP_VEGA10
||
1052 sscreen
->b
.family
== CHIP_RAVEN
;
1053 sscreen
->dpbb_allowed
= sscreen
->b
.chip_class
>= GFX9
&&
1054 !(sscreen
->b
.debug_flags
& DBG_NO_DPBB
);
1055 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
&&
1056 !(sscreen
->b
.debug_flags
& DBG_NO_DFSM
);
1058 /* While it would be nice not to have this flag, we are constrained
1059 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1062 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->b
.chip_class
<= VI
;
1064 sscreen
->b
.has_cp_dma
= true;
1065 sscreen
->b
.has_streamout
= true;
1067 /* Some chips have RB+ registers, but don't support RB+. Those must
1068 * always disable it.
1070 if (sscreen
->b
.family
== CHIP_STONEY
||
1071 sscreen
->b
.chip_class
>= GFX9
) {
1072 sscreen
->b
.has_rbplus
= true;
1074 sscreen
->b
.rbplus_allowed
=
1075 !(sscreen
->b
.debug_flags
& DBG_NO_RB_PLUS
) &&
1076 (sscreen
->b
.family
== CHIP_STONEY
||
1077 sscreen
->b
.family
== CHIP_RAVEN
);
1080 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1081 sscreen
->use_monolithic_shaders
=
1082 (sscreen
->b
.debug_flags
& DBG_MONOLITHIC_SHADERS
) != 0;
1084 sscreen
->b
.barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
1085 SI_CONTEXT_INV_VMEM_L1
;
1086 if (sscreen
->b
.chip_class
<= VI
) {
1087 sscreen
->b
.barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_GLOBAL_L2
;
1088 sscreen
->b
.barrier_flags
.L2_to_cp
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1091 sscreen
->b
.barrier_flags
.compute_to_L2
= SI_CONTEXT_CS_PARTIAL_FLUSH
;
1093 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1094 sscreen
->b
.debug_flags
|= DBG_ALL_SHADERS
;
1096 for (i
= 0; i
< num_compiler_threads
; i
++)
1097 sscreen
->tm
[i
] = si_create_llvm_target_machine(sscreen
);
1098 for (i
= 0; i
< num_compiler_threads_lowprio
; i
++)
1099 sscreen
->tm_low_priority
[i
] = si_create_llvm_target_machine(sscreen
);
1101 /* Create the auxiliary context. This must be done last. */
1102 sscreen
->b
.aux_context
= si_create_context(&sscreen
->b
.b
, 0);
1104 if (sscreen
->b
.debug_flags
& DBG_TEST_DMA
)
1105 r600_test_dma(&sscreen
->b
);
1107 if (sscreen
->b
.debug_flags
& (DBG_TEST_VMFAULT_CP
|
1108 DBG_TEST_VMFAULT_SDMA
|
1109 DBG_TEST_VMFAULT_SHADER
))
1110 si_test_vmfault(sscreen
);
1112 return &sscreen
->b
.b
;