2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_format.h"
34 #include "util/u_transfer.h"
35 #include "util/u_surface.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_simple_shaders.h"
40 #include "util/u_upload_mgr.h"
41 #include "vl/vl_decoder.h"
42 #include "vl/vl_video_buffer.h"
43 #include "os/os_time.h"
44 #include "pipebuffer/pb_buffer.h"
46 #include "radeon/radeon_uvd.h"
49 #include "si_resource.h"
52 #include "../radeon/r600_cs.h"
57 void si_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
60 struct si_context
*sctx
= (struct si_context
*)ctx
;
61 struct pipe_query
*render_cond
= NULL
;
62 boolean render_cond_cond
= FALSE
;
63 unsigned render_cond_mode
= 0;
66 *fence
= sctx
->b
.ws
->cs_create_fence(sctx
->b
.rings
.gfx
.cs
);
69 /* Disable render condition. */
70 if (sctx
->b
.current_render_cond
) {
71 render_cond
= sctx
->b
.current_render_cond
;
72 render_cond_cond
= sctx
->b
.current_render_cond_cond
;
73 render_cond_mode
= sctx
->b
.current_render_cond_mode
;
74 ctx
->render_condition(ctx
, NULL
, FALSE
, 0);
77 si_context_flush(sctx
, flags
);
79 /* Re-enable render condition. */
81 ctx
->render_condition(ctx
, render_cond
, render_cond_cond
, render_cond_mode
);
85 static void si_flush_from_st(struct pipe_context
*ctx
,
86 struct pipe_fence_handle
**fence
,
90 flags
& PIPE_FLUSH_END_OF_FRAME
? RADEON_FLUSH_END_OF_FRAME
: 0);
93 static void si_flush_from_winsys(void *ctx
, unsigned flags
)
95 si_flush((struct pipe_context
*)ctx
, NULL
, flags
);
98 static void si_destroy_context(struct pipe_context
*context
)
100 struct si_context
*sctx
= (struct si_context
*)context
;
102 si_release_all_descriptors(sctx
);
104 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
105 r600_resource_reference(&sctx
->border_color_table
, NULL
);
107 if (sctx
->dummy_pixel_shader
) {
108 sctx
->b
.b
.delete_fs_state(&sctx
->b
.b
, sctx
->dummy_pixel_shader
);
110 for (int i
= 0; i
< 8; i
++) {
111 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush_depth_stencil
[i
]);
112 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush_depth
[i
]);
113 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush_stencil
[i
]);
115 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush_inplace
);
116 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
117 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
118 util_unreference_framebuffer_state(&sctx
->framebuffer
);
120 util_blitter_destroy(sctx
->blitter
);
122 r600_common_context_cleanup(&sctx
->b
);
126 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
, void *priv
)
128 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
129 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
135 sctx
->b
.b
.screen
= screen
; /* this must be set first */
136 sctx
->b
.b
.priv
= priv
;
137 sctx
->b
.b
.destroy
= si_destroy_context
;
138 sctx
->b
.b
.flush
= si_flush_from_st
;
139 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
141 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
))
144 si_init_blit_functions(sctx
);
145 si_init_compute_functions(sctx
);
147 if (sscreen
->b
.info
.has_uvd
) {
148 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
149 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
151 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
152 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
155 sctx
->b
.rings
.gfx
.cs
= sctx
->b
.ws
->cs_create(sctx
->b
.ws
, RING_GFX
, NULL
);
156 sctx
->b
.rings
.gfx
.flush
= si_flush_from_winsys
;
158 si_init_all_descriptors(sctx
);
160 /* Initialize cache_flush. */
161 sctx
->cache_flush
= si_atom_cache_flush
;
162 sctx
->atoms
.cache_flush
= &sctx
->cache_flush
;
164 sctx
->atoms
.streamout_begin
= &sctx
->b
.streamout
.begin_atom
;
166 switch (sctx
->b
.chip_class
) {
169 si_init_state_functions(sctx
);
170 si_init_config(sctx
);
173 R600_ERR("Unsupported chip class %d.\n", sctx
->b
.chip_class
);
177 sctx
->b
.ws
->cs_set_flush_callback(sctx
->b
.rings
.gfx
.cs
, si_flush_from_winsys
, sctx
);
179 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
180 if (sctx
->blitter
== NULL
)
183 sctx
->dummy_pixel_shader
=
184 util_make_fragment_cloneinput_shader(&sctx
->b
.b
, 0,
185 TGSI_SEMANTIC_GENERIC
,
186 TGSI_INTERPOLATE_CONSTANT
);
187 sctx
->b
.b
.bind_fs_state(&sctx
->b
.b
, sctx
->dummy_pixel_shader
);
189 /* these must be last */
190 si_begin_new_cs(sctx
);
191 r600_query_init_backend_mask(&sctx
->b
); /* this emits commands and must be last */
193 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
194 * with a NULL buffer). We need to use a dummy buffer instead. */
195 if (sctx
->b
.chip_class
== CIK
) {
196 sctx
->null_const_buf
.buffer
= pipe_buffer_create(screen
, PIPE_BIND_CONSTANT_BUFFER
,
197 PIPE_USAGE_STATIC
, 16);
198 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
200 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
201 for (i
= 0; i
< NUM_CONST_BUFFERS
; i
++) {
202 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
203 &sctx
->null_const_buf
);
207 /* Clear the NULL constant buffer, because loads should return zeros. */
208 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
209 sctx
->null_const_buf
.buffer
->width0
, 0);
214 si_destroy_context(&sctx
->b
.b
);
222 const char *si_get_llvm_processor_name(enum radeon_family family
)
225 case CHIP_TAHITI
: return "tahiti";
226 case CHIP_PITCAIRN
: return "pitcairn";
227 case CHIP_VERDE
: return "verde";
228 case CHIP_OLAND
: return "oland";
229 #if HAVE_LLVM <= 0x0303
230 default: return "SI";
232 case CHIP_HAINAN
: return "hainan";
233 case CHIP_BONAIRE
: return "bonaire";
234 case CHIP_KABINI
: return "kabini";
235 case CHIP_KAVERI
: return "kaveri";
236 case CHIP_HAWAII
: return "hawaii";
242 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
244 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
247 /* Supported features (boolean caps). */
248 case PIPE_CAP_TWO_SIDED_STENCIL
:
249 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
250 case PIPE_CAP_ANISOTROPIC_FILTER
:
251 case PIPE_CAP_POINT_SPRITE
:
252 case PIPE_CAP_OCCLUSION_QUERY
:
253 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
254 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
255 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
256 case PIPE_CAP_TEXTURE_SWIZZLE
:
257 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
258 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
259 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
260 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
261 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
262 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
264 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
265 case PIPE_CAP_PRIMITIVE_RESTART
:
266 case PIPE_CAP_CONDITIONAL_RENDER
:
267 case PIPE_CAP_TEXTURE_BARRIER
:
268 case PIPE_CAP_INDEP_BLEND_ENABLE
:
269 case PIPE_CAP_INDEP_BLEND_FUNC
:
270 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
271 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
272 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
273 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
274 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
275 case PIPE_CAP_USER_INDEX_BUFFERS
:
276 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
277 case PIPE_CAP_START_INSTANCE
:
278 case PIPE_CAP_NPOT_TEXTURES
:
279 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
280 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
281 case PIPE_CAP_TGSI_INSTANCEID
:
282 case PIPE_CAP_COMPUTE
:
283 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
284 case PIPE_CAP_TGSI_VS_LAYER
:
285 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
288 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
289 /* 2D tiling on CIK is supported since DRM 2.35.0 */
290 return HAVE_LLVM
>= 0x0304 && (sscreen
->b
.chip_class
< CIK
||
291 sscreen
->b
.info
.drm_minor
>= 35);
293 case PIPE_CAP_TGSI_TEXCOORD
:
296 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
299 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
302 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
305 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
307 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
308 return MIN2(sscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
310 /* Unsupported features. */
311 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
312 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
313 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
314 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
315 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
316 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
317 case PIPE_CAP_USER_VERTEX_BUFFERS
:
318 case PIPE_CAP_CUBE_MAP_ARRAY
:
321 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
322 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
325 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
326 return sscreen
->b
.has_streamout
? 4 : 0;
327 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
328 return sscreen
->b
.has_streamout
? 1 : 0;
329 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
330 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
331 return sscreen
->b
.has_streamout
? 32*4 : 0;
334 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
335 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
336 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
338 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
340 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
343 /* Render targets. */
344 case PIPE_CAP_MAX_RENDER_TARGETS
:
347 case PIPE_CAP_MAX_VIEWPORTS
:
350 /* Timer queries, present when the clock frequency is non zero. */
351 case PIPE_CAP_QUERY_TIMESTAMP
:
352 case PIPE_CAP_QUERY_TIME_ELAPSED
:
353 return sscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
355 case PIPE_CAP_MIN_TEXEL_OFFSET
:
358 case PIPE_CAP_MAX_TEXEL_OFFSET
:
360 case PIPE_CAP_ENDIANNESS
:
361 return PIPE_ENDIAN_LITTLE
;
366 static float si_get_paramf(struct pipe_screen
* pscreen
,
367 enum pipe_capf param
)
370 case PIPE_CAPF_MAX_LINE_WIDTH
:
371 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
372 case PIPE_CAPF_MAX_POINT_WIDTH
:
373 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
375 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
377 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
379 case PIPE_CAPF_GUARD_BAND_LEFT
:
380 case PIPE_CAPF_GUARD_BAND_TOP
:
381 case PIPE_CAPF_GUARD_BAND_RIGHT
:
382 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
388 static int si_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
392 case PIPE_SHADER_FRAGMENT
:
393 case PIPE_SHADER_VERTEX
:
395 case PIPE_SHADER_GEOMETRY
:
396 /* TODO: support and enable geometry programs */
398 case PIPE_SHADER_COMPUTE
:
400 case PIPE_SHADER_CAP_PREFERRED_IR
:
401 return PIPE_SHADER_IR_LLVM
;
406 /* TODO: support tessellation */
411 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
412 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
413 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
414 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
416 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
418 case PIPE_SHADER_CAP_MAX_INPUTS
:
420 case PIPE_SHADER_CAP_MAX_TEMPS
:
421 return 256; /* Max native temporaries. */
422 case PIPE_SHADER_CAP_MAX_ADDRS
:
423 /* FIXME Isn't this equal to TEMPS? */
424 return 1; /* Max native address registers */
425 case PIPE_SHADER_CAP_MAX_CONSTS
:
426 return 4096; /* actually only memory limits this */
427 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
428 return NUM_PIPE_CONST_BUFFERS
;
429 case PIPE_SHADER_CAP_MAX_PREDS
:
430 return 0; /* FIXME */
431 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
433 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
435 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
436 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
437 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
438 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
440 case PIPE_SHADER_CAP_INTEGERS
:
442 case PIPE_SHADER_CAP_SUBROUTINES
:
444 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
445 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
447 case PIPE_SHADER_CAP_PREFERRED_IR
:
448 return PIPE_SHADER_IR_TGSI
;
453 static int si_get_video_param(struct pipe_screen
*screen
,
454 enum pipe_video_profile profile
,
455 enum pipe_video_entrypoint entrypoint
,
456 enum pipe_video_cap param
)
459 case PIPE_VIDEO_CAP_SUPPORTED
:
460 return vl_profile_supported(screen
, profile
, entrypoint
);
461 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
463 case PIPE_VIDEO_CAP_MAX_WIDTH
:
464 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
465 return vl_video_buffer_max_size(screen
);
466 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
467 return PIPE_FORMAT_NV12
;
468 case PIPE_VIDEO_CAP_MAX_LEVEL
:
469 return vl_level_supported(screen
, profile
);
475 static int si_get_compute_param(struct pipe_screen
*screen
,
476 enum pipe_compute_cap param
,
479 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
480 //TODO: select these params by asic
482 case PIPE_COMPUTE_CAP_IR_TARGET
: {
483 const char *gpu
= si_get_llvm_processor_name(sscreen
->b
.family
);
485 sprintf(ret
, "%s-r600--", gpu
);
487 return (8 + strlen(gpu
)) * sizeof(char);
489 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
491 uint64_t * grid_dimension
= ret
;
492 grid_dimension
[0] = 3;
494 return 1 * sizeof(uint64_t);
495 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
497 uint64_t * grid_size
= ret
;
498 grid_size
[0] = 65535;
499 grid_size
[1] = 65535;
502 return 3 * sizeof(uint64_t) ;
504 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
506 uint64_t * block_size
= ret
;
511 return 3 * sizeof(uint64_t);
512 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
514 uint64_t * max_threads_per_block
= ret
;
515 *max_threads_per_block
= 256;
517 return sizeof(uint64_t);
519 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
521 uint64_t *max_global_size
= ret
;
522 /* XXX: Not sure what to put here. */
523 *max_global_size
= 2000000000;
525 return sizeof(uint64_t);
526 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
528 uint64_t *max_local_size
= ret
;
529 /* Value reported by the closed source driver. */
530 *max_local_size
= 32768;
532 return sizeof(uint64_t);
533 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
535 uint64_t *max_input_size
= ret
;
536 /* Value reported by the closed source driver. */
537 *max_input_size
= 1024;
539 return sizeof(uint64_t);
540 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
542 uint64_t max_global_size
;
543 uint64_t *max_mem_alloc_size
= ret
;
544 si_get_compute_param(screen
, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
, &max_global_size
);
545 *max_mem_alloc_size
= max_global_size
/ 4;
547 return sizeof(uint64_t);
549 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
554 static void si_destroy_screen(struct pipe_screen
* pscreen
)
556 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
561 if (!radeon_winsys_unref(sscreen
->b
.ws
))
564 r600_common_screen_cleanup(&sscreen
->b
);
567 if (sscreen
->trace_bo
) {
568 sscreen
->ws
->buffer_unmap(sscreen
->trace_bo
->cs_buf
);
569 pipe_resource_reference((struct pipe_resource
**)&sscreen
->trace_bo
, NULL
);
573 sscreen
->b
.ws
->destroy(sscreen
->b
.ws
);
577 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
579 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
580 if (sscreen
== NULL
) {
584 ws
->query_info(ws
, &sscreen
->b
.info
);
586 /* Set functions first. */
587 sscreen
->b
.b
.context_create
= si_create_context
;
588 sscreen
->b
.b
.destroy
= si_destroy_screen
;
589 sscreen
->b
.b
.get_param
= si_get_param
;
590 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
591 sscreen
->b
.b
.get_paramf
= si_get_paramf
;
592 sscreen
->b
.b
.get_compute_param
= si_get_compute_param
;
593 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
594 if (sscreen
->b
.info
.has_uvd
) {
595 sscreen
->b
.b
.get_video_param
= ruvd_get_video_param
;
596 sscreen
->b
.b
.is_video_format_supported
= ruvd_is_format_supported
;
598 sscreen
->b
.b
.get_video_param
= si_get_video_param
;
599 sscreen
->b
.b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
602 if (!r600_common_screen_init(&sscreen
->b
, ws
)) {
607 sscreen
->b
.has_cp_dma
= true;
608 sscreen
->b
.has_streamout
= HAVE_LLVM
>= 0x0304;
610 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE
))
611 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
614 sscreen
->cs_count
= 0;
615 if (sscreen
->info
.drm_minor
>= 28) {
616 sscreen
->trace_bo
= (struct r600_resource
*)pipe_buffer_create(&sscreen
->screen
,
620 if (sscreen
->trace_bo
) {
621 sscreen
->trace_ptr
= sscreen
->ws
->buffer_map(sscreen
->trace_bo
->cs_buf
, NULL
,
622 PIPE_TRANSFER_UNSYNCHRONIZED
);
627 /* Create the auxiliary context. This must be done last. */
628 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
);
630 return &sscreen
->b
.b
;