src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_table, NULL);
  48         r600_resource_reference(&sctx->scratch_buffer, NULL);
  49         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  50
  51         si_pm4_free_state(sctx, sctx->init_config, ~0);
  52         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  53         si_pm4_delete_state(sctx, tf_ring, sctx->tf_state);
  54         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  55                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  56
  57         if (sctx->pstipple_sampler_state)
  58                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  59         if (sctx->dummy_pixel_shader)
  60                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  61         if (sctx->fixed_func_tcs_shader)
  62                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader);
  63         if (sctx->custom_dsa_flush)
  64                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  65         if (sctx->custom_blend_resolve)
  66                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  67         if (sctx->custom_blend_decompress)
  68                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  69         if (sctx->custom_blend_fastclear)
  70                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  71         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  72
  73         if (sctx->blitter)
  74                 util_blitter_destroy(sctx->blitter);
  75
  76         si_pm4_cleanup(sctx);
  77
  78         r600_common_context_cleanup(&sctx->b);
  79
  80 #if HAVE_LLVM >= 0x0306
  81         LLVMDisposeTargetMachine(sctx->tm);
  82 #endif
  83
  84         free(sctx->last_ib);
  85         FREE(sctx);
  86 }
  87
  88 static enum pipe_reset_status
  89 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  90 {
  91         struct si_context *sctx = (struct si_context *)ctx;
  92
  93         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  94 }
  95
  96 static struct pipe_context *si_create_context(struct pipe_screen *screen,
  97                                               void *priv, unsigned flags)
  98 {
  99         struct si_context *sctx = CALLOC_STRUCT(si_context);
 100         struct si_screen* sscreen = (struct si_screen *)screen;
 101         struct radeon_winsys *ws = sscreen->b.ws;
 102         LLVMTargetRef r600_target;
 103 #if HAVE_LLVM >= 0x0306
 104         const char *triple = "amdgcn--";
 105 #endif
 106         int shader, i;
 107
 108         if (sctx == NULL)
 109                 return NULL;
 110
 111         sctx->b.b.screen = screen; /* this must be set first */
 112         sctx->b.b.priv = priv;
 113         sctx->b.b.destroy = si_destroy_context;
 114         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 115         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 116         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 117
 118         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 119                 goto fail;
 120
 121         if (sscreen->b.info.drm_major == 3)
 122                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 123
 124         si_init_blit_functions(sctx);
 125         si_init_compute_functions(sctx);
 126         si_init_cp_dma_functions(sctx);
 127         si_init_debug_functions(sctx);
 128
 129         if (sscreen->b.info.has_uvd) {
 130                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 131                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 132         } else {
 133                 sctx->b.b.create_video_codec = vl_create_decoder;
 134                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 135         }
 136
 137         sctx->b.rings.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 138                                              sctx, sscreen->b.trace_bo ?
 139                                                 sscreen->b.trace_bo->cs_buf : NULL);
 140         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 141
 142         si_init_all_descriptors(sctx);
 143
 144         /* Initialize cache_flush. */
 145         sctx->cache_flush = si_atom_cache_flush;
 146         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 147
 148         sctx->msaa_sample_locs = si_atom_msaa_sample_locs;
 149         sctx->atoms.s.msaa_sample_locs = &sctx->msaa_sample_locs;
 150
 151         sctx->msaa_config = si_atom_msaa_config;
 152         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 153
 154         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 155         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 156
 157         si_init_state_functions(sctx);
 158         si_init_shader_functions(sctx);
 159
 160         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 161                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 162
 163         sctx->blitter = util_blitter_create(&sctx->b.b);
 164         if (sctx->blitter == NULL)
 165                 goto fail;
 166         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 167
 168         /* these must be last */
 169         si_begin_new_cs(sctx);
 170         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 171
 172         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 173          * with a NULL buffer). We need to use a dummy buffer instead. */
 174         if (sctx->b.chip_class == CIK) {
 175                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 176                                                                  PIPE_USAGE_DEFAULT, 16);
 177                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 178
 179                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 180                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 181                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 182                                                               &sctx->null_const_buf);
 183                         }
 184                 }
 185
 186                 /* Clear the NULL constant buffer, because loads should return zeros. */
 187                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 188                                      sctx->null_const_buf.buffer->width0, 0, false);
 189         }
 190
 191         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 192          * this for non-cs shaders.  Using the wrong value here can result in
 193          * GPU lockups, but the maximum value seems to always work.
 194          */
 195         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 196
 197 #if HAVE_LLVM >= 0x0306
 198         /* Initialize LLVM TargetMachine */
 199         r600_target = radeon_llvm_get_r600_target(triple);
 200         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 201                                            r600_get_llvm_processor_name(sscreen->b.family),
 202                                            sctx->b.chip_class >= VI ?
 203                                                    "+DumpCode" :
 204                                                    "+DumpCode,+vgpr-spilling",
 205                                            LLVMCodeGenLevelDefault,
 206                                            LLVMRelocDefault,
 207                                            LLVMCodeModelDefault);
 208 #endif
 209
 210         return &sctx->b.b;
 211 fail:
 212         si_destroy_context(&sctx->b.b);
 213         return NULL;
 214 }
 215
 216 /*
 217  * pipe_screen
 218  */
 219
 220 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 221 {
 222         struct si_screen *sscreen = (struct si_screen *)pscreen;
 223
 224         switch (param) {
 225         /* Supported features (boolean caps). */
 226         case PIPE_CAP_TWO_SIDED_STENCIL:
 227         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 228         case PIPE_CAP_ANISOTROPIC_FILTER:
 229         case PIPE_CAP_POINT_SPRITE:
 230         case PIPE_CAP_OCCLUSION_QUERY:
 231         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 232         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 233         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 234         case PIPE_CAP_TEXTURE_SWIZZLE:
 235         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 236         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 237         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 238         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 239         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 240         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 241         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 242         case PIPE_CAP_SM3:
 243         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 244         case PIPE_CAP_PRIMITIVE_RESTART:
 245         case PIPE_CAP_CONDITIONAL_RENDER:
 246         case PIPE_CAP_TEXTURE_BARRIER:
 247         case PIPE_CAP_INDEP_BLEND_ENABLE:
 248         case PIPE_CAP_INDEP_BLEND_FUNC:
 249         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 250         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 251         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 252         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 253         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 254         case PIPE_CAP_USER_INDEX_BUFFERS:
 255         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 256         case PIPE_CAP_START_INSTANCE:
 257         case PIPE_CAP_NPOT_TEXTURES:
 258         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 259         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 260         case PIPE_CAP_TGSI_INSTANCEID:
 261         case PIPE_CAP_COMPUTE:
 262         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 263         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 264         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 265         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 266         case PIPE_CAP_CUBE_MAP_ARRAY:
 267         case PIPE_CAP_SAMPLE_SHADING:
 268         case PIPE_CAP_DRAW_INDIRECT:
 269         case PIPE_CAP_CLIP_HALFZ:
 270         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 271         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 272         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 273         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 274         case PIPE_CAP_TGSI_TEXCOORD:
 275         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 276         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 277         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 278         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 279         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 280                 return 1;
 281
 282         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 283                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 284
 285         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 286                 return (sscreen->b.info.drm_major == 2 &&
 287                         sscreen->b.info.drm_minor >= 43) ||
 288                        sscreen->b.info.drm_major == 3;
 289
 290         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 291                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 292                 return sscreen->b.chip_class < CIK ||
 293                        (sscreen->b.info.drm_major == 2 &&
 294                         sscreen->b.info.drm_minor >= 35) ||
 295                        sscreen->b.info.drm_major == 3;
 296
 297         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 298                 return R600_MAP_BUFFER_ALIGNMENT;
 299
 300         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 301         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 302                 return 4;
 303
 304         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 305                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 306
 307         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 308                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 309
 310         case PIPE_CAP_TEXTURE_QUERY_LOD:
 311         case PIPE_CAP_TEXTURE_GATHER_SM5:
 312                 return HAVE_LLVM >= 0x0305;
 313         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 314                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 315
 316         /* Unsupported features. */
 317         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 318         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 319         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 320         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 321         case PIPE_CAP_USER_VERTEX_BUFFERS:
 322         case PIPE_CAP_FAKE_SW_MSAA:
 323         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 324         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 325         case PIPE_CAP_VERTEXID_NOBASE:
 326                 return 0;
 327
 328         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 329                 return 30;
 330
 331         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 332                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 333
 334         /* Stream output. */
 335         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 336                 return sscreen->b.has_streamout ? 4 : 0;
 337         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 338                 return sscreen->b.has_streamout ? 1 : 0;
 339         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 340         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 341                 return sscreen->b.has_streamout ? 32*4 : 0;
 342
 343         /* Geometry shader output. */
 344         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 345                 return 1024;
 346         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 347                 return 4095;
 348         case PIPE_CAP_MAX_VERTEX_STREAMS:
 349                 return 4;
 350
 351         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 352                 return 2048;
 353
 354         /* Texturing. */
 355         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 356         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 357                 return 15; /* 16384 */
 358         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 359                 /* textures support 8192, but layered rendering supports 2048 */
 360                 return 12;
 361         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 362                 /* textures support 8192, but layered rendering supports 2048 */
 363                 return 2048;
 364
 365         /* Render targets. */
 366         case PIPE_CAP_MAX_RENDER_TARGETS:
 367                 return 8;
 368
 369         case PIPE_CAP_MAX_VIEWPORTS:
 370                 return 16;
 371
 372         /* Timer queries, present when the clock frequency is non zero. */
 373         case PIPE_CAP_QUERY_TIMESTAMP:
 374         case PIPE_CAP_QUERY_TIME_ELAPSED:
 375                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 376
 377         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 378         case PIPE_CAP_MIN_TEXEL_OFFSET:
 379                 return -32;
 380
 381         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 382         case PIPE_CAP_MAX_TEXEL_OFFSET:
 383                 return 31;
 384
 385         case PIPE_CAP_ENDIANNESS:
 386                 return PIPE_ENDIAN_LITTLE;
 387
 388         case PIPE_CAP_VENDOR_ID:
 389                 return 0x1002;
 390         case PIPE_CAP_DEVICE_ID:
 391                 return sscreen->b.info.pci_id;
 392         case PIPE_CAP_ACCELERATED:
 393                 return 1;
 394         case PIPE_CAP_VIDEO_MEMORY:
 395                 return sscreen->b.info.vram_size >> 20;
 396         case PIPE_CAP_UMA:
 397                 return 0;
 398         }
 399         return 0;
 400 }
 401
 402 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 403 {
 404         switch(shader)
 405         {
 406         case PIPE_SHADER_FRAGMENT:
 407         case PIPE_SHADER_VERTEX:
 408         case PIPE_SHADER_GEOMETRY:
 409                 break;
 410         case PIPE_SHADER_TESS_CTRL:
 411         case PIPE_SHADER_TESS_EVAL:
 412                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 413                 if (HAVE_LLVM < 0x0306 ||
 414                     (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
 415                         return 0;
 416                 break;
 417         case PIPE_SHADER_COMPUTE:
 418                 switch (param) {
 419                 case PIPE_SHADER_CAP_PREFERRED_IR:
 420 #if HAVE_LLVM < 0x0306
 421                         return PIPE_SHADER_IR_LLVM;
 422 #else
 423                         return PIPE_SHADER_IR_NATIVE;
 424 #endif
 425                 case PIPE_SHADER_CAP_DOUBLES:
 426                         return HAVE_LLVM >= 0x0307;
 427
 428                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 429                         uint64_t max_const_buffer_size;
 430                         pscreen->get_compute_param(pscreen,
 431                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 432                                 &max_const_buffer_size);
 433                         return max_const_buffer_size;
 434                 }
 435                 default:
 436                         /* If compute shaders don't require a special value
 437                          * for this cap, we can return the same value we
 438                          * do for other shader types. */
 439                         break;
 440                 }
 441                 break;
 442         default:
 443                 return 0;
 444         }
 445
 446         switch (param) {
 447         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 448         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 449         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 450         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 451                 return 16384;
 452         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 453                 return 32;
 454         case PIPE_SHADER_CAP_MAX_INPUTS:
 455                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 456         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 457                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 458         case PIPE_SHADER_CAP_MAX_TEMPS:
 459                 return 256; /* Max native temporaries. */
 460         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 461                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 462         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 463                 return SI_NUM_USER_CONST_BUFFERS;
 464         case PIPE_SHADER_CAP_MAX_PREDS:
 465                 return 0; /* FIXME */
 466         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 467                 return 1;
 468         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 469                 return 1;
 470         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 471                 /* Indirection of geometry shader input dimension is not
 472                  * handled yet
 473                  */
 474                 return shader != PIPE_SHADER_GEOMETRY;
 475         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 476         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 477         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 478                 return 1;
 479         case PIPE_SHADER_CAP_INTEGERS:
 480                 return 1;
 481         case PIPE_SHADER_CAP_SUBROUTINES:
 482                 return 0;
 483         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 484         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 485                 return 16;
 486         case PIPE_SHADER_CAP_PREFERRED_IR:
 487                 return PIPE_SHADER_IR_TGSI;
 488         case PIPE_SHADER_CAP_DOUBLES:
 489                 return HAVE_LLVM >= 0x0307;
 490         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 491         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 492                 return 0;
 493         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 494         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 495                 return 1;
 496         }
 497         return 0;
 498 }
 499
 500 static void si_destroy_screen(struct pipe_screen* pscreen)
 501 {
 502         struct si_screen *sscreen = (struct si_screen *)pscreen;
 503
 504         if (sscreen == NULL)
 505                 return;
 506
 507         if (!sscreen->b.ws->unref(sscreen->b.ws))
 508                 return;
 509
 510         r600_destroy_common_screen(&sscreen->b);
 511 }
 512
 513 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 514
 515 /* Initialize pipe config. This is especially important for GPUs
 516  * with 16 pipes and more where it's initialized incorrectly by
 517  * the TILING_CONFIG ioctl. */
 518 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 519 {
 520         unsigned mode2d;
 521
 522         /* This is okay, because there can be no 2D tiling without
 523          * the tile mode array, so we won't need the pipe config.
 524          * Return "success".
 525          */
 526         if (!sscreen->b.info.si_tile_mode_array_valid)
 527                 return true;
 528
 529         /* The same index is used for the 2D mode on CIK too. */
 530         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 531
 532         switch (G_009910_PIPE_CONFIG(mode2d)) {
 533         case V_02803C_ADDR_SURF_P2:
 534                 sscreen->b.tiling_info.num_channels = 2;
 535                 break;
 536         case V_02803C_X_ADDR_SURF_P4_8X16:
 537         case V_02803C_X_ADDR_SURF_P4_16X16:
 538         case V_02803C_X_ADDR_SURF_P4_16X32:
 539         case V_02803C_X_ADDR_SURF_P4_32X32:
 540                 sscreen->b.tiling_info.num_channels = 4;
 541                 break;
 542         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 543         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 544         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 545         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 546         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 547         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 548         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 549                 sscreen->b.tiling_info.num_channels = 8;
 550                 break;
 551         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 552         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 553                 sscreen->b.tiling_info.num_channels = 16;
 554                 break;
 555         default:
 556                 assert(0);
 557                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 558                         G_009910_PIPE_CONFIG(mode2d));
 559                 return false;
 560         }
 561         return true;
 562 }
 563
 564 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 565 {
 566         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 567
 568         if (sscreen == NULL) {
 569                 return NULL;
 570         }
 571
 572         /* Set functions first. */
 573         sscreen->b.b.context_create = si_create_context;
 574         sscreen->b.b.destroy = si_destroy_screen;
 575         sscreen->b.b.get_param = si_get_param;
 576         sscreen->b.b.get_shader_param = si_get_shader_param;
 577         sscreen->b.b.is_format_supported = si_is_format_supported;
 578         sscreen->b.b.resource_create = r600_resource_create_common;
 579
 580         if (!r600_common_screen_init(&sscreen->b, ws) ||
 581             !si_initialize_pipe_config(sscreen)) {
 582                 FREE(sscreen);
 583                 return NULL;
 584         }
 585
 586         sscreen->b.has_cp_dma = true;
 587         sscreen->b.has_streamout = true;
 588
 589         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 590                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 591
 592         /* Create the auxiliary context. This must be done last. */
 593         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 594
 595         return &sscreen->b.b;
 596 }