src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_suballoc.h"
  32 #include "util/u_tests.h"
  33 #include "vl/vl_decoder.h"
  34 #include "../ddebug/dd_util.h"
  35
  36 /*
  37  * pipe_context
  38  */
  39 static void si_destroy_context(struct pipe_context *context)
  40 {
  41         struct si_context *sctx = (struct si_context *)context;
  42         int i;
  43
  44         /* Unreference the framebuffer normally to disable related logic
  45          * properly.
  46          */
  47         struct pipe_framebuffer_state fb = {};
  48         context->set_framebuffer_state(context, &fb);
  49
  50         si_release_all_descriptors(sctx);
  51
  52         if (sctx->ce_suballocator)
  53                 u_suballocator_destroy(sctx->ce_suballocator);
  54
  55         r600_resource_reference(&sctx->ce_ram_saved_buffer, NULL);
  56         pipe_resource_reference(&sctx->esgs_ring, NULL);
  57         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  58         pipe_resource_reference(&sctx->tf_ring, NULL);
  59         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  60         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  61         r600_resource_reference(&sctx->border_color_buffer, NULL);
  62         free(sctx->border_color_table);
  63         r600_resource_reference(&sctx->scratch_buffer, NULL);
  64         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  65
  66         si_pm4_free_state(sctx, sctx->init_config, ~0);
  67         if (sctx->init_config_gs_rings)
  68                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  69         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  70                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  71
  72         if (sctx->fixed_func_tcs_shader.cso)
  73                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  74         if (sctx->custom_dsa_flush)
  75                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  76         if (sctx->custom_blend_resolve)
  77                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  78         if (sctx->custom_blend_decompress)
  79                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  80         if (sctx->custom_blend_fastclear)
  81                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  82         if (sctx->custom_blend_dcc_decompress)
  83                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  84
  85         if (sctx->blitter)
  86                 util_blitter_destroy(sctx->blitter);
  87
  88         r600_common_context_cleanup(&sctx->b);
  89
  90         LLVMDisposeTargetMachine(sctx->tm);
  91
  92         r600_resource_reference(&sctx->trace_buf, NULL);
  93         r600_resource_reference(&sctx->last_trace_buf, NULL);
  94         radeon_clear_saved_cs(&sctx->last_gfx);
  95
  96         FREE(sctx);
  97 }
  98
  99 static enum pipe_reset_status
 100 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 101 {
 102         struct si_context *sctx = (struct si_context *)ctx;
 103
 104         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 105 }
 106
 107 /* Apitrace profiling:
 108  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 109  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 110  *      and remember its number.
 111  *   3) In Mesa, enable queries and performance counters around that draw
 112  *      call and print the results.
 113  *   4) glretrace --benchmark --markers ..
 114  */
 115 static void si_emit_string_marker(struct pipe_context *ctx,
 116                                   const char *string, int len)
 117 {
 118         struct si_context *sctx = (struct si_context *)ctx;
 119
 120         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 121 }
 122
 123 static LLVMTargetMachineRef
 124 si_create_llvm_target_machine(struct si_screen *sscreen)
 125 {
 126         const char *triple = "amdgcn--";
 127         char features[256];
 128
 129         snprintf(features, sizeof(features),
 130                  "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s",
 131                  sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
 132                  sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
 133
 134         return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple), triple,
 135                                        r600_get_llvm_processor_name(sscreen->b.family),
 136                                        features,
 137                                        LLVMCodeGenLevelDefault,
 138                                        LLVMRelocDefault,
 139                                        LLVMCodeModelDefault);
 140 }
 141
 142 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 143                                               unsigned flags)
 144 {
 145         struct si_context *sctx = CALLOC_STRUCT(si_context);
 146         struct si_screen* sscreen = (struct si_screen *)screen;
 147         struct radeon_winsys *ws = sscreen->b.ws;
 148         int shader, i;
 149
 150         if (!sctx)
 151                 return NULL;
 152
 153         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 154                 flags |= PIPE_CONTEXT_DEBUG;
 155
 156         if (flags & PIPE_CONTEXT_DEBUG)
 157                 sscreen->record_llvm_ir = true; /* racy but not critical */
 158
 159         sctx->b.b.screen = screen; /* this must be set first */
 160         sctx->b.b.priv = NULL;
 161         sctx->b.b.destroy = si_destroy_context;
 162         sctx->b.b.emit_string_marker = si_emit_string_marker;
 163         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 164         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 165         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 166
 167         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 168                 goto fail;
 169
 170         if (sscreen->b.info.drm_major == 3)
 171                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 172
 173         si_init_blit_functions(sctx);
 174         si_init_compute_functions(sctx);
 175         si_init_cp_dma_functions(sctx);
 176         si_init_debug_functions(sctx);
 177
 178         if (sscreen->b.info.has_hw_decode) {
 179                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 180                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 181         } else {
 182                 sctx->b.b.create_video_codec = vl_create_decoder;
 183                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 184         }
 185
 186         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 187                                        si_context_gfx_flush, sctx);
 188
 189         /* SI + AMDGPU + CE = GPU hang */
 190         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
 191             sscreen->b.chip_class != SI &&
 192             /* These can't use CE due to a power gating bug in the kernel. */
 193             sscreen->b.family != CHIP_CARRIZO &&
 194             sscreen->b.family != CHIP_STONEY &&
 195             /* Some CE bug is causing green screen corruption w/ MPV video
 196              * playback and occasional corruption w/ 3D. */
 197             sscreen->b.chip_class != GFX9) {
 198                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 199                 if (!sctx->ce_ib)
 200                         goto fail;
 201
 202                 if (ws->cs_add_const_preamble_ib) {
 203                         sctx->ce_preamble_ib =
 204                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 205
 206                         if (!sctx->ce_preamble_ib)
 207                                 goto fail;
 208                 }
 209
 210                 sctx->ce_suballocator =
 211                         u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
 212                                               PIPE_USAGE_DEFAULT,
 213                                               R600_RESOURCE_FLAG_UNMAPPABLE, false);
 214                 if (!sctx->ce_suballocator)
 215                         goto fail;
 216         }
 217
 218         sctx->b.gfx.flush = si_context_gfx_flush;
 219
 220         /* Border colors. */
 221         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 222                                           sizeof(*sctx->border_color_table));
 223         if (!sctx->border_color_table)
 224                 goto fail;
 225
 226         sctx->border_color_buffer = (struct r600_resource*)
 227                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 228                                    SI_MAX_BORDER_COLORS *
 229                                    sizeof(*sctx->border_color_table));
 230         if (!sctx->border_color_buffer)
 231                 goto fail;
 232
 233         sctx->border_color_map =
 234                 ws->buffer_map(sctx->border_color_buffer->buf,
 235                                NULL, PIPE_TRANSFER_WRITE);
 236         if (!sctx->border_color_map)
 237                 goto fail;
 238
 239         si_init_all_descriptors(sctx);
 240         si_init_state_functions(sctx);
 241         si_init_shader_functions(sctx);
 242         si_init_ia_multi_vgt_param_table(sctx);
 243
 244         if (sctx->b.chip_class >= CIK)
 245                 cik_init_sdma_functions(sctx);
 246         else
 247                 si_init_dma_functions(sctx);
 248
 249         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 250                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 251
 252         sctx->blitter = util_blitter_create(&sctx->b.b);
 253         if (sctx->blitter == NULL)
 254                 goto fail;
 255         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 256
 257         sctx->sample_mask.sample_mask = 0xffff;
 258
 259         /* these must be last */
 260         si_begin_new_cs(sctx);
 261
 262         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 263          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 264         if (sctx->b.chip_class == CIK) {
 265                 sctx->null_const_buf.buffer =
 266                         r600_aligned_buffer_create(screen,
 267                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 268                                                    PIPE_USAGE_DEFAULT, 16,
 269                                                    sctx->screen->b.info.tcc_cache_line_size);
 270                 if (!sctx->null_const_buf.buffer)
 271                         goto fail;
 272                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 273
 274                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 275                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 276                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 277                                                               &sctx->null_const_buf);
 278                         }
 279                 }
 280
 281                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 282                                  &sctx->null_const_buf);
 283                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 284                                  &sctx->null_const_buf);
 285                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 286                                  &sctx->null_const_buf);
 287                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 288                                  &sctx->null_const_buf);
 289
 290                 /* Clear the NULL constant buffer, because loads should return zeros. */
 291                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 292                                      sctx->null_const_buf.buffer->width0, 0,
 293                                      R600_COHERENCY_SHADER);
 294         }
 295
 296         uint64_t max_threads_per_block;
 297         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 298                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 299                                   &max_threads_per_block);
 300
 301         /* The maximum number of scratch waves. Scratch space isn't divided
 302          * evenly between CUs. The number is only a function of the number of CUs.
 303          * We can decrease the constant to decrease the scratch buffer size.
 304          *
 305          * sctx->scratch_waves must be >= the maximum posible size of
 306          * 1 threadgroup, so that the hw doesn't hang from being unable
 307          * to start any.
 308          *
 309          * The recommended value is 4 per CU at most. Higher numbers don't
 310          * bring much benefit, but they still occupy chip resources (think
 311          * async compute). I've seen ~2% performance difference between 4 and 32.
 312          */
 313         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 314                                    max_threads_per_block / 64);
 315
 316         sctx->tm = si_create_llvm_target_machine(sscreen);
 317
 318         return &sctx->b.b;
 319 fail:
 320         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 321         si_destroy_context(&sctx->b.b);
 322         return NULL;
 323 }
 324
 325 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 326                                                    void *priv, unsigned flags)
 327 {
 328         struct si_screen *sscreen = (struct si_screen *)screen;
 329         struct pipe_context *ctx = si_create_context(screen, flags);
 330
 331         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 332                 return ctx;
 333
 334         /* Clover (compute-only) is unsupported.
 335          *
 336          * Since the threaded context creates shader states from the non-driver
 337          * thread, asynchronous compilation is required for create_{shader}_-
 338          * state not to use pipe_context. Debug contexts (ddebug) disable
 339          * asynchronous compilation, so don't use the threaded context with
 340          * those.
 341          */
 342         if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
 343                 return ctx;
 344
 345         /* When shaders are logged to stderr, asynchronous compilation is
 346          * disabled too. */
 347         if (sscreen->b.debug_flags & (DBG_VS | DBG_TCS | DBG_TES | DBG_GS |
 348                                       DBG_PS | DBG_CS))
 349                 return ctx;
 350
 351         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 352                                        r600_replace_buffer_storage,
 353                                        &((struct si_context*)ctx)->b.tc);
 354 }
 355
 356 /*
 357  * pipe_screen
 358  */
 359 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 360 {
 361         /* Old kernels disallowed some register writes for SI
 362          * that are used for indirect dispatches. */
 363         return (sscreen->b.chip_class >= CIK ||
 364                 sscreen->b.info.drm_major == 3 ||
 365                 (sscreen->b.info.drm_major == 2 &&
 366                  sscreen->b.info.drm_minor >= 45));
 367 }
 368
 369 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 370 {
 371         struct si_screen *sscreen = (struct si_screen *)pscreen;
 372
 373         switch (param) {
 374         /* Supported features (boolean caps). */
 375         case PIPE_CAP_ACCELERATED:
 376         case PIPE_CAP_TWO_SIDED_STENCIL:
 377         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 378         case PIPE_CAP_ANISOTROPIC_FILTER:
 379         case PIPE_CAP_POINT_SPRITE:
 380         case PIPE_CAP_OCCLUSION_QUERY:
 381         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 382         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 383         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 384         case PIPE_CAP_TEXTURE_SWIZZLE:
 385         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 386         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 387         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 388         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 389         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 390         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 391         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 392         case PIPE_CAP_SM3:
 393         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 394         case PIPE_CAP_PRIMITIVE_RESTART:
 395         case PIPE_CAP_CONDITIONAL_RENDER:
 396         case PIPE_CAP_TEXTURE_BARRIER:
 397         case PIPE_CAP_INDEP_BLEND_ENABLE:
 398         case PIPE_CAP_INDEP_BLEND_FUNC:
 399         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 400         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 401         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 402         case PIPE_CAP_START_INSTANCE:
 403         case PIPE_CAP_NPOT_TEXTURES:
 404         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 405         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 406         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 407         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 408         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 409         case PIPE_CAP_TGSI_INSTANCEID:
 410         case PIPE_CAP_COMPUTE:
 411         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 412         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 413         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 414         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 415         case PIPE_CAP_CUBE_MAP_ARRAY:
 416         case PIPE_CAP_SAMPLE_SHADING:
 417         case PIPE_CAP_DRAW_INDIRECT:
 418         case PIPE_CAP_CLIP_HALFZ:
 419         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 420         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 421         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 422         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 423         case PIPE_CAP_TGSI_TEXCOORD:
 424         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 425         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 426         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 427         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 428         case PIPE_CAP_SHAREABLE_SHADERS:
 429         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 430         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 431         case PIPE_CAP_TEXTURE_QUERY_LOD:
 432         case PIPE_CAP_TEXTURE_GATHER_SM5:
 433         case PIPE_CAP_TGSI_TXQS:
 434         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 435         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 436         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 437         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 438         case PIPE_CAP_INVALIDATE_BUFFER:
 439         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 440         case PIPE_CAP_QUERY_MEMORY_INFO:
 441         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 442         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 443         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 444         case PIPE_CAP_GENERATE_MIPMAP:
 445         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 446         case PIPE_CAP_STRING_MARKER:
 447         case PIPE_CAP_CLEAR_TEXTURE:
 448         case PIPE_CAP_CULL_DISTANCE:
 449         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 450         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 451         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 452         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 453         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 454         case PIPE_CAP_DOUBLES:
 455         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 456         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 457         case PIPE_CAP_INT64:
 458         case PIPE_CAP_INT64_DIVMOD:
 459         case PIPE_CAP_TGSI_CLOCK:
 460         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 461         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 462                 return 1;
 463
 464         case PIPE_CAP_TGSI_VOTE:
 465                 return HAVE_LLVM >= 0x0400;
 466
 467         case PIPE_CAP_TGSI_BALLOT:
 468                 return HAVE_LLVM >= 0x0500;
 469
 470         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 471                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 472
 473         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 474                 return (sscreen->b.info.drm_major == 2 &&
 475                         sscreen->b.info.drm_minor >= 43) ||
 476                        sscreen->b.info.drm_major == 3;
 477
 478         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 479                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 480                 return sscreen->b.chip_class < CIK ||
 481                        (sscreen->b.info.drm_major == 2 &&
 482                         sscreen->b.info.drm_minor >= 35) ||
 483                        sscreen->b.info.drm_major == 3;
 484
 485         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 486                 return R600_MAP_BUFFER_ALIGNMENT;
 487
 488         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 489         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 490         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 491         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 492         case PIPE_CAP_MAX_VERTEX_STREAMS:
 493         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 494                 return 4;
 495
 496         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 497                 if (si_have_tgsi_compute(sscreen))
 498                         return 450;
 499                 return 420;
 500
 501         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 502                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 503
 504         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 505         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 506         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 507                 /* SI doesn't support unaligned loads.
 508                  * CIK needs DRM 2.50.0 on radeon. */
 509                 return sscreen->b.chip_class == SI ||
 510                        (sscreen->b.info.drm_major == 2 &&
 511                         sscreen->b.info.drm_minor < 50);
 512
 513         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 514                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 515                  * faults are mitigated in software.
 516                  */
 517                 if (sscreen->b.chip_class >= CIK &&
 518                     sscreen->b.info.drm_major == 3 &&
 519                     sscreen->b.info.drm_minor >= 13)
 520                         return RADEON_SPARSE_PAGE_SIZE;
 521                 return 0;
 522
 523         /* Unsupported features. */
 524         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 525         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 526         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 527         case PIPE_CAP_USER_VERTEX_BUFFERS:
 528         case PIPE_CAP_FAKE_SW_MSAA:
 529         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 530         case PIPE_CAP_VERTEXID_NOBASE:
 531         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 532         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 533         case PIPE_CAP_NATIVE_FENCE_FD:
 534         case PIPE_CAP_TGSI_FS_FBFETCH:
 535         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 536         case PIPE_CAP_UMA:
 537         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 538                 return 0;
 539
 540         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 541                 return si_have_tgsi_compute(sscreen);
 542
 543         case PIPE_CAP_DRAW_PARAMETERS:
 544         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 545         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 546                 return sscreen->has_draw_indirect_multi;
 547
 548         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 549                 return 30;
 550
 551         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 552                 return sscreen->b.chip_class <= VI ?
 553                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 554
 555         /* Stream output. */
 556         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 557         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 558                 return 32*4;
 559
 560         /* Geometry shader output. */
 561         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 562                 return 1024;
 563         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 564                 return 4095;
 565
 566         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 567                 return 2048;
 568
 569         /* Texturing. */
 570         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 571         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 572                 return 15; /* 16384 */
 573         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 574                 /* textures support 8192, but layered rendering supports 2048 */
 575                 return 12;
 576         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 577                 /* textures support 8192, but layered rendering supports 2048 */
 578                 return 2048;
 579
 580         /* Viewports and render targets. */
 581         case PIPE_CAP_MAX_VIEWPORTS:
 582                 return R600_MAX_VIEWPORTS;
 583         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 584         case PIPE_CAP_MAX_RENDER_TARGETS:
 585                 return 8;
 586
 587         /* Timer queries, present when the clock frequency is non zero. */
 588         case PIPE_CAP_QUERY_TIMESTAMP:
 589         case PIPE_CAP_QUERY_TIME_ELAPSED:
 590                 return sscreen->b.info.clock_crystal_freq != 0;
 591
 592         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 593         case PIPE_CAP_MIN_TEXEL_OFFSET:
 594                 return -32;
 595
 596         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 597         case PIPE_CAP_MAX_TEXEL_OFFSET:
 598                 return 31;
 599
 600         case PIPE_CAP_ENDIANNESS:
 601                 return PIPE_ENDIAN_LITTLE;
 602
 603         case PIPE_CAP_VENDOR_ID:
 604                 return ATI_VENDOR_ID;
 605         case PIPE_CAP_DEVICE_ID:
 606                 return sscreen->b.info.pci_id;
 607         case PIPE_CAP_VIDEO_MEMORY:
 608                 return sscreen->b.info.vram_size >> 20;
 609         case PIPE_CAP_PCI_GROUP:
 610                 return sscreen->b.info.pci_domain;
 611         case PIPE_CAP_PCI_BUS:
 612                 return sscreen->b.info.pci_bus;
 613         case PIPE_CAP_PCI_DEVICE:
 614                 return sscreen->b.info.pci_dev;
 615         case PIPE_CAP_PCI_FUNCTION:
 616                 return sscreen->b.info.pci_func;
 617         }
 618         return 0;
 619 }
 620
 621 static int si_get_shader_param(struct pipe_screen* pscreen,
 622                                enum pipe_shader_type shader,
 623                                enum pipe_shader_cap param)
 624 {
 625         struct si_screen *sscreen = (struct si_screen *)pscreen;
 626
 627         switch(shader)
 628         {
 629         case PIPE_SHADER_FRAGMENT:
 630         case PIPE_SHADER_VERTEX:
 631         case PIPE_SHADER_GEOMETRY:
 632         case PIPE_SHADER_TESS_CTRL:
 633         case PIPE_SHADER_TESS_EVAL:
 634                 break;
 635         case PIPE_SHADER_COMPUTE:
 636                 switch (param) {
 637                 case PIPE_SHADER_CAP_PREFERRED_IR:
 638                         return PIPE_SHADER_IR_NATIVE;
 639
 640                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 641                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 642
 643                         if (si_have_tgsi_compute(sscreen))
 644                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 645
 646                         return ir;
 647                 }
 648
 649                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 650                         uint64_t max_const_buffer_size;
 651                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 652                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 653                                 &max_const_buffer_size);
 654                         return MIN2(max_const_buffer_size, INT_MAX);
 655                 }
 656                 default:
 657                         /* If compute shaders don't require a special value
 658                          * for this cap, we can return the same value we
 659                          * do for other shader types. */
 660                         break;
 661                 }
 662                 break;
 663         default:
 664                 return 0;
 665         }
 666
 667         switch (param) {
 668         /* Shader limits. */
 669         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 670         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 671         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 672         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 673         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 674                 return 16384;
 675         case PIPE_SHADER_CAP_MAX_INPUTS:
 676                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 677         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 678                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 679         case PIPE_SHADER_CAP_MAX_TEMPS:
 680                 return 256; /* Max native temporaries. */
 681         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 682                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 683         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 684                 return SI_NUM_CONST_BUFFERS;
 685         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 686         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 687                 return SI_NUM_SAMPLERS;
 688         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 689                 return SI_NUM_SHADER_BUFFERS;
 690         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 691                 return SI_NUM_IMAGES;
 692         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 693                 return 32;
 694         case PIPE_SHADER_CAP_PREFERRED_IR:
 695                 return PIPE_SHADER_IR_TGSI;
 696         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 697                 return 3;
 698
 699         /* Supported boolean features. */
 700         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 701         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 702         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 703         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 704         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 705         case PIPE_SHADER_CAP_INTEGERS:
 706         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 707         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 708         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 709                 return 1;
 710
 711         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 712                 /* TODO: Indirection of geometry shader input dimension is not
 713                  * handled yet
 714                  */
 715                 return shader != PIPE_SHADER_GEOMETRY;
 716
 717         /* Unsupported boolean features. */
 718         case PIPE_SHADER_CAP_SUBROUTINES:
 719         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 720         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 721         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 722                 return 0;
 723         }
 724         return 0;
 725 }
 726
 727 static void si_destroy_screen(struct pipe_screen* pscreen)
 728 {
 729         struct si_screen *sscreen = (struct si_screen *)pscreen;
 730         struct si_shader_part *parts[] = {
 731                 sscreen->vs_prologs,
 732                 sscreen->tcs_epilogs,
 733                 sscreen->gs_prologs,
 734                 sscreen->ps_prologs,
 735                 sscreen->ps_epilogs
 736         };
 737         unsigned i;
 738
 739         if (!sscreen->b.ws->unref(sscreen->b.ws))
 740                 return;
 741
 742         util_queue_destroy(&sscreen->shader_compiler_queue);
 743
 744         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 745                 if (sscreen->tm[i])
 746                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 747
 748         /* Free shader parts. */
 749         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 750                 while (parts[i]) {
 751                         struct si_shader_part *part = parts[i];
 752
 753                         parts[i] = part->next;
 754                         radeon_shader_binary_clean(&part->binary);
 755                         FREE(part);
 756                 }
 757         }
 758         mtx_destroy(&sscreen->shader_parts_mutex);
 759         si_destroy_shader_cache(sscreen);
 760         r600_destroy_common_screen(&sscreen->b);
 761 }
 762
 763 static bool si_init_gs_info(struct si_screen *sscreen)
 764 {
 765         switch (sscreen->b.family) {
 766         case CHIP_OLAND:
 767         case CHIP_HAINAN:
 768         case CHIP_KAVERI:
 769         case CHIP_KABINI:
 770         case CHIP_MULLINS:
 771         case CHIP_ICELAND:
 772         case CHIP_CARRIZO:
 773         case CHIP_STONEY:
 774                 sscreen->gs_table_depth = 16;
 775                 return true;
 776         case CHIP_TAHITI:
 777         case CHIP_PITCAIRN:
 778         case CHIP_VERDE:
 779         case CHIP_BONAIRE:
 780         case CHIP_HAWAII:
 781         case CHIP_TONGA:
 782         case CHIP_FIJI:
 783         case CHIP_POLARIS10:
 784         case CHIP_POLARIS11:
 785         case CHIP_POLARIS12:
 786         case CHIP_VEGA10:
 787         case CHIP_RAVEN:
 788                 sscreen->gs_table_depth = 32;
 789                 return true;
 790         default:
 791                 return false;
 792         }
 793 }
 794
 795 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 796 {
 797         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 798         unsigned i;
 799
 800         if (!family)
 801                 return;
 802
 803         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 804                 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
 805                         /* Override family and chip_class. */
 806                         sscreen->b.family = sscreen->b.info.family = i;
 807
 808                         if (i >= CHIP_VEGA10)
 809                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 810                         else if (i >= CHIP_TONGA)
 811                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 812                         else if (i >= CHIP_BONAIRE)
 813                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 814                         else
 815                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 816
 817                         /* Don't submit any IBs. */
 818                         setenv("RADEON_NOOP", "1", 1);
 819                         return;
 820                 }
 821         }
 822
 823         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 824         exit(1);
 825 }
 826
 827 static void si_test_vmfault(struct si_screen *sscreen)
 828 {
 829         struct pipe_context *ctx = sscreen->b.aux_context;
 830         struct si_context *sctx = (struct si_context *)ctx;
 831         struct pipe_resource *buf =
 832                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 833
 834         if (!buf) {
 835                 puts("Buffer allocation failed.");
 836                 exit(1);
 837         }
 838
 839         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 840
 841         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
 842                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 843                 ctx->flush(ctx, NULL, 0);
 844                 puts("VM fault test: CP - done.");
 845         }
 846         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
 847                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 848                 ctx->flush(ctx, NULL, 0);
 849                 puts("VM fault test: SDMA - done.");
 850         }
 851         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
 852                 util_test_constant_buffer(ctx, buf);
 853                 puts("VM fault test: Shader - done.");
 854         }
 855         exit(0);
 856 }
 857
 858 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 859 {
 860         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 861         unsigned num_cpus, num_compiler_threads, i;
 862
 863         if (!sscreen) {
 864                 return NULL;
 865         }
 866
 867         /* Set functions first. */
 868         sscreen->b.b.context_create = si_pipe_create_context;
 869         sscreen->b.b.destroy = si_destroy_screen;
 870         sscreen->b.b.get_param = si_get_param;
 871         sscreen->b.b.get_shader_param = si_get_shader_param;
 872         sscreen->b.b.resource_create = r600_resource_create_common;
 873
 874         si_init_screen_state_functions(sscreen);
 875
 876         if (!r600_common_screen_init(&sscreen->b, ws) ||
 877             !si_init_gs_info(sscreen) ||
 878             !si_init_shader_cache(sscreen)) {
 879                 FREE(sscreen);
 880                 return NULL;
 881         }
 882
 883         /* Only enable as many threads as we have target machines and CPUs. */
 884         num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 885         num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
 886
 887         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 888                              32, num_compiler_threads)) {
 889                 si_destroy_shader_cache(sscreen);
 890                 FREE(sscreen);
 891                 return NULL;
 892         }
 893
 894         si_handle_env_var_force_family(sscreen);
 895
 896         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 897                 si_init_perfcounters(sscreen);
 898
 899         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 900          * around by setting 4K granularity.
 901          */
 902         sscreen->tess_offchip_block_dw_size =
 903                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
 904
 905         sscreen->has_distributed_tess =
 906                 sscreen->b.chip_class >= VI &&
 907                 sscreen->b.info.max_se >= 2;
 908
 909         sscreen->has_draw_indirect_multi =
 910                 (sscreen->b.family >= CHIP_POLARIS10) ||
 911                 (sscreen->b.chip_class == VI &&
 912                  sscreen->b.info.pfp_fw_version >= 121 &&
 913                  sscreen->b.info.me_fw_version >= 87) ||
 914                 (sscreen->b.chip_class == CIK &&
 915                  sscreen->b.info.pfp_fw_version >= 211 &&
 916                  sscreen->b.info.me_fw_version >= 173) ||
 917                 (sscreen->b.chip_class == SI &&
 918                  sscreen->b.info.pfp_fw_version >= 121 &&
 919                  sscreen->b.info.me_fw_version >= 87);
 920
 921         sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
 922         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
 923                                             sscreen->b.family <= CHIP_POLARIS12) ||
 924                                            sscreen->b.family == CHIP_VEGA10 ||
 925                                            sscreen->b.family == CHIP_RAVEN;
 926
 927         sscreen->b.has_cp_dma = true;
 928         sscreen->b.has_streamout = true;
 929
 930         /* Some chips have RB+ registers, but don't support RB+. Those must
 931          * always disable it.
 932          */
 933         if (sscreen->b.family == CHIP_STONEY ||
 934             sscreen->b.chip_class >= GFX9) {
 935                 sscreen->b.has_rbplus = true;
 936
 937                 sscreen->b.rbplus_allowed =
 938                         !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
 939                         (sscreen->b.family == CHIP_STONEY ||
 940                          sscreen->b.family == CHIP_RAVEN);
 941         }
 942
 943         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
 944         sscreen->use_monolithic_shaders =
 945                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 946
 947         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
 948                                             SI_CONTEXT_INV_VMEM_L1 |
 949                                             SI_CONTEXT_INV_GLOBAL_L2;
 950         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
 951
 952         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
 953                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 954
 955         for (i = 0; i < num_compiler_threads; i++)
 956                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 957
 958         /* Create the auxiliary context. This must be done last. */
 959         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
 960
 961         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 962                 r600_test_dma(&sscreen->b);
 963
 964         if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
 965                                       DBG_TEST_VMFAULT_SDMA |
 966                                       DBG_TEST_VMFAULT_SHADER))
 967                 si_test_vmfault(sscreen);
 968
 969         return &sscreen->b.b;
 970 }