2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
26 #include "si_shader_internal.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/hash_table.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_suballoc.h"
34 #include "util/u_tests.h"
35 #include "util/xmlconfig.h"
36 #include "vl/vl_decoder.h"
37 #include "../ddebug/dd_util.h"
39 #include "compiler/nir/nir.h"
44 static void si_destroy_context(struct pipe_context
*context
)
46 struct si_context
*sctx
= (struct si_context
*)context
;
49 /* Unreference the framebuffer normally to disable related logic
52 struct pipe_framebuffer_state fb
= {};
53 if (context
->set_framebuffer_state
)
54 context
->set_framebuffer_state(context
, &fb
);
56 si_release_all_descriptors(sctx
);
58 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
59 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
60 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
61 pipe_resource_reference(&sctx
->tess_offchip_ring
, NULL
);
62 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
63 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
64 free(sctx
->border_color_table
);
65 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
66 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
67 r600_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
69 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
70 if (sctx
->init_config_gs_rings
)
71 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
72 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
73 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
75 if (sctx
->fixed_func_tcs_shader
.cso
)
76 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
.cso
);
77 if (sctx
->custom_dsa_flush
)
78 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
79 if (sctx
->custom_blend_resolve
)
80 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
81 if (sctx
->custom_blend_fmask_decompress
)
82 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fmask_decompress
);
83 if (sctx
->custom_blend_eliminate_fastclear
)
84 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_eliminate_fastclear
);
85 if (sctx
->custom_blend_dcc_decompress
)
86 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_dcc_decompress
);
87 if (sctx
->vs_blit_pos
)
88 sctx
->b
.b
.delete_vs_state(&sctx
->b
.b
, sctx
->vs_blit_pos
);
89 if (sctx
->vs_blit_pos_layered
)
90 sctx
->b
.b
.delete_vs_state(&sctx
->b
.b
, sctx
->vs_blit_pos_layered
);
91 if (sctx
->vs_blit_color
)
92 sctx
->b
.b
.delete_vs_state(&sctx
->b
.b
, sctx
->vs_blit_color
);
93 if (sctx
->vs_blit_color_layered
)
94 sctx
->b
.b
.delete_vs_state(&sctx
->b
.b
, sctx
->vs_blit_color_layered
);
95 if (sctx
->vs_blit_texcoord
)
96 sctx
->b
.b
.delete_vs_state(&sctx
->b
.b
, sctx
->vs_blit_texcoord
);
99 util_blitter_destroy(sctx
->blitter
);
101 si_common_context_cleanup(&sctx
->b
);
103 LLVMDisposeTargetMachine(sctx
->tm
);
105 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
107 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
108 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
110 util_dynarray_fini(&sctx
->resident_tex_handles
);
111 util_dynarray_fini(&sctx
->resident_img_handles
);
112 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
113 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
114 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
118 static enum pipe_reset_status
119 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
121 struct si_context
*sctx
= (struct si_context
*)ctx
;
123 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
126 /* Apitrace profiling:
127 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
128 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
129 * and remember its number.
130 * 3) In Mesa, enable queries and performance counters around that draw
131 * call and print the results.
132 * 4) glretrace --benchmark --markers ..
134 static void si_emit_string_marker(struct pipe_context
*ctx
,
135 const char *string
, int len
)
137 struct si_context
*sctx
= (struct si_context
*)ctx
;
139 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
142 u_log_printf(sctx
->b
.log
, "\nString marker: %*s\n", len
, string
);
145 static LLVMTargetMachineRef
146 si_create_llvm_target_machine(struct si_screen
*sscreen
)
148 const char *triple
= "amdgcn--";
151 snprintf(features
, sizeof(features
),
152 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
153 sscreen
->b
.chip_class
>= GFX9
? ",+xnack" : ",-xnack",
154 sscreen
->llvm_has_working_vgpr_indexing
? "" : ",-promote-alloca",
155 sscreen
->b
.debug_flags
& DBG(SI_SCHED
) ? ",+si-scheduler" : "");
157 return LLVMCreateTargetMachine(ac_get_llvm_target(triple
), triple
,
158 si_get_llvm_processor_name(sscreen
->b
.family
),
160 LLVMCodeGenLevelDefault
,
162 LLVMCodeModelDefault
);
165 static void si_set_log_context(struct pipe_context
*ctx
,
166 struct u_log_context
*log
)
168 struct si_context
*sctx
= (struct si_context
*)ctx
;
172 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
175 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
178 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
179 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
180 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
186 if (flags
& PIPE_CONTEXT_DEBUG
)
187 sscreen
->record_llvm_ir
= true; /* racy but not critical */
189 sctx
->b
.b
.screen
= screen
; /* this must be set first */
190 sctx
->b
.b
.priv
= NULL
;
191 sctx
->b
.b
.destroy
= si_destroy_context
;
192 sctx
->b
.b
.emit_string_marker
= si_emit_string_marker
;
193 sctx
->b
.b
.set_log_context
= si_set_log_context
;
194 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
195 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
196 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
198 if (!si_common_context_init(&sctx
->b
, &sscreen
->b
, flags
))
201 if (sscreen
->b
.info
.drm_major
== 3)
202 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
204 si_init_blit_functions(sctx
);
205 si_init_compute_functions(sctx
);
206 si_init_cp_dma_functions(sctx
);
207 si_init_debug_functions(sctx
);
208 si_init_msaa_functions(sctx
);
209 si_init_streamout_functions(sctx
);
211 if (sscreen
->b
.info
.has_hw_decode
) {
212 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
213 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
215 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
216 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
219 sctx
->b
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
,
220 si_context_gfx_flush
, sctx
);
221 sctx
->b
.gfx
.flush
= si_context_gfx_flush
;
224 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
225 sizeof(*sctx
->border_color_table
));
226 if (!sctx
->border_color_table
)
229 sctx
->border_color_buffer
= (struct r600_resource
*)
230 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
231 SI_MAX_BORDER_COLORS
*
232 sizeof(*sctx
->border_color_table
));
233 if (!sctx
->border_color_buffer
)
236 sctx
->border_color_map
=
237 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
238 NULL
, PIPE_TRANSFER_WRITE
);
239 if (!sctx
->border_color_map
)
242 si_init_all_descriptors(sctx
);
243 si_init_state_functions(sctx
);
244 si_init_shader_functions(sctx
);
245 si_init_viewport_functions(sctx
);
246 si_init_ia_multi_vgt_param_table(sctx
);
248 if (sctx
->b
.chip_class
>= CIK
)
249 cik_init_sdma_functions(sctx
);
251 si_init_dma_functions(sctx
);
253 if (sscreen
->b
.debug_flags
& DBG(FORCE_DMA
))
254 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
256 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
257 if (sctx
->blitter
== NULL
)
259 sctx
->blitter
->draw_rectangle
= si_draw_rectangle
;
260 sctx
->blitter
->skip_viewport_restore
= true;
262 sctx
->sample_mask
.sample_mask
= 0xffff;
264 /* these must be last */
265 si_begin_new_cs(sctx
);
267 if (sctx
->b
.chip_class
>= GFX9
) {
268 sctx
->wait_mem_scratch
= (struct r600_resource
*)
269 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 4);
270 if (!sctx
->wait_mem_scratch
)
273 /* Initialize the memory. */
274 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
275 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
276 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
277 S_370_WR_CONFIRM(1) |
278 S_370_ENGINE_SEL(V_370_ME
));
279 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
);
280 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
>> 32);
281 radeon_emit(cs
, sctx
->wait_mem_number
);
284 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
285 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
286 if (sctx
->b
.chip_class
== CIK
) {
287 sctx
->null_const_buf
.buffer
=
288 si_aligned_buffer_create(screen
,
289 R600_RESOURCE_FLAG_UNMAPPABLE
,
290 PIPE_USAGE_DEFAULT
, 16,
291 sctx
->screen
->b
.info
.tcc_cache_line_size
);
292 if (!sctx
->null_const_buf
.buffer
)
294 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
296 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
297 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
298 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
299 &sctx
->null_const_buf
);
303 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
304 &sctx
->null_const_buf
);
305 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
306 &sctx
->null_const_buf
);
307 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
308 &sctx
->null_const_buf
);
309 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
310 &sctx
->null_const_buf
);
311 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
312 &sctx
->null_const_buf
);
314 /* Clear the NULL constant buffer, because loads should return zeros. */
315 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
316 sctx
->null_const_buf
.buffer
->width0
, 0,
317 R600_COHERENCY_SHADER
);
320 uint64_t max_threads_per_block
;
321 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
322 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
323 &max_threads_per_block
);
325 /* The maximum number of scratch waves. Scratch space isn't divided
326 * evenly between CUs. The number is only a function of the number of CUs.
327 * We can decrease the constant to decrease the scratch buffer size.
329 * sctx->scratch_waves must be >= the maximum posible size of
330 * 1 threadgroup, so that the hw doesn't hang from being unable
333 * The recommended value is 4 per CU at most. Higher numbers don't
334 * bring much benefit, but they still occupy chip resources (think
335 * async compute). I've seen ~2% performance difference between 4 and 32.
337 sctx
->scratch_waves
= MAX2(32 * sscreen
->b
.info
.num_good_compute_units
,
338 max_threads_per_block
/ 64);
340 sctx
->tm
= si_create_llvm_target_machine(sscreen
);
342 /* Bindless handles. */
343 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
344 _mesa_key_pointer_equal
);
345 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
346 _mesa_key_pointer_equal
);
348 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
349 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
350 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
351 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
352 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
356 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
357 si_destroy_context(&sctx
->b
.b
);
361 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
362 void *priv
, unsigned flags
)
364 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
365 struct pipe_context
*ctx
;
367 if (sscreen
->b
.debug_flags
& DBG(CHECK_VM
))
368 flags
|= PIPE_CONTEXT_DEBUG
;
370 ctx
= si_create_context(screen
, flags
);
372 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
375 /* Clover (compute-only) is unsupported.
377 * Since the threaded context creates shader states from the non-driver
378 * thread, asynchronous compilation is required for create_{shader}_-
379 * state not to use pipe_context. Debug contexts (ddebug) disable
380 * asynchronous compilation, so don't use the threaded context with
383 if (flags
& (PIPE_CONTEXT_COMPUTE_ONLY
| PIPE_CONTEXT_DEBUG
))
386 /* When shaders are logged to stderr, asynchronous compilation is
388 if (sscreen
->b
.debug_flags
& DBG_ALL_SHADERS
)
391 return threaded_context_create(ctx
, &sscreen
->b
.pool_transfers
,
392 si_replace_buffer_storage
,
393 &((struct si_context
*)ctx
)->b
.tc
);
399 static bool si_have_tgsi_compute(struct si_screen
*sscreen
)
401 /* Old kernels disallowed some register writes for SI
402 * that are used for indirect dispatches. */
403 return (sscreen
->b
.chip_class
>= CIK
||
404 sscreen
->b
.info
.drm_major
== 3 ||
405 (sscreen
->b
.info
.drm_major
== 2 &&
406 sscreen
->b
.info
.drm_minor
>= 45));
409 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
411 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
414 /* Supported features (boolean caps). */
415 case PIPE_CAP_ACCELERATED
:
416 case PIPE_CAP_TWO_SIDED_STENCIL
:
417 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
418 case PIPE_CAP_ANISOTROPIC_FILTER
:
419 case PIPE_CAP_POINT_SPRITE
:
420 case PIPE_CAP_OCCLUSION_QUERY
:
421 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
422 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
423 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
424 case PIPE_CAP_TEXTURE_SWIZZLE
:
425 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
426 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
427 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
428 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
429 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
430 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
431 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
433 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
434 case PIPE_CAP_PRIMITIVE_RESTART
:
435 case PIPE_CAP_CONDITIONAL_RENDER
:
436 case PIPE_CAP_TEXTURE_BARRIER
:
437 case PIPE_CAP_INDEP_BLEND_ENABLE
:
438 case PIPE_CAP_INDEP_BLEND_FUNC
:
439 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
440 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
441 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
442 case PIPE_CAP_START_INSTANCE
:
443 case PIPE_CAP_NPOT_TEXTURES
:
444 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
445 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
446 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
447 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
448 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
449 case PIPE_CAP_TGSI_INSTANCEID
:
450 case PIPE_CAP_COMPUTE
:
451 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
452 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
453 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
454 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
455 case PIPE_CAP_CUBE_MAP_ARRAY
:
456 case PIPE_CAP_SAMPLE_SHADING
:
457 case PIPE_CAP_DRAW_INDIRECT
:
458 case PIPE_CAP_CLIP_HALFZ
:
459 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
460 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
461 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
462 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
463 case PIPE_CAP_TGSI_TEXCOORD
:
464 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
465 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
466 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
467 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
468 case PIPE_CAP_SHAREABLE_SHADERS
:
469 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
470 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
471 case PIPE_CAP_TEXTURE_QUERY_LOD
:
472 case PIPE_CAP_TEXTURE_GATHER_SM5
:
473 case PIPE_CAP_TGSI_TXQS
:
474 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
475 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
476 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
477 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
478 case PIPE_CAP_INVALIDATE_BUFFER
:
479 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
480 case PIPE_CAP_QUERY_MEMORY_INFO
:
481 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
482 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
483 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
484 case PIPE_CAP_GENERATE_MIPMAP
:
485 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
486 case PIPE_CAP_STRING_MARKER
:
487 case PIPE_CAP_CLEAR_TEXTURE
:
488 case PIPE_CAP_CULL_DISTANCE
:
489 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
490 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
491 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
492 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
493 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
494 case PIPE_CAP_DOUBLES
:
495 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
496 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
497 case PIPE_CAP_BINDLESS_TEXTURE
:
498 case PIPE_CAP_QUERY_TIMESTAMP
:
499 case PIPE_CAP_QUERY_TIME_ELAPSED
:
500 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
501 case PIPE_CAP_QUERY_SO_OVERFLOW
:
502 case PIPE_CAP_MEMOBJ
:
503 case PIPE_CAP_LOAD_CONSTBUF
:
505 case PIPE_CAP_INT64_DIVMOD
:
506 case PIPE_CAP_TGSI_CLOCK
:
507 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
508 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
509 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
510 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
513 case PIPE_CAP_TGSI_VOTE
:
514 return HAVE_LLVM
>= 0x0400;
516 case PIPE_CAP_TGSI_BALLOT
:
517 return HAVE_LLVM
>= 0x0500;
519 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
520 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
522 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
523 return (sscreen
->b
.info
.drm_major
== 2 &&
524 sscreen
->b
.info
.drm_minor
>= 43) ||
525 sscreen
->b
.info
.drm_major
== 3;
527 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
528 /* 2D tiling on CIK is supported since DRM 2.35.0 */
529 return sscreen
->b
.chip_class
< CIK
||
530 (sscreen
->b
.info
.drm_major
== 2 &&
531 sscreen
->b
.info
.drm_minor
>= 35) ||
532 sscreen
->b
.info
.drm_major
== 3;
534 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
535 return R600_MAP_BUFFER_ALIGNMENT
;
537 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
538 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
539 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
540 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
541 case PIPE_CAP_MAX_VERTEX_STREAMS
:
542 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
545 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
546 if (sscreen
->b
.debug_flags
& DBG(NIR
))
547 return 140; /* no geometry and tessellation shaders yet */
548 if (si_have_tgsi_compute(sscreen
))
552 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
553 return MIN2(sscreen
->b
.info
.max_alloc_size
, INT_MAX
);
555 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
556 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
557 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
558 /* SI doesn't support unaligned loads.
559 * CIK needs DRM 2.50.0 on radeon. */
560 return sscreen
->b
.chip_class
== SI
||
561 (sscreen
->b
.info
.drm_major
== 2 &&
562 sscreen
->b
.info
.drm_minor
< 50);
564 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
565 /* TODO: GFX9 hangs. */
566 if (sscreen
->b
.chip_class
>= GFX9
)
568 /* Disable on SI due to VM faults in CP DMA. Enable once these
569 * faults are mitigated in software.
571 if (sscreen
->b
.chip_class
>= CIK
&&
572 sscreen
->b
.info
.drm_major
== 3 &&
573 sscreen
->b
.info
.drm_minor
>= 13)
574 return RADEON_SPARSE_PAGE_SIZE
;
577 /* Unsupported features. */
578 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
579 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
580 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
581 case PIPE_CAP_USER_VERTEX_BUFFERS
:
582 case PIPE_CAP_FAKE_SW_MSAA
:
583 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
584 case PIPE_CAP_VERTEXID_NOBASE
:
585 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
586 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
587 case PIPE_CAP_TGSI_FS_FBFETCH
:
588 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
590 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
591 case PIPE_CAP_POST_DEPTH_COVERAGE
:
592 case PIPE_CAP_TILE_RASTER_ORDER
:
593 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
596 case PIPE_CAP_NATIVE_FENCE_FD
:
597 return sscreen
->b
.info
.has_sync_file
;
599 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
600 return si_have_tgsi_compute(sscreen
);
602 case PIPE_CAP_DRAW_PARAMETERS
:
603 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
604 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
605 return sscreen
->has_draw_indirect_multi
;
607 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
610 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
611 return sscreen
->b
.chip_class
<= VI
?
612 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
615 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
616 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
619 /* Geometry shader output. */
620 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
622 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
625 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
629 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
630 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
631 return 15; /* 16384 */
632 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
633 /* textures support 8192, but layered rendering supports 2048 */
635 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
636 /* textures support 8192, but layered rendering supports 2048 */
639 /* Viewports and render targets. */
640 case PIPE_CAP_MAX_VIEWPORTS
:
641 return SI_MAX_VIEWPORTS
;
642 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
643 case PIPE_CAP_MAX_RENDER_TARGETS
:
646 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
647 case PIPE_CAP_MIN_TEXEL_OFFSET
:
650 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
651 case PIPE_CAP_MAX_TEXEL_OFFSET
:
654 case PIPE_CAP_ENDIANNESS
:
655 return PIPE_ENDIAN_LITTLE
;
657 case PIPE_CAP_VENDOR_ID
:
658 return ATI_VENDOR_ID
;
659 case PIPE_CAP_DEVICE_ID
:
660 return sscreen
->b
.info
.pci_id
;
661 case PIPE_CAP_VIDEO_MEMORY
:
662 return sscreen
->b
.info
.vram_size
>> 20;
663 case PIPE_CAP_PCI_GROUP
:
664 return sscreen
->b
.info
.pci_domain
;
665 case PIPE_CAP_PCI_BUS
:
666 return sscreen
->b
.info
.pci_bus
;
667 case PIPE_CAP_PCI_DEVICE
:
668 return sscreen
->b
.info
.pci_dev
;
669 case PIPE_CAP_PCI_FUNCTION
:
670 return sscreen
->b
.info
.pci_func
;
675 static int si_get_shader_param(struct pipe_screen
* pscreen
,
676 enum pipe_shader_type shader
,
677 enum pipe_shader_cap param
)
679 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
683 case PIPE_SHADER_FRAGMENT
:
684 case PIPE_SHADER_VERTEX
:
685 case PIPE_SHADER_GEOMETRY
:
686 case PIPE_SHADER_TESS_CTRL
:
687 case PIPE_SHADER_TESS_EVAL
:
689 case PIPE_SHADER_COMPUTE
:
691 case PIPE_SHADER_CAP_PREFERRED_IR
:
692 return PIPE_SHADER_IR_NATIVE
;
694 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
695 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
697 if (si_have_tgsi_compute(sscreen
))
698 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
703 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
704 uint64_t max_const_buffer_size
;
705 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
706 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
707 &max_const_buffer_size
);
708 return MIN2(max_const_buffer_size
, INT_MAX
);
711 /* If compute shaders don't require a special value
712 * for this cap, we can return the same value we
713 * do for other shader types. */
723 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
724 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
725 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
726 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
727 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
729 case PIPE_SHADER_CAP_MAX_INPUTS
:
730 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
731 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
732 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
733 case PIPE_SHADER_CAP_MAX_TEMPS
:
734 return 256; /* Max native temporaries. */
735 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
736 return 4096 * sizeof(float[4]); /* actually only memory limits this */
737 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
738 return SI_NUM_CONST_BUFFERS
;
739 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
740 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
741 return SI_NUM_SAMPLERS
;
742 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
743 return SI_NUM_SHADER_BUFFERS
;
744 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
745 return SI_NUM_IMAGES
;
746 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
748 case PIPE_SHADER_CAP_PREFERRED_IR
:
749 if (sscreen
->b
.debug_flags
& DBG(NIR
) &&
750 (shader
== PIPE_SHADER_VERTEX
||
751 shader
== PIPE_SHADER_FRAGMENT
))
752 return PIPE_SHADER_IR_NIR
;
753 return PIPE_SHADER_IR_TGSI
;
754 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
757 /* Supported boolean features. */
758 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
759 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
760 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
761 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
762 case PIPE_SHADER_CAP_INTEGERS
:
763 case PIPE_SHADER_CAP_INT64_ATOMICS
:
764 case PIPE_SHADER_CAP_FP16
:
765 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
766 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
767 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
768 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
769 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
770 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
773 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
774 /* TODO: Indirect indexing of GS inputs is unimplemented. */
775 return shader
!= PIPE_SHADER_GEOMETRY
&&
776 (sscreen
->llvm_has_working_vgpr_indexing
||
777 /* TCS and TES load inputs directly from LDS or
778 * offchip memory, so indirect indexing is trivial. */
779 shader
== PIPE_SHADER_TESS_CTRL
||
780 shader
== PIPE_SHADER_TESS_EVAL
);
782 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
783 return sscreen
->llvm_has_working_vgpr_indexing
||
784 /* TCS stores outputs directly to memory. */
785 shader
== PIPE_SHADER_TESS_CTRL
;
787 /* Unsupported boolean features. */
788 case PIPE_SHADER_CAP_SUBROUTINES
:
789 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
795 static const struct nir_shader_compiler_options nir_options
= {
796 .vertex_id_zero_based
= true,
798 .lower_flrp32
= true,
803 .lower_pack_snorm_2x16
= true,
804 .lower_pack_snorm_4x8
= true,
805 .lower_pack_unorm_2x16
= true,
806 .lower_pack_unorm_4x8
= true,
807 .lower_unpack_snorm_2x16
= true,
808 .lower_unpack_snorm_4x8
= true,
809 .lower_unpack_unorm_2x16
= true,
810 .lower_unpack_unorm_4x8
= true,
811 .lower_extract_byte
= true,
812 .lower_extract_word
= true,
813 .max_unroll_iterations
= 32,
814 .native_integers
= true,
818 si_get_compiler_options(struct pipe_screen
*screen
,
819 enum pipe_shader_ir ir
,
820 enum pipe_shader_type shader
)
822 assert(ir
== PIPE_SHADER_IR_NIR
);
826 static void si_destroy_screen(struct pipe_screen
* pscreen
)
828 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
829 struct si_shader_part
*parts
[] = {
831 sscreen
->tcs_epilogs
,
838 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
841 util_queue_destroy(&sscreen
->shader_compiler_queue
);
842 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
844 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm
); i
++)
846 LLVMDisposeTargetMachine(sscreen
->tm
[i
]);
848 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm_low_priority
); i
++)
849 if (sscreen
->tm_low_priority
[i
])
850 LLVMDisposeTargetMachine(sscreen
->tm_low_priority
[i
]);
852 /* Free shader parts. */
853 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
855 struct si_shader_part
*part
= parts
[i
];
857 parts
[i
] = part
->next
;
858 si_radeon_shader_binary_clean(&part
->binary
);
862 mtx_destroy(&sscreen
->shader_parts_mutex
);
863 si_destroy_shader_cache(sscreen
);
864 si_destroy_common_screen(&sscreen
->b
);
867 static bool si_init_gs_info(struct si_screen
*sscreen
)
869 /* gs_table_depth is not used by GFX9 */
870 if (sscreen
->b
.chip_class
>= GFX9
)
873 switch (sscreen
->b
.family
) {
882 sscreen
->gs_table_depth
= 16;
894 sscreen
->gs_table_depth
= 32;
901 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
903 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
909 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
910 if (!strcmp(family
, si_get_llvm_processor_name(i
))) {
911 /* Override family and chip_class. */
912 sscreen
->b
.family
= sscreen
->b
.info
.family
= i
;
914 if (i
>= CHIP_VEGA10
)
915 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= GFX9
;
916 else if (i
>= CHIP_TONGA
)
917 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= VI
;
918 else if (i
>= CHIP_BONAIRE
)
919 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= CIK
;
921 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= SI
;
923 /* Don't submit any IBs. */
924 setenv("RADEON_NOOP", "1", 1);
929 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
933 static void si_test_vmfault(struct si_screen
*sscreen
)
935 struct pipe_context
*ctx
= sscreen
->b
.aux_context
;
936 struct si_context
*sctx
= (struct si_context
*)ctx
;
937 struct pipe_resource
*buf
=
938 pipe_buffer_create(&sscreen
->b
.b
, 0, PIPE_USAGE_DEFAULT
, 64);
941 puts("Buffer allocation failed.");
945 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
947 if (sscreen
->b
.debug_flags
& DBG(TEST_VMFAULT_CP
)) {
948 si_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0);
949 ctx
->flush(ctx
, NULL
, 0);
950 puts("VM fault test: CP - done.");
952 if (sscreen
->b
.debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
953 sctx
->b
.dma_clear_buffer(ctx
, buf
, 0, 4, 0);
954 ctx
->flush(ctx
, NULL
, 0);
955 puts("VM fault test: SDMA - done.");
957 if (sscreen
->b
.debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
958 util_test_constant_buffer(ctx
, buf
);
959 puts("VM fault test: Shader - done.");
964 static void radeonsi_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
966 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
969 static void radeonsi_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
971 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
973 ac_compute_device_uuid(&rscreen
->info
, uuid
, PIPE_UUID_SIZE
);
976 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
,
977 const struct pipe_screen_config
*config
)
979 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
980 unsigned num_threads
, num_compiler_threads
, num_compiler_threads_lowprio
, i
;
986 /* Set functions first. */
987 sscreen
->b
.b
.context_create
= si_pipe_create_context
;
988 sscreen
->b
.b
.destroy
= si_destroy_screen
;
989 sscreen
->b
.b
.get_param
= si_get_param
;
990 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
991 sscreen
->b
.b
.get_compiler_options
= si_get_compiler_options
;
992 sscreen
->b
.b
.get_device_uuid
= radeonsi_get_device_uuid
;
993 sscreen
->b
.b
.get_driver_uuid
= radeonsi_get_driver_uuid
;
994 sscreen
->b
.b
.resource_create
= si_resource_create_common
;
996 si_init_screen_state_functions(sscreen
);
998 /* Set these flags in debug_flags early, so that the shader cache takes
1001 if (driQueryOptionb(config
->options
,
1002 "glsl_correct_derivatives_after_discard"))
1003 sscreen
->b
.debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
1004 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
1005 sscreen
->b
.debug_flags
|= DBG(SI_SCHED
);
1007 if (!si_common_screen_init(&sscreen
->b
, ws
) ||
1008 !si_init_gs_info(sscreen
) ||
1009 !si_init_shader_cache(sscreen
)) {
1014 /* Only enable as many threads as we have target machines, but at most
1015 * the number of CPUs - 1 if there is more than one.
1017 num_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
1018 num_threads
= MAX2(1, num_threads
- 1);
1019 num_compiler_threads
= MIN2(num_threads
, ARRAY_SIZE(sscreen
->tm
));
1020 num_compiler_threads_lowprio
=
1021 MIN2(num_threads
, ARRAY_SIZE(sscreen
->tm_low_priority
));
1023 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "si_shader",
1024 32, num_compiler_threads
,
1025 UTIL_QUEUE_INIT_RESIZE_IF_FULL
)) {
1026 si_destroy_shader_cache(sscreen
);
1031 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
1033 32, num_compiler_threads_lowprio
,
1034 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1035 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
1036 si_destroy_shader_cache(sscreen
);
1041 si_handle_env_var_force_family(sscreen
);
1043 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1044 si_init_perfcounters(sscreen
);
1046 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1047 * around by setting 4K granularity.
1049 sscreen
->tess_offchip_block_dw_size
=
1050 sscreen
->b
.family
== CHIP_HAWAII
? 4096 : 8192;
1052 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1054 sscreen
->has_clear_state
= sscreen
->b
.chip_class
>= CIK
;
1056 sscreen
->has_distributed_tess
=
1057 sscreen
->b
.chip_class
>= VI
&&
1058 sscreen
->b
.info
.max_se
>= 2;
1060 sscreen
->has_draw_indirect_multi
=
1061 (sscreen
->b
.family
>= CHIP_POLARIS10
) ||
1062 (sscreen
->b
.chip_class
== VI
&&
1063 sscreen
->b
.info
.pfp_fw_version
>= 121 &&
1064 sscreen
->b
.info
.me_fw_version
>= 87) ||
1065 (sscreen
->b
.chip_class
== CIK
&&
1066 sscreen
->b
.info
.pfp_fw_version
>= 211 &&
1067 sscreen
->b
.info
.me_fw_version
>= 173) ||
1068 (sscreen
->b
.chip_class
== SI
&&
1069 sscreen
->b
.info
.pfp_fw_version
>= 79 &&
1070 sscreen
->b
.info
.me_fw_version
>= 142);
1072 sscreen
->has_out_of_order_rast
= sscreen
->b
.chip_class
>= VI
&&
1073 sscreen
->b
.info
.max_se
>= 2 &&
1074 !(sscreen
->b
.debug_flags
& DBG(NO_OUT_OF_ORDER
));
1075 sscreen
->assume_no_z_fights
=
1076 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
1077 sscreen
->commutative_blend_add
=
1078 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
1079 sscreen
->clear_db_cache_before_clear
=
1080 driQueryOptionb(config
->options
, "radeonsi_clear_db_cache_before_clear");
1081 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->b
.family
>= CHIP_POLARIS10
&&
1082 sscreen
->b
.family
<= CHIP_POLARIS12
) ||
1083 sscreen
->b
.family
== CHIP_VEGA10
||
1084 sscreen
->b
.family
== CHIP_RAVEN
;
1086 if (sscreen
->b
.debug_flags
& DBG(DPBB
)) {
1087 sscreen
->dpbb_allowed
= true;
1089 /* Only enable primitive binning on Raven by default. */
1090 sscreen
->dpbb_allowed
= sscreen
->b
.family
== CHIP_RAVEN
&&
1091 !(sscreen
->b
.debug_flags
& DBG(NO_DPBB
));
1094 if (sscreen
->b
.debug_flags
& DBG(DFSM
)) {
1095 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
;
1097 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
&&
1098 !(sscreen
->b
.debug_flags
& DBG(NO_DFSM
));
1101 /* While it would be nice not to have this flag, we are constrained
1102 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1105 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->b
.chip_class
<= VI
;
1107 sscreen
->b
.has_cp_dma
= true;
1108 sscreen
->b
.has_streamout
= true;
1110 /* Some chips have RB+ registers, but don't support RB+. Those must
1111 * always disable it.
1113 if (sscreen
->b
.family
== CHIP_STONEY
||
1114 sscreen
->b
.chip_class
>= GFX9
) {
1115 sscreen
->b
.has_rbplus
= true;
1117 sscreen
->b
.rbplus_allowed
=
1118 !(sscreen
->b
.debug_flags
& DBG(NO_RB_PLUS
)) &&
1119 (sscreen
->b
.family
== CHIP_STONEY
||
1120 sscreen
->b
.family
== CHIP_RAVEN
);
1123 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1124 sscreen
->use_monolithic_shaders
=
1125 (sscreen
->b
.debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1127 sscreen
->b
.barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
1128 SI_CONTEXT_INV_VMEM_L1
;
1129 if (sscreen
->b
.chip_class
<= VI
) {
1130 sscreen
->b
.barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_GLOBAL_L2
;
1131 sscreen
->b
.barrier_flags
.L2_to_cp
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1134 sscreen
->b
.barrier_flags
.compute_to_L2
= SI_CONTEXT_CS_PARTIAL_FLUSH
;
1136 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1137 sscreen
->b
.debug_flags
|= DBG_ALL_SHADERS
;
1139 for (i
= 0; i
< num_compiler_threads
; i
++)
1140 sscreen
->tm
[i
] = si_create_llvm_target_machine(sscreen
);
1141 for (i
= 0; i
< num_compiler_threads_lowprio
; i
++)
1142 sscreen
->tm_low_priority
[i
] = si_create_llvm_target_machine(sscreen
);
1144 /* Create the auxiliary context. This must be done last. */
1145 sscreen
->b
.aux_context
= si_create_context(&sscreen
->b
.b
, 0);
1147 if (sscreen
->b
.debug_flags
& DBG(TEST_DMA
))
1148 si_test_dma(&sscreen
->b
);
1150 if (sscreen
->b
.debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1151 DBG(TEST_VMFAULT_SDMA
) |
1152 DBG(TEST_VMFAULT_SHADER
)))
1153 si_test_vmfault(sscreen
);
1155 return &sscreen
->b
.b
;