2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
28 #include "radeon/radeon_llvm_emit.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/u_memory.h"
31 #include "vl/vl_decoder.h"
36 static void si_destroy_context(struct pipe_context
*context
)
38 struct si_context
*sctx
= (struct si_context
*)context
;
41 si_release_all_descriptors(sctx
);
43 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
44 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
45 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
46 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
47 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
48 free(sctx
->border_color_table
);
49 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
50 sctx
->b
.ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
52 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
53 for (i
= 0; i
< Elements(sctx
->vgt_shader_config
); i
++)
54 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
56 if (sctx
->pstipple_sampler_state
)
57 sctx
->b
.b
.delete_sampler_state(&sctx
->b
.b
, sctx
->pstipple_sampler_state
);
58 if (sctx
->fixed_func_tcs_shader
.cso
)
59 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
.cso
);
60 if (sctx
->custom_dsa_flush
)
61 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
62 if (sctx
->custom_blend_resolve
)
63 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
64 if (sctx
->custom_blend_decompress
)
65 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
66 if (sctx
->custom_blend_fastclear
)
67 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fastclear
);
68 util_unreference_framebuffer_state(&sctx
->framebuffer
.state
);
71 util_blitter_destroy(sctx
->blitter
);
73 r600_common_context_cleanup(&sctx
->b
);
75 #if HAVE_LLVM >= 0x0306
76 LLVMDisposeTargetMachine(sctx
->tm
);
79 r600_resource_reference(&sctx
->trace_buf
, NULL
);
80 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
82 if (sctx
->last_bo_list
) {
83 for (i
= 0; i
< sctx
->last_bo_count
; i
++)
84 pb_reference(&sctx
->last_bo_list
[i
].buf
, NULL
);
85 free(sctx
->last_bo_list
);
90 static enum pipe_reset_status
91 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
93 struct si_context
*sctx
= (struct si_context
*)ctx
;
95 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
98 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
99 void *priv
, unsigned flags
)
101 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
102 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
103 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
104 LLVMTargetRef r600_target
;
105 #if HAVE_LLVM >= 0x0306
106 const char *triple
= "amdgcn--";
113 if (sscreen
->b
.debug_flags
& DBG_CHECK_VM
)
114 flags
|= PIPE_CONTEXT_DEBUG
;
116 sctx
->b
.b
.screen
= screen
; /* this must be set first */
117 sctx
->b
.b
.priv
= priv
;
118 sctx
->b
.b
.destroy
= si_destroy_context
;
119 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
120 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
121 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
123 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
))
126 if (sscreen
->b
.info
.drm_major
== 3)
127 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
129 si_init_blit_functions(sctx
);
130 si_init_compute_functions(sctx
);
131 si_init_cp_dma_functions(sctx
);
132 si_init_debug_functions(sctx
);
134 if (sscreen
->b
.info
.has_uvd
) {
135 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
136 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
138 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
139 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
142 sctx
->b
.rings
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
, si_context_gfx_flush
,
143 sctx
, sscreen
->b
.trace_bo
?
144 sscreen
->b
.trace_bo
->cs_buf
: NULL
);
145 sctx
->b
.rings
.gfx
.flush
= si_context_gfx_flush
;
148 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
149 sizeof(*sctx
->border_color_table
));
150 if (!sctx
->border_color_table
)
153 sctx
->border_color_buffer
= (struct r600_resource
*)
154 pipe_buffer_create(screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_DEFAULT
,
155 SI_MAX_BORDER_COLORS
*
156 sizeof(*sctx
->border_color_table
));
157 if (!sctx
->border_color_buffer
)
160 sctx
->border_color_map
=
161 ws
->buffer_map(sctx
->border_color_buffer
->cs_buf
,
162 NULL
, PIPE_TRANSFER_WRITE
);
163 if (!sctx
->border_color_map
)
166 si_init_all_descriptors(sctx
);
167 si_init_state_functions(sctx
);
168 si_init_shader_functions(sctx
);
170 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
171 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
173 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
174 if (sctx
->blitter
== NULL
)
176 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
178 sctx
->sample_mask
.sample_mask
= 0xffff;
180 /* these must be last */
181 si_begin_new_cs(sctx
);
182 r600_query_init_backend_mask(&sctx
->b
); /* this emits commands and must be last */
184 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
185 * with a NULL buffer). We need to use a dummy buffer instead. */
186 if (sctx
->b
.chip_class
== CIK
) {
187 sctx
->null_const_buf
.buffer
= pipe_buffer_create(screen
, PIPE_BIND_CONSTANT_BUFFER
,
188 PIPE_USAGE_DEFAULT
, 16);
189 if (!sctx
->null_const_buf
.buffer
)
191 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
193 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
194 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
195 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
196 &sctx
->null_const_buf
);
200 /* Clear the NULL constant buffer, because loads should return zeros. */
201 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
202 sctx
->null_const_buf
.buffer
->width0
, 0, false);
205 /* XXX: This is the maximum value allowed. I'm not sure how to compute
206 * this for non-cs shaders. Using the wrong value here can result in
207 * GPU lockups, but the maximum value seems to always work.
209 sctx
->scratch_waves
= 32 * sscreen
->b
.info
.max_compute_units
;
211 #if HAVE_LLVM >= 0x0306
212 /* Initialize LLVM TargetMachine */
213 r600_target
= radeon_llvm_get_r600_target(triple
);
214 sctx
->tm
= LLVMCreateTargetMachine(r600_target
, triple
,
215 r600_get_llvm_processor_name(sscreen
->b
.family
),
216 "+DumpCode,+vgpr-spilling",
217 LLVMCodeGenLevelDefault
,
219 LLVMCodeModelDefault
);
224 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
225 si_destroy_context(&sctx
->b
.b
);
233 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
235 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
238 /* Supported features (boolean caps). */
239 case PIPE_CAP_TWO_SIDED_STENCIL
:
240 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
241 case PIPE_CAP_ANISOTROPIC_FILTER
:
242 case PIPE_CAP_POINT_SPRITE
:
243 case PIPE_CAP_OCCLUSION_QUERY
:
244 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
245 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
246 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
247 case PIPE_CAP_TEXTURE_SWIZZLE
:
248 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
249 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
250 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
251 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
252 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
253 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
254 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
256 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
257 case PIPE_CAP_PRIMITIVE_RESTART
:
258 case PIPE_CAP_CONDITIONAL_RENDER
:
259 case PIPE_CAP_TEXTURE_BARRIER
:
260 case PIPE_CAP_INDEP_BLEND_ENABLE
:
261 case PIPE_CAP_INDEP_BLEND_FUNC
:
262 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
263 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
264 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
265 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
266 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
267 case PIPE_CAP_USER_INDEX_BUFFERS
:
268 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
269 case PIPE_CAP_START_INSTANCE
:
270 case PIPE_CAP_NPOT_TEXTURES
:
271 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
272 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
273 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
274 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
275 case PIPE_CAP_TGSI_INSTANCEID
:
276 case PIPE_CAP_COMPUTE
:
277 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
278 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
279 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
280 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
281 case PIPE_CAP_CUBE_MAP_ARRAY
:
282 case PIPE_CAP_SAMPLE_SHADING
:
283 case PIPE_CAP_DRAW_INDIRECT
:
284 case PIPE_CAP_CLIP_HALFZ
:
285 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
286 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
287 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
288 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
289 case PIPE_CAP_TGSI_TEXCOORD
:
290 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
291 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
292 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
293 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
294 case PIPE_CAP_SHAREABLE_SHADERS
:
295 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
296 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
297 case PIPE_CAP_TEXTURE_QUERY_LOD
:
298 case PIPE_CAP_TEXTURE_GATHER_SM5
:
299 case PIPE_CAP_TGSI_TXQS
:
300 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
301 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
304 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
305 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
307 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
308 return (sscreen
->b
.info
.drm_major
== 2 &&
309 sscreen
->b
.info
.drm_minor
>= 43) ||
310 sscreen
->b
.info
.drm_major
== 3;
312 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
313 /* 2D tiling on CIK is supported since DRM 2.35.0 */
314 return sscreen
->b
.chip_class
< CIK
||
315 (sscreen
->b
.info
.drm_major
== 2 &&
316 sscreen
->b
.info
.drm_minor
>= 35) ||
317 sscreen
->b
.info
.drm_major
== 3;
319 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
320 return R600_MAP_BUFFER_ALIGNMENT
;
322 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
323 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
324 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
327 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
328 return HAVE_LLVM
>= 0x0307 ? 410 : 330;
330 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
331 return MIN2(sscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
333 /* Unsupported features. */
334 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
335 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
336 case PIPE_CAP_USER_VERTEX_BUFFERS
:
337 case PIPE_CAP_FAKE_SW_MSAA
:
338 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
339 case PIPE_CAP_VERTEXID_NOBASE
:
342 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
345 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
346 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
349 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
350 return sscreen
->b
.has_streamout
? 4 : 0;
351 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
352 return sscreen
->b
.has_streamout
? 1 : 0;
353 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
354 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
355 return sscreen
->b
.has_streamout
? 32*4 : 0;
357 /* Geometry shader output. */
358 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
360 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
362 case PIPE_CAP_MAX_VERTEX_STREAMS
:
365 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
369 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
370 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
371 return 15; /* 16384 */
372 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
373 /* textures support 8192, but layered rendering supports 2048 */
375 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
376 /* textures support 8192, but layered rendering supports 2048 */
379 /* Render targets. */
380 case PIPE_CAP_MAX_RENDER_TARGETS
:
383 case PIPE_CAP_MAX_VIEWPORTS
:
384 return SI_MAX_VIEWPORTS
;
386 /* Timer queries, present when the clock frequency is non zero. */
387 case PIPE_CAP_QUERY_TIMESTAMP
:
388 case PIPE_CAP_QUERY_TIME_ELAPSED
:
389 return sscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
391 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
392 case PIPE_CAP_MIN_TEXEL_OFFSET
:
395 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
396 case PIPE_CAP_MAX_TEXEL_OFFSET
:
399 case PIPE_CAP_ENDIANNESS
:
400 return PIPE_ENDIAN_LITTLE
;
402 case PIPE_CAP_VENDOR_ID
:
404 case PIPE_CAP_DEVICE_ID
:
405 return sscreen
->b
.info
.pci_id
;
406 case PIPE_CAP_ACCELERATED
:
408 case PIPE_CAP_VIDEO_MEMORY
:
409 return sscreen
->b
.info
.vram_size
>> 20;
416 static int si_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
420 case PIPE_SHADER_FRAGMENT
:
421 case PIPE_SHADER_VERTEX
:
422 case PIPE_SHADER_GEOMETRY
:
424 case PIPE_SHADER_TESS_CTRL
:
425 case PIPE_SHADER_TESS_EVAL
:
426 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
427 if (HAVE_LLVM
< 0x0306 ||
428 (HAVE_LLVM
== 0x0306 && MESA_LLVM_VERSION_PATCH
< 2))
431 case PIPE_SHADER_COMPUTE
:
433 case PIPE_SHADER_CAP_PREFERRED_IR
:
434 #if HAVE_LLVM < 0x0306
435 return PIPE_SHADER_IR_LLVM
;
437 return PIPE_SHADER_IR_NATIVE
;
439 case PIPE_SHADER_CAP_DOUBLES
:
440 return HAVE_LLVM
>= 0x0307;
442 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
443 uint64_t max_const_buffer_size
;
444 pscreen
->get_compute_param(pscreen
,
445 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
446 &max_const_buffer_size
);
447 return max_const_buffer_size
;
450 /* If compute shaders don't require a special value
451 * for this cap, we can return the same value we
452 * do for other shader types. */
461 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
462 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
463 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
464 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
466 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
468 case PIPE_SHADER_CAP_MAX_INPUTS
:
469 return shader
== PIPE_SHADER_VERTEX
? SI_NUM_VERTEX_BUFFERS
: 32;
470 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
471 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
472 case PIPE_SHADER_CAP_MAX_TEMPS
:
473 return 256; /* Max native temporaries. */
474 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
475 return 4096 * sizeof(float[4]); /* actually only memory limits this */
476 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
477 return SI_NUM_USER_CONST_BUFFERS
;
478 case PIPE_SHADER_CAP_MAX_PREDS
:
479 return 0; /* FIXME */
480 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
482 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
484 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
485 /* Indirection of geometry shader input dimension is not
488 return shader
!= PIPE_SHADER_GEOMETRY
;
489 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
490 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
491 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
493 case PIPE_SHADER_CAP_INTEGERS
:
495 case PIPE_SHADER_CAP_SUBROUTINES
:
497 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
498 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
500 case PIPE_SHADER_CAP_PREFERRED_IR
:
501 return PIPE_SHADER_IR_TGSI
;
502 case PIPE_SHADER_CAP_DOUBLES
:
503 return HAVE_LLVM
>= 0x0307;
504 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
505 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
507 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
508 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
510 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
516 static void si_destroy_screen(struct pipe_screen
* pscreen
)
518 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
523 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
526 r600_destroy_common_screen(&sscreen
->b
);
529 #define SI_TILE_MODE_COLOR_2D_8BPP 14
531 /* Initialize pipe config. This is especially important for GPUs
532 * with 16 pipes and more where it's initialized incorrectly by
533 * the TILING_CONFIG ioctl. */
534 static bool si_initialize_pipe_config(struct si_screen
*sscreen
)
538 /* This is okay, because there can be no 2D tiling without
539 * the tile mode array, so we won't need the pipe config.
542 if (!sscreen
->b
.info
.si_tile_mode_array_valid
)
545 /* The same index is used for the 2D mode on CIK too. */
546 mode2d
= sscreen
->b
.info
.si_tile_mode_array
[SI_TILE_MODE_COLOR_2D_8BPP
];
548 switch (G_009910_PIPE_CONFIG(mode2d
)) {
549 case V_02803C_ADDR_SURF_P2
:
550 sscreen
->b
.tiling_info
.num_channels
= 2;
552 case V_02803C_X_ADDR_SURF_P4_8X16
:
553 case V_02803C_X_ADDR_SURF_P4_16X16
:
554 case V_02803C_X_ADDR_SURF_P4_16X32
:
555 case V_02803C_X_ADDR_SURF_P4_32X32
:
556 sscreen
->b
.tiling_info
.num_channels
= 4;
558 case V_02803C_X_ADDR_SURF_P8_16X16_8X16
:
559 case V_02803C_X_ADDR_SURF_P8_16X32_8X16
:
560 case V_02803C_X_ADDR_SURF_P8_32X32_8X16
:
561 case V_02803C_X_ADDR_SURF_P8_16X32_16X16
:
562 case V_02803C_X_ADDR_SURF_P8_32X32_16X16
:
563 case V_02803C_X_ADDR_SURF_P8_32X32_16X32
:
564 case V_02803C_X_ADDR_SURF_P8_32X64_32X32
:
565 sscreen
->b
.tiling_info
.num_channels
= 8;
567 case V_02803C_X_ADDR_SURF_P16_32X32_8X16
:
568 case V_02803C_X_ADDR_SURF_P16_32X32_16X16
:
569 sscreen
->b
.tiling_info
.num_channels
= 16;
573 fprintf(stderr
, "radeonsi: Unknown pipe config %i.\n",
574 G_009910_PIPE_CONFIG(mode2d
));
580 static bool si_init_gs_info(struct si_screen
*sscreen
)
582 switch (sscreen
->b
.family
) {
591 sscreen
->gs_table_depth
= 16;
600 sscreen
->gs_table_depth
= 32;
607 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
609 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
611 if (sscreen
== NULL
) {
615 /* Set functions first. */
616 sscreen
->b
.b
.context_create
= si_create_context
;
617 sscreen
->b
.b
.destroy
= si_destroy_screen
;
618 sscreen
->b
.b
.get_param
= si_get_param
;
619 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
620 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
621 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
623 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
624 !si_initialize_pipe_config(sscreen
) ||
625 !si_init_gs_info(sscreen
)) {
630 sscreen
->b
.has_cp_dma
= true;
631 sscreen
->b
.has_streamout
= true;
633 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE
))
634 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
636 /* Create the auxiliary context. This must be done last. */
637 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
, 0);
639 return &sscreen
->b
.b
;