src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26
  27 #include "radeon/radeon_uvd.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_flush_from_st(struct pipe_context *ctx,
  37                              struct pipe_fence_handle **fence,
  38                              unsigned flags)
  39 {
  40         struct si_context *sctx = (struct si_context *)ctx;
  41         unsigned rflags = 0;
  42
  43         if (flags & PIPE_FLUSH_END_OF_FRAME)
  44                 rflags |= RADEON_FLUSH_END_OF_FRAME;
  45
  46         if (sctx->b.rings.dma.cs) {
  47                 sctx->b.rings.dma.flush(sctx, rflags, NULL);
  48         }
  49         sctx->b.rings.gfx.flush(sctx, rflags, fence);
  50 }
  51
  52 static void si_destroy_context(struct pipe_context *context)
  53 {
  54         struct si_context *sctx = (struct si_context *)context;
  55
  56         si_release_all_descriptors(sctx);
  57
  58         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  59         r600_resource_reference(&sctx->border_color_table, NULL);
  60
  61         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  62         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  63         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  64
  65         if (sctx->dummy_pixel_shader) {
  66                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  67         }
  68         for (int i = 0; i < 8; i++) {
  69                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
  70                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
  71                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
  72         }
  73         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
  74         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  75         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  76         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  77         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  78
  79         util_blitter_destroy(sctx->blitter);
  80
  81         si_pm4_cleanup(sctx);
  82
  83         r600_common_context_cleanup(&sctx->b);
  84         FREE(sctx);
  85 }
  86
  87 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  88 {
  89         struct si_context *sctx = CALLOC_STRUCT(si_context);
  90         struct si_screen* sscreen = (struct si_screen *)screen;
  91         struct radeon_winsys *ws = sscreen->b.ws;
  92         int shader, i;
  93
  94         if (sctx == NULL)
  95                 return NULL;
  96
  97         sctx->b.b.screen = screen; /* this must be set first */
  98         sctx->b.b.priv = priv;
  99         sctx->b.b.destroy = si_destroy_context;
 100         sctx->b.b.flush = si_flush_from_st;
 101         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 102
 103         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 104                 goto fail;
 105
 106         si_init_blit_functions(sctx);
 107         si_init_compute_functions(sctx);
 108
 109         if (sscreen->b.info.has_uvd) {
 110                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 111                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 112         } else {
 113                 sctx->b.b.create_video_codec = vl_create_decoder;
 114                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 115         }
 116
 117         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
 118                                              sctx, NULL);
 119         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 120
 121         si_init_all_descriptors(sctx);
 122
 123         /* Initialize cache_flush. */
 124         sctx->cache_flush = si_atom_cache_flush;
 125         sctx->atoms.cache_flush = &sctx->cache_flush;
 126
 127         sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
 128         sctx->atoms.streamout_enable = &sctx->b.streamout.enable_atom;
 129
 130         switch (sctx->b.chip_class) {
 131         case SI:
 132         case CIK:
 133                 si_init_state_functions(sctx);
 134                 si_init_config(sctx);
 135                 break;
 136         default:
 137                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 138                 goto fail;
 139         }
 140
 141         sctx->blitter = util_blitter_create(&sctx->b.b);
 142         if (sctx->blitter == NULL)
 143                 goto fail;
 144
 145         sctx->dummy_pixel_shader =
 146                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 147                                                      TGSI_SEMANTIC_GENERIC,
 148                                                      TGSI_INTERPOLATE_CONSTANT);
 149         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 150
 151         /* these must be last */
 152         si_begin_new_cs(sctx);
 153         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 154
 155         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 156          * with a NULL buffer). We need to use a dummy buffer instead. */
 157         if (sctx->b.chip_class == CIK) {
 158                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 159                                                                  PIPE_USAGE_DEFAULT, 16);
 160                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 161
 162                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 163                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 164                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 165                                                               &sctx->null_const_buf);
 166                         }
 167                 }
 168
 169                 /* Clear the NULL constant buffer, because loads should return zeros. */
 170                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 171                                      sctx->null_const_buf.buffer->width0, 0);
 172         }
 173
 174         return &sctx->b.b;
 175 fail:
 176         si_destroy_context(&sctx->b.b);
 177         return NULL;
 178 }
 179
 180 /*
 181  * pipe_screen
 182  */
 183
 184 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 185 {
 186         struct si_screen *sscreen = (struct si_screen *)pscreen;
 187
 188         switch (param) {
 189         /* Supported features (boolean caps). */
 190         case PIPE_CAP_TWO_SIDED_STENCIL:
 191         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 192         case PIPE_CAP_ANISOTROPIC_FILTER:
 193         case PIPE_CAP_POINT_SPRITE:
 194         case PIPE_CAP_OCCLUSION_QUERY:
 195         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 196         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 197         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 198         case PIPE_CAP_TEXTURE_SWIZZLE:
 199         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 200         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 201         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 202         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 203         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 204         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 205         case PIPE_CAP_SM3:
 206         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 207         case PIPE_CAP_PRIMITIVE_RESTART:
 208         case PIPE_CAP_CONDITIONAL_RENDER:
 209         case PIPE_CAP_TEXTURE_BARRIER:
 210         case PIPE_CAP_INDEP_BLEND_ENABLE:
 211         case PIPE_CAP_INDEP_BLEND_FUNC:
 212         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 213         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 214         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 215         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 216         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 217         case PIPE_CAP_USER_INDEX_BUFFERS:
 218         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 219         case PIPE_CAP_START_INSTANCE:
 220         case PIPE_CAP_NPOT_TEXTURES:
 221         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 222         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 223         case PIPE_CAP_TGSI_INSTANCEID:
 224         case PIPE_CAP_COMPUTE:
 225         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 226         case PIPE_CAP_TGSI_VS_LAYER:
 227         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 228         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 229                 return 1;
 230
 231         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 232                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 233                 return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
 234                                                sscreen->b.info.drm_minor >= 35);
 235
 236         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 237                 return R600_MAP_BUFFER_ALIGNMENT;
 238
 239         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 240         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 241                 return 4;
 242
 243         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 244                 return HAVE_LLVM >= 0x0305 ? 330 : 140;
 245
 246         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 247                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 248
 249         /* Unsupported features. */
 250         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 251         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 252         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 253         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 254         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 255         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 256         case PIPE_CAP_USER_VERTEX_BUFFERS:
 257         case PIPE_CAP_CUBE_MAP_ARRAY:
 258         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 259         case PIPE_CAP_TEXTURE_GATHER_SM5:
 260         case PIPE_CAP_TGSI_TEXCOORD:
 261         case PIPE_CAP_FAKE_SW_MSAA:
 262         case PIPE_CAP_TEXTURE_QUERY_LOD:
 263                 return 0;
 264
 265         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 266                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 267
 268         /* Stream output. */
 269         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 270                 return sscreen->b.has_streamout ? 4 : 0;
 271         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 272                 return sscreen->b.has_streamout ? 1 : 0;
 273         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 274         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 275                 return sscreen->b.has_streamout ? 32*4 : 0;
 276
 277         /* Geometry shader output. */
 278         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 279                 return 1024;
 280         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 281                 return 4095;
 282
 283         /* Texturing. */
 284         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 285         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 286                 return 15; /* 16384 */
 287         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 288                 /* textures support 8192, but layered rendering supports 2048 */
 289                 return 12;
 290         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 291                 /* textures support 8192, but layered rendering supports 2048 */
 292                 return 2048;
 293
 294         /* Render targets. */
 295         case PIPE_CAP_MAX_RENDER_TARGETS:
 296                 return 8;
 297
 298         case PIPE_CAP_MAX_VIEWPORTS:
 299                 return 1;
 300
 301         /* Timer queries, present when the clock frequency is non zero. */
 302         case PIPE_CAP_QUERY_TIMESTAMP:
 303         case PIPE_CAP_QUERY_TIME_ELAPSED:
 304                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 305
 306         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 307         case PIPE_CAP_MIN_TEXEL_OFFSET:
 308                 return -8;
 309
 310         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 311         case PIPE_CAP_MAX_TEXEL_OFFSET:
 312                 return 7;
 313         case PIPE_CAP_ENDIANNESS:
 314                 return PIPE_ENDIAN_LITTLE;
 315         }
 316         return 0;
 317 }
 318
 319 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 320 {
 321         switch(shader)
 322         {
 323         case PIPE_SHADER_FRAGMENT:
 324         case PIPE_SHADER_VERTEX:
 325                 break;
 326         case PIPE_SHADER_GEOMETRY:
 327 #if HAVE_LLVM < 0x0305
 328                 return 0;
 329 #endif
 330                 break;
 331         case PIPE_SHADER_COMPUTE:
 332                 switch (param) {
 333                 case PIPE_SHADER_CAP_PREFERRED_IR:
 334                         return PIPE_SHADER_IR_LLVM;
 335                 default:
 336                         return 0;
 337                 }
 338         default:
 339                 /* TODO: support tessellation */
 340                 return 0;
 341         }
 342
 343         switch (param) {
 344         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 345         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 346         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 347         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 348                 return 16384;
 349         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 350                 return 32;
 351         case PIPE_SHADER_CAP_MAX_INPUTS:
 352                 return 32;
 353         case PIPE_SHADER_CAP_MAX_TEMPS:
 354                 return 256; /* Max native temporaries. */
 355         case PIPE_SHADER_CAP_MAX_ADDRS:
 356                 /* FIXME Isn't this equal to TEMPS? */
 357                 return 1; /* Max native address registers */
 358         case PIPE_SHADER_CAP_MAX_CONSTS:
 359                 return 4096; /* actually only memory limits this */
 360         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 361                 return NUM_PIPE_CONST_BUFFERS;
 362         case PIPE_SHADER_CAP_MAX_PREDS:
 363                 return 0; /* FIXME */
 364         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 365                 return 1;
 366         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 367                 return 0;
 368         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 369                 /* Indirection of geometry shader input dimension is not
 370                  * handled yet
 371                  */
 372                 return shader < PIPE_SHADER_GEOMETRY;
 373         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 374         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 375         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 376                 return 1;
 377         case PIPE_SHADER_CAP_INTEGERS:
 378                 return 1;
 379         case PIPE_SHADER_CAP_SUBROUTINES:
 380                 return 0;
 381         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 382         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 383                 return 16;
 384         case PIPE_SHADER_CAP_PREFERRED_IR:
 385                 return PIPE_SHADER_IR_TGSI;
 386         }
 387         return 0;
 388 }
 389
 390 static void si_destroy_screen(struct pipe_screen* pscreen)
 391 {
 392         struct si_screen *sscreen = (struct si_screen *)pscreen;
 393
 394         if (sscreen == NULL)
 395                 return;
 396
 397         if (!sscreen->b.ws->unref(sscreen->b.ws))
 398                 return;
 399
 400         r600_destroy_common_screen(&sscreen->b);
 401 }
 402
 403 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 404 {
 405         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 406         if (sscreen == NULL) {
 407                 return NULL;
 408         }
 409
 410         /* Set functions first. */
 411         sscreen->b.b.context_create = si_create_context;
 412         sscreen->b.b.destroy = si_destroy_screen;
 413         sscreen->b.b.get_param = si_get_param;
 414         sscreen->b.b.get_shader_param = si_get_shader_param;
 415         sscreen->b.b.is_format_supported = si_is_format_supported;
 416         sscreen->b.b.resource_create = r600_resource_create_common;
 417
 418         if (!r600_common_screen_init(&sscreen->b, ws)) {
 419                 FREE(sscreen);
 420                 return NULL;
 421         }
 422
 423         sscreen->b.has_cp_dma = true;
 424         sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 425
 426         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 427                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 428
 429         /* Create the auxiliary context. This must be done last. */
 430         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 431
 432         return &sscreen->b.b;
 433 }