2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
26 #include "si_shader_internal.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/u_memory.h"
31 #include "util/u_suballoc.h"
32 #include "util/u_tests.h"
33 #include "vl/vl_decoder.h"
34 #include "../ddebug/dd_util.h"
36 #define SI_LLVM_DEFAULT_FEATURES \
37 "+DumpCode,+vgpr-spilling,-fp32-denormals,-xnack"
42 static void si_destroy_context(struct pipe_context
*context
)
44 struct si_context
*sctx
= (struct si_context
*)context
;
47 /* Unreference the framebuffer normally to disable related logic
50 struct pipe_framebuffer_state fb
= {};
51 context
->set_framebuffer_state(context
, &fb
);
53 si_release_all_descriptors(sctx
);
55 if (sctx
->ce_suballocator
)
56 u_suballocator_destroy(sctx
->ce_suballocator
);
58 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
59 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
60 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
61 pipe_resource_reference(&sctx
->tess_offchip_ring
, NULL
);
62 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
63 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
64 free(sctx
->border_color_table
);
65 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
66 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
68 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
69 if (sctx
->init_config_gs_rings
)
70 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
71 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
72 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
74 if (sctx
->fixed_func_tcs_shader
.cso
)
75 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
.cso
);
76 if (sctx
->custom_dsa_flush
)
77 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
78 if (sctx
->custom_blend_resolve
)
79 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
80 if (sctx
->custom_blend_decompress
)
81 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
82 if (sctx
->custom_blend_fastclear
)
83 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fastclear
);
84 if (sctx
->custom_blend_dcc_decompress
)
85 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_dcc_decompress
);
88 util_blitter_destroy(sctx
->blitter
);
90 r600_common_context_cleanup(&sctx
->b
);
92 LLVMDisposeTargetMachine(sctx
->tm
);
94 r600_resource_reference(&sctx
->trace_buf
, NULL
);
95 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
96 radeon_clear_saved_cs(&sctx
->last_gfx
);
101 static enum pipe_reset_status
102 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
104 struct si_context
*sctx
= (struct si_context
*)ctx
;
106 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
109 /* Apitrace profiling:
110 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
111 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
112 * and remember its number.
113 * 3) In Mesa, enable queries and performance counters around that draw
114 * call and print the results.
115 * 4) glretrace --benchmark --markers ..
117 static void si_emit_string_marker(struct pipe_context
*ctx
,
118 const char *string
, int len
)
120 struct si_context
*sctx
= (struct si_context
*)ctx
;
122 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
125 static LLVMTargetMachineRef
126 si_create_llvm_target_machine(struct si_screen
*sscreen
)
128 const char *triple
= "amdgcn--";
130 return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple
), triple
,
131 r600_get_llvm_processor_name(sscreen
->b
.family
),
132 sscreen
->b
.debug_flags
& DBG_SI_SCHED
?
133 SI_LLVM_DEFAULT_FEATURES
",+si-scheduler" :
134 SI_LLVM_DEFAULT_FEATURES
,
135 LLVMCodeGenLevelDefault
,
137 LLVMCodeModelDefault
);
140 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
141 void *priv
, unsigned flags
)
143 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
144 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
145 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
151 if (sscreen
->b
.debug_flags
& DBG_CHECK_VM
)
152 flags
|= PIPE_CONTEXT_DEBUG
;
154 if (flags
& PIPE_CONTEXT_DEBUG
)
155 sscreen
->record_llvm_ir
= true; /* racy but not critical */
157 sctx
->b
.b
.screen
= screen
; /* this must be set first */
158 sctx
->b
.b
.priv
= priv
;
159 sctx
->b
.b
.destroy
= si_destroy_context
;
160 sctx
->b
.b
.emit_string_marker
= si_emit_string_marker
;
161 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
162 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
163 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
165 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
, flags
))
168 if (sscreen
->b
.info
.drm_major
== 3)
169 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
171 si_init_blit_functions(sctx
);
172 si_init_compute_functions(sctx
);
173 si_init_cp_dma_functions(sctx
);
174 si_init_debug_functions(sctx
);
176 if (sscreen
->b
.info
.has_uvd
) {
177 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
178 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
180 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
181 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
184 sctx
->b
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
,
185 si_context_gfx_flush
, sctx
);
187 /* SI + AMDGPU + CE = GPU hang */
188 if (!(sscreen
->b
.debug_flags
& DBG_NO_CE
) && ws
->cs_add_const_ib
&&
189 sscreen
->b
.chip_class
!= SI
&&
190 /* These can't use CE due to a power gating bug in the kernel. */
191 sscreen
->b
.family
!= CHIP_CARRIZO
&&
192 sscreen
->b
.family
!= CHIP_STONEY
&&
193 /* Some CE bug is causing green screen corruption w/ MPV video
194 * playback and occasional corruption w/ 3D. */
195 sscreen
->b
.chip_class
!= GFX9
) {
196 sctx
->ce_ib
= ws
->cs_add_const_ib(sctx
->b
.gfx
.cs
);
200 if (ws
->cs_add_const_preamble_ib
) {
201 sctx
->ce_preamble_ib
=
202 ws
->cs_add_const_preamble_ib(sctx
->b
.gfx
.cs
);
204 if (!sctx
->ce_preamble_ib
)
208 sctx
->ce_suballocator
=
209 u_suballocator_create(&sctx
->b
.b
, 1024 * 1024, 0,
211 R600_RESOURCE_FLAG_UNMAPPABLE
, false);
212 if (!sctx
->ce_suballocator
)
216 sctx
->b
.gfx
.flush
= si_context_gfx_flush
;
219 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
220 sizeof(*sctx
->border_color_table
));
221 if (!sctx
->border_color_table
)
224 sctx
->border_color_buffer
= (struct r600_resource
*)
225 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
226 SI_MAX_BORDER_COLORS
*
227 sizeof(*sctx
->border_color_table
));
228 if (!sctx
->border_color_buffer
)
231 sctx
->border_color_map
=
232 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
233 NULL
, PIPE_TRANSFER_WRITE
);
234 if (!sctx
->border_color_map
)
237 si_init_all_descriptors(sctx
);
238 si_init_state_functions(sctx
);
239 si_init_shader_functions(sctx
);
240 si_init_ia_multi_vgt_param_table(sctx
);
242 if (sctx
->b
.chip_class
>= CIK
)
243 cik_init_sdma_functions(sctx
);
245 si_init_dma_functions(sctx
);
247 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
248 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
250 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
251 if (sctx
->blitter
== NULL
)
253 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
255 sctx
->sample_mask
.sample_mask
= 0xffff;
257 /* these must be last */
258 si_begin_new_cs(sctx
);
260 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
261 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
262 if (sctx
->b
.chip_class
== CIK
) {
263 sctx
->null_const_buf
.buffer
=
264 r600_aligned_buffer_create(screen
,
265 R600_RESOURCE_FLAG_UNMAPPABLE
,
266 PIPE_USAGE_DEFAULT
, 16,
267 sctx
->screen
->b
.info
.tcc_cache_line_size
);
268 if (!sctx
->null_const_buf
.buffer
)
270 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
272 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
273 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
274 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
275 &sctx
->null_const_buf
);
279 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
280 &sctx
->null_const_buf
);
281 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
282 &sctx
->null_const_buf
);
283 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
284 &sctx
->null_const_buf
);
285 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
286 &sctx
->null_const_buf
);
288 /* Clear the NULL constant buffer, because loads should return zeros. */
289 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
290 sctx
->null_const_buf
.buffer
->width0
, 0,
291 R600_COHERENCY_SHADER
);
294 uint64_t max_threads_per_block
;
295 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
296 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
297 &max_threads_per_block
);
299 /* The maximum number of scratch waves. Scratch space isn't divided
300 * evenly between CUs. The number is only a function of the number of CUs.
301 * We can decrease the constant to decrease the scratch buffer size.
303 * sctx->scratch_waves must be >= the maximum posible size of
304 * 1 threadgroup, so that the hw doesn't hang from being unable
307 * The recommended value is 4 per CU at most. Higher numbers don't
308 * bring much benefit, but they still occupy chip resources (think
309 * async compute). I've seen ~2% performance difference between 4 and 32.
311 sctx
->scratch_waves
= MAX2(32 * sscreen
->b
.info
.num_good_compute_units
,
312 max_threads_per_block
/ 64);
314 sctx
->tm
= si_create_llvm_target_machine(sscreen
);
318 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
319 si_destroy_context(&sctx
->b
.b
);
326 static bool si_have_tgsi_compute(struct si_screen
*sscreen
)
328 /* Old kernels disallowed some register writes for SI
329 * that are used for indirect dispatches. */
330 return HAVE_LLVM
>= 0x309 &&
331 (sscreen
->b
.chip_class
>= CIK
||
332 sscreen
->b
.info
.drm_major
== 3 ||
333 (sscreen
->b
.info
.drm_major
== 2 &&
334 sscreen
->b
.info
.drm_minor
>= 45));
337 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
339 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
342 /* Supported features (boolean caps). */
343 case PIPE_CAP_ACCELERATED
:
344 case PIPE_CAP_TWO_SIDED_STENCIL
:
345 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
346 case PIPE_CAP_ANISOTROPIC_FILTER
:
347 case PIPE_CAP_POINT_SPRITE
:
348 case PIPE_CAP_OCCLUSION_QUERY
:
349 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
350 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
351 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
352 case PIPE_CAP_TEXTURE_SWIZZLE
:
353 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
354 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
355 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
356 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
357 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
358 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
359 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
361 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
362 case PIPE_CAP_PRIMITIVE_RESTART
:
363 case PIPE_CAP_CONDITIONAL_RENDER
:
364 case PIPE_CAP_TEXTURE_BARRIER
:
365 case PIPE_CAP_INDEP_BLEND_ENABLE
:
366 case PIPE_CAP_INDEP_BLEND_FUNC
:
367 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
368 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
369 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
370 case PIPE_CAP_START_INSTANCE
:
371 case PIPE_CAP_NPOT_TEXTURES
:
372 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
373 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
374 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
375 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
376 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
377 case PIPE_CAP_TGSI_INSTANCEID
:
378 case PIPE_CAP_COMPUTE
:
379 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
380 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
381 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
382 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
383 case PIPE_CAP_CUBE_MAP_ARRAY
:
384 case PIPE_CAP_SAMPLE_SHADING
:
385 case PIPE_CAP_DRAW_INDIRECT
:
386 case PIPE_CAP_CLIP_HALFZ
:
387 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
388 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
389 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
390 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
391 case PIPE_CAP_TGSI_TEXCOORD
:
392 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
393 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
394 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
395 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
396 case PIPE_CAP_SHAREABLE_SHADERS
:
397 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
398 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
399 case PIPE_CAP_TEXTURE_QUERY_LOD
:
400 case PIPE_CAP_TEXTURE_GATHER_SM5
:
401 case PIPE_CAP_TGSI_TXQS
:
402 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
403 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
404 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
405 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
406 case PIPE_CAP_INVALIDATE_BUFFER
:
407 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
408 case PIPE_CAP_QUERY_MEMORY_INFO
:
409 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
410 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
411 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
412 case PIPE_CAP_GENERATE_MIPMAP
:
413 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
414 case PIPE_CAP_STRING_MARKER
:
415 case PIPE_CAP_CLEAR_TEXTURE
:
416 case PIPE_CAP_CULL_DISTANCE
:
417 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
418 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
419 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
420 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
421 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
422 case PIPE_CAP_DOUBLES
:
423 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
427 case PIPE_CAP_INT64_DIVMOD
:
428 case PIPE_CAP_TGSI_CLOCK
:
429 return HAVE_LLVM
>= 0x0309;
431 case PIPE_CAP_TGSI_VOTE
:
432 return HAVE_LLVM
>= 0x0400;
434 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
435 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
437 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
438 return (sscreen
->b
.info
.drm_major
== 2 &&
439 sscreen
->b
.info
.drm_minor
>= 43) ||
440 sscreen
->b
.info
.drm_major
== 3;
442 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
443 /* 2D tiling on CIK is supported since DRM 2.35.0 */
444 return sscreen
->b
.chip_class
< CIK
||
445 (sscreen
->b
.info
.drm_major
== 2 &&
446 sscreen
->b
.info
.drm_minor
>= 35) ||
447 sscreen
->b
.info
.drm_major
== 3;
449 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
450 return R600_MAP_BUFFER_ALIGNMENT
;
452 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
453 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
454 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
455 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
456 case PIPE_CAP_MAX_VERTEX_STREAMS
:
459 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
460 return HAVE_LLVM
>= 0x0309 ? 4 : 0;
462 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
463 if (sscreen
->b
.chip_class
>= GFX9
)
465 if (si_have_tgsi_compute(sscreen
))
467 return HAVE_LLVM
>= 0x0309 ? 420 : 410;
469 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
470 return MIN2(sscreen
->b
.info
.max_alloc_size
, INT_MAX
);
472 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
473 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
474 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
475 /* SI doesn't support unaligned loads.
476 * CIK needs DRM 2.50.0 on radeon. */
477 return sscreen
->b
.chip_class
== SI
||
478 (sscreen
->b
.info
.drm_major
== 2 &&
479 sscreen
->b
.info
.drm_minor
< 50);
481 /* Unsupported features. */
482 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
483 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
484 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
485 case PIPE_CAP_USER_VERTEX_BUFFERS
:
486 case PIPE_CAP_FAKE_SW_MSAA
:
487 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
488 case PIPE_CAP_VERTEXID_NOBASE
:
489 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
490 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
491 case PIPE_CAP_NATIVE_FENCE_FD
:
492 case PIPE_CAP_TGSI_FS_FBFETCH
:
493 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
495 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
496 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
499 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
500 return si_have_tgsi_compute(sscreen
);
502 case PIPE_CAP_DRAW_PARAMETERS
:
503 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
504 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
505 return sscreen
->has_draw_indirect_multi
;
507 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
510 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
511 return sscreen
->b
.chip_class
<= VI
?
512 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
515 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
516 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
519 /* Geometry shader output. */
520 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
522 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
525 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
529 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
530 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
531 return 15; /* 16384 */
532 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
533 /* textures support 8192, but layered rendering supports 2048 */
535 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
536 /* textures support 8192, but layered rendering supports 2048 */
539 /* Viewports and render targets. */
540 case PIPE_CAP_MAX_VIEWPORTS
:
541 return R600_MAX_VIEWPORTS
;
542 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
543 case PIPE_CAP_MAX_RENDER_TARGETS
:
546 /* Timer queries, present when the clock frequency is non zero. */
547 case PIPE_CAP_QUERY_TIMESTAMP
:
548 case PIPE_CAP_QUERY_TIME_ELAPSED
:
549 return sscreen
->b
.info
.clock_crystal_freq
!= 0;
551 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
552 case PIPE_CAP_MIN_TEXEL_OFFSET
:
555 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
556 case PIPE_CAP_MAX_TEXEL_OFFSET
:
559 case PIPE_CAP_ENDIANNESS
:
560 return PIPE_ENDIAN_LITTLE
;
562 case PIPE_CAP_VENDOR_ID
:
563 return ATI_VENDOR_ID
;
564 case PIPE_CAP_DEVICE_ID
:
565 return sscreen
->b
.info
.pci_id
;
566 case PIPE_CAP_VIDEO_MEMORY
:
567 return sscreen
->b
.info
.vram_size
>> 20;
568 case PIPE_CAP_PCI_GROUP
:
569 return sscreen
->b
.info
.pci_domain
;
570 case PIPE_CAP_PCI_BUS
:
571 return sscreen
->b
.info
.pci_bus
;
572 case PIPE_CAP_PCI_DEVICE
:
573 return sscreen
->b
.info
.pci_dev
;
574 case PIPE_CAP_PCI_FUNCTION
:
575 return sscreen
->b
.info
.pci_func
;
580 static int si_get_shader_param(struct pipe_screen
* pscreen
,
581 enum pipe_shader_type shader
,
582 enum pipe_shader_cap param
)
584 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
588 case PIPE_SHADER_FRAGMENT
:
589 case PIPE_SHADER_VERTEX
:
591 case PIPE_SHADER_GEOMETRY
:
592 case PIPE_SHADER_TESS_CTRL
:
593 case PIPE_SHADER_TESS_EVAL
:
594 if (sscreen
->b
.chip_class
>= GFX9
)
597 case PIPE_SHADER_COMPUTE
:
599 case PIPE_SHADER_CAP_PREFERRED_IR
:
600 return PIPE_SHADER_IR_NATIVE
;
602 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
603 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
605 if (si_have_tgsi_compute(sscreen
))
606 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
611 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
612 uint64_t max_const_buffer_size
;
613 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
614 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
615 &max_const_buffer_size
);
616 return MIN2(max_const_buffer_size
, INT_MAX
);
619 /* If compute shaders don't require a special value
620 * for this cap, we can return the same value we
621 * do for other shader types. */
631 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
632 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
633 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
634 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
635 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
637 case PIPE_SHADER_CAP_MAX_INPUTS
:
638 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
639 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
640 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
641 case PIPE_SHADER_CAP_MAX_TEMPS
:
642 return 256; /* Max native temporaries. */
643 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
644 return 4096 * sizeof(float[4]); /* actually only memory limits this */
645 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
646 return SI_NUM_CONST_BUFFERS
;
647 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
648 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
649 return SI_NUM_SAMPLERS
;
650 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
651 return HAVE_LLVM
>= 0x0309 ? SI_NUM_SHADER_BUFFERS
: 0;
652 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
653 return HAVE_LLVM
>= 0x0309 ? SI_NUM_IMAGES
: 0;
654 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
656 case PIPE_SHADER_CAP_PREFERRED_IR
:
657 return PIPE_SHADER_IR_TGSI
;
658 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
661 /* Supported boolean features. */
662 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
663 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
664 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
665 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
666 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
667 case PIPE_SHADER_CAP_INTEGERS
:
668 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
669 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
672 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
673 /* TODO: Indirection of geometry shader input dimension is not
676 return shader
!= PIPE_SHADER_GEOMETRY
;
678 /* Unsupported boolean features. */
679 case PIPE_SHADER_CAP_SUBROUTINES
:
680 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
681 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
682 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
688 static void si_destroy_screen(struct pipe_screen
* pscreen
)
690 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
691 struct si_shader_part
*parts
[] = {
694 sscreen
->tcs_epilogs
,
701 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
704 util_queue_destroy(&sscreen
->shader_compiler_queue
);
706 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm
); i
++)
708 LLVMDisposeTargetMachine(sscreen
->tm
[i
]);
710 /* Free shader parts. */
711 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
713 struct si_shader_part
*part
= parts
[i
];
715 parts
[i
] = part
->next
;
716 radeon_shader_binary_clean(&part
->binary
);
720 mtx_destroy(&sscreen
->shader_parts_mutex
);
721 si_destroy_shader_cache(sscreen
);
722 r600_destroy_common_screen(&sscreen
->b
);
725 static bool si_init_gs_info(struct si_screen
*sscreen
)
727 switch (sscreen
->b
.family
) {
736 sscreen
->gs_table_depth
= 16;
749 sscreen
->gs_table_depth
= 32;
756 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
758 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
764 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
765 if (!strcmp(family
, r600_get_llvm_processor_name(i
))) {
766 /* Override family and chip_class. */
767 sscreen
->b
.family
= sscreen
->b
.info
.family
= i
;
769 if (i
>= CHIP_VEGA10
)
770 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= GFX9
;
771 else if (i
>= CHIP_TONGA
)
772 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= VI
;
773 else if (i
>= CHIP_BONAIRE
)
774 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= CIK
;
776 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= SI
;
778 /* Don't submit any IBs. */
779 setenv("RADEON_NOOP", "1", 1);
784 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
788 static void si_test_vmfault(struct si_screen
*sscreen
)
790 struct pipe_context
*ctx
= sscreen
->b
.aux_context
;
791 struct si_context
*sctx
= (struct si_context
*)ctx
;
792 struct pipe_resource
*buf
=
793 pipe_buffer_create(&sscreen
->b
.b
, 0, PIPE_USAGE_DEFAULT
, 64);
796 puts("Buffer allocation failed.");
800 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
802 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_CP
) {
803 si_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0);
804 ctx
->flush(ctx
, NULL
, 0);
805 puts("VM fault test: CP - done.");
807 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_SDMA
) {
808 sctx
->b
.dma_clear_buffer(ctx
, buf
, 0, 4, 0);
809 ctx
->flush(ctx
, NULL
, 0);
810 puts("VM fault test: SDMA - done.");
812 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_SHADER
) {
813 util_test_constant_buffer(ctx
, buf
);
814 puts("VM fault test: Shader - done.");
819 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
821 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
822 unsigned num_cpus
, num_compiler_threads
, i
;
828 /* Set functions first. */
829 sscreen
->b
.b
.context_create
= si_create_context
;
830 sscreen
->b
.b
.destroy
= si_destroy_screen
;
831 sscreen
->b
.b
.get_param
= si_get_param
;
832 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
833 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
835 si_init_screen_state_functions(sscreen
);
837 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
838 !si_init_gs_info(sscreen
) ||
839 !si_init_shader_cache(sscreen
)) {
844 /* Only enable as many threads as we have target machines and CPUs. */
845 num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
846 num_compiler_threads
= MIN2(num_cpus
, ARRAY_SIZE(sscreen
->tm
));
848 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "si_shader",
849 32, num_compiler_threads
)) {
850 si_destroy_shader_cache(sscreen
);
855 si_handle_env_var_force_family(sscreen
);
857 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
858 si_init_perfcounters(sscreen
);
860 /* Hawaii has a bug with offchip buffers > 256 that can be worked
861 * around by setting 4K granularity.
863 sscreen
->tess_offchip_block_dw_size
=
864 sscreen
->b
.family
== CHIP_HAWAII
? 4096 : 8192;
866 sscreen
->has_distributed_tess
=
867 sscreen
->b
.chip_class
>= VI
&&
868 sscreen
->b
.info
.max_se
>= 2;
870 sscreen
->has_draw_indirect_multi
=
871 (sscreen
->b
.family
>= CHIP_POLARIS10
) ||
872 (sscreen
->b
.chip_class
== VI
&&
873 sscreen
->b
.info
.pfp_fw_version
>= 121 &&
874 sscreen
->b
.info
.me_fw_version
>= 87) ||
875 (sscreen
->b
.chip_class
== CIK
&&
876 sscreen
->b
.info
.pfp_fw_version
>= 211 &&
877 sscreen
->b
.info
.me_fw_version
>= 173) ||
878 (sscreen
->b
.chip_class
== SI
&&
879 sscreen
->b
.info
.pfp_fw_version
>= 121 &&
880 sscreen
->b
.info
.me_fw_version
>= 87);
882 sscreen
->has_ds_bpermute
= HAVE_LLVM
>= 0x0309 &&
883 sscreen
->b
.chip_class
>= VI
;
885 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->b
.family
>= CHIP_POLARIS10
&&
886 sscreen
->b
.family
<= CHIP_POLARIS12
) ||
887 sscreen
->b
.family
== CHIP_VEGA10
;
889 sscreen
->b
.has_cp_dma
= true;
890 sscreen
->b
.has_streamout
= true;
892 /* Some chips have RB+ registers, but don't support RB+. Those must
895 if (sscreen
->b
.family
== CHIP_STONEY
||
896 sscreen
->b
.chip_class
>= GFX9
) {
897 sscreen
->b
.has_rbplus
= true;
899 sscreen
->b
.rbplus_allowed
=
900 !(sscreen
->b
.debug_flags
& DBG_NO_RB_PLUS
) &&
901 sscreen
->b
.family
== CHIP_STONEY
;
904 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
905 sscreen
->use_monolithic_shaders
=
906 (sscreen
->b
.debug_flags
& DBG_MONOLITHIC_SHADERS
) != 0;
908 sscreen
->b
.barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
909 SI_CONTEXT_INV_VMEM_L1
|
910 SI_CONTEXT_INV_GLOBAL_L2
;
911 sscreen
->b
.barrier_flags
.compute_to_L2
= SI_CONTEXT_CS_PARTIAL_FLUSH
;
913 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
914 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
916 for (i
= 0; i
< num_compiler_threads
; i
++)
917 sscreen
->tm
[i
] = si_create_llvm_target_machine(sscreen
);
919 /* Create the auxiliary context. This must be done last. */
920 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
, 0);
922 if (sscreen
->b
.debug_flags
& DBG_TEST_DMA
)
923 r600_test_dma(&sscreen
->b
);
925 if (sscreen
->b
.debug_flags
& (DBG_TEST_VMFAULT_CP
|
926 DBG_TEST_VMFAULT_SDMA
|
927 DBG_TEST_VMFAULT_SHADER
))
928 si_test_vmfault(sscreen
);
930 return &sscreen
->b
.b
;