2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
26 #include "si_shader_internal.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_suballoc.h"
33 #include "util/u_tests.h"
34 #include "vl/vl_decoder.h"
35 #include "../ddebug/dd_util.h"
40 static void si_destroy_context(struct pipe_context
*context
)
42 struct si_context
*sctx
= (struct si_context
*)context
;
45 /* Unreference the framebuffer normally to disable related logic
48 struct pipe_framebuffer_state fb
= {};
49 if (context
->set_framebuffer_state
)
50 context
->set_framebuffer_state(context
, &fb
);
52 si_release_all_descriptors(sctx
);
54 if (sctx
->ce_suballocator
)
55 u_suballocator_destroy(sctx
->ce_suballocator
);
57 r600_resource_reference(&sctx
->ce_ram_saved_buffer
, NULL
);
58 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
59 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
60 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
61 pipe_resource_reference(&sctx
->tess_offchip_ring
, NULL
);
62 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
63 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
64 free(sctx
->border_color_table
);
65 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
66 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
68 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
69 if (sctx
->init_config_gs_rings
)
70 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
71 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
72 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
74 if (sctx
->fixed_func_tcs_shader
.cso
)
75 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
.cso
);
76 if (sctx
->custom_dsa_flush
)
77 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
78 if (sctx
->custom_blend_resolve
)
79 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
80 if (sctx
->custom_blend_fmask_decompress
)
81 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fmask_decompress
);
82 if (sctx
->custom_blend_eliminate_fastclear
)
83 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_eliminate_fastclear
);
84 if (sctx
->custom_blend_dcc_decompress
)
85 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_dcc_decompress
);
88 util_blitter_destroy(sctx
->blitter
);
90 r600_common_context_cleanup(&sctx
->b
);
92 LLVMDisposeTargetMachine(sctx
->tm
);
94 r600_resource_reference(&sctx
->trace_buf
, NULL
);
95 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
96 radeon_clear_saved_cs(&sctx
->last_gfx
);
98 pb_slabs_deinit(&sctx
->bindless_descriptor_slabs
);
99 util_dynarray_fini(&sctx
->bindless_descriptors
);
101 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
102 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
104 util_dynarray_fini(&sctx
->resident_tex_handles
);
105 util_dynarray_fini(&sctx
->resident_img_handles
);
106 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
107 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
108 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
112 static enum pipe_reset_status
113 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
115 struct si_context
*sctx
= (struct si_context
*)ctx
;
117 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
120 /* Apitrace profiling:
121 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
122 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
123 * and remember its number.
124 * 3) In Mesa, enable queries and performance counters around that draw
125 * call and print the results.
126 * 4) glretrace --benchmark --markers ..
128 static void si_emit_string_marker(struct pipe_context
*ctx
,
129 const char *string
, int len
)
131 struct si_context
*sctx
= (struct si_context
*)ctx
;
133 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
136 static LLVMTargetMachineRef
137 si_create_llvm_target_machine(struct si_screen
*sscreen
)
139 const char *triple
= "amdgcn--";
142 snprintf(features
, sizeof(features
),
143 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s",
144 sscreen
->b
.chip_class
>= GFX9
? ",+xnack" : ",-xnack",
145 sscreen
->b
.debug_flags
& DBG_SI_SCHED
? ",+si-scheduler" : "");
147 return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple
), triple
,
148 r600_get_llvm_processor_name(sscreen
->b
.family
),
150 LLVMCodeGenLevelDefault
,
152 LLVMCodeModelDefault
);
155 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
158 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
159 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
160 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
166 if (sscreen
->b
.debug_flags
& DBG_CHECK_VM
)
167 flags
|= PIPE_CONTEXT_DEBUG
;
169 if (flags
& PIPE_CONTEXT_DEBUG
)
170 sscreen
->record_llvm_ir
= true; /* racy but not critical */
172 sctx
->b
.b
.screen
= screen
; /* this must be set first */
173 sctx
->b
.b
.priv
= NULL
;
174 sctx
->b
.b
.destroy
= si_destroy_context
;
175 sctx
->b
.b
.emit_string_marker
= si_emit_string_marker
;
176 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
177 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
178 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
180 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
, flags
))
183 if (sscreen
->b
.info
.drm_major
== 3)
184 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
186 si_init_blit_functions(sctx
);
187 si_init_compute_functions(sctx
);
188 si_init_cp_dma_functions(sctx
);
189 si_init_debug_functions(sctx
);
191 if (sscreen
->b
.info
.has_hw_decode
) {
192 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
193 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
195 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
196 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
199 sctx
->b
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
,
200 si_context_gfx_flush
, sctx
);
202 /* SI + AMDGPU + CE = GPU hang */
203 if (!(sscreen
->b
.debug_flags
& DBG_NO_CE
) && ws
->cs_add_const_ib
&&
204 sscreen
->b
.chip_class
!= SI
&&
205 /* These can't use CE due to a power gating bug in the kernel. */
206 sscreen
->b
.family
!= CHIP_CARRIZO
&&
207 sscreen
->b
.family
!= CHIP_STONEY
&&
208 /* Some CE bug is causing green screen corruption w/ MPV video
209 * playback and occasional corruption w/ 3D. */
210 sscreen
->b
.chip_class
!= GFX9
) {
211 sctx
->ce_ib
= ws
->cs_add_const_ib(sctx
->b
.gfx
.cs
);
215 if (ws
->cs_add_const_preamble_ib
) {
216 sctx
->ce_preamble_ib
=
217 ws
->cs_add_const_preamble_ib(sctx
->b
.gfx
.cs
);
219 if (!sctx
->ce_preamble_ib
)
223 sctx
->ce_suballocator
=
224 u_suballocator_create(&sctx
->b
.b
, 1024 * 1024, 0,
226 R600_RESOURCE_FLAG_UNMAPPABLE
, false);
227 if (!sctx
->ce_suballocator
)
231 sctx
->b
.gfx
.flush
= si_context_gfx_flush
;
234 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
235 sizeof(*sctx
->border_color_table
));
236 if (!sctx
->border_color_table
)
239 sctx
->border_color_buffer
= (struct r600_resource
*)
240 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
241 SI_MAX_BORDER_COLORS
*
242 sizeof(*sctx
->border_color_table
));
243 if (!sctx
->border_color_buffer
)
246 sctx
->border_color_map
=
247 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
248 NULL
, PIPE_TRANSFER_WRITE
);
249 if (!sctx
->border_color_map
)
252 si_init_all_descriptors(sctx
);
253 si_init_state_functions(sctx
);
254 si_init_shader_functions(sctx
);
255 si_init_ia_multi_vgt_param_table(sctx
);
257 if (sctx
->b
.chip_class
>= CIK
)
258 cik_init_sdma_functions(sctx
);
260 si_init_dma_functions(sctx
);
262 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
263 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
265 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
266 if (sctx
->blitter
== NULL
)
268 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
270 sctx
->sample_mask
.sample_mask
= 0xffff;
272 /* these must be last */
273 si_begin_new_cs(sctx
);
275 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
276 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
277 if (sctx
->b
.chip_class
== CIK
) {
278 sctx
->null_const_buf
.buffer
=
279 r600_aligned_buffer_create(screen
,
280 R600_RESOURCE_FLAG_UNMAPPABLE
,
281 PIPE_USAGE_DEFAULT
, 16,
282 sctx
->screen
->b
.info
.tcc_cache_line_size
);
283 if (!sctx
->null_const_buf
.buffer
)
285 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
287 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
288 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
289 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
290 &sctx
->null_const_buf
);
294 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
295 &sctx
->null_const_buf
);
296 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
297 &sctx
->null_const_buf
);
298 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
299 &sctx
->null_const_buf
);
300 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
301 &sctx
->null_const_buf
);
303 /* Clear the NULL constant buffer, because loads should return zeros. */
304 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
305 sctx
->null_const_buf
.buffer
->width0
, 0,
306 R600_COHERENCY_SHADER
);
309 uint64_t max_threads_per_block
;
310 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
311 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
312 &max_threads_per_block
);
314 /* The maximum number of scratch waves. Scratch space isn't divided
315 * evenly between CUs. The number is only a function of the number of CUs.
316 * We can decrease the constant to decrease the scratch buffer size.
318 * sctx->scratch_waves must be >= the maximum posible size of
319 * 1 threadgroup, so that the hw doesn't hang from being unable
322 * The recommended value is 4 per CU at most. Higher numbers don't
323 * bring much benefit, but they still occupy chip resources (think
324 * async compute). I've seen ~2% performance difference between 4 and 32.
326 sctx
->scratch_waves
= MAX2(32 * sscreen
->b
.info
.num_good_compute_units
,
327 max_threads_per_block
/ 64);
329 sctx
->tm
= si_create_llvm_target_machine(sscreen
);
331 /* Create a slab allocator for all bindless descriptors. */
332 if (!pb_slabs_init(&sctx
->bindless_descriptor_slabs
, 6, 6, 1, sctx
,
333 si_bindless_descriptor_can_reclaim_slab
,
334 si_bindless_descriptor_slab_alloc
,
335 si_bindless_descriptor_slab_free
))
338 util_dynarray_init(&sctx
->bindless_descriptors
, NULL
);
340 /* Bindless handles. */
341 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
342 _mesa_key_pointer_equal
);
343 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
344 _mesa_key_pointer_equal
);
346 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
347 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
348 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
349 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
350 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
354 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
355 si_destroy_context(&sctx
->b
.b
);
359 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
360 void *priv
, unsigned flags
)
362 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
363 struct pipe_context
*ctx
= si_create_context(screen
, flags
);
365 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
368 /* Clover (compute-only) is unsupported.
370 * Since the threaded context creates shader states from the non-driver
371 * thread, asynchronous compilation is required for create_{shader}_-
372 * state not to use pipe_context. Debug contexts (ddebug) disable
373 * asynchronous compilation, so don't use the threaded context with
376 if (flags
& (PIPE_CONTEXT_COMPUTE_ONLY
| PIPE_CONTEXT_DEBUG
))
379 /* When shaders are logged to stderr, asynchronous compilation is
381 if (sscreen
->b
.debug_flags
& (DBG_VS
| DBG_TCS
| DBG_TES
| DBG_GS
|
385 return threaded_context_create(ctx
, &sscreen
->b
.pool_transfers
,
386 r600_replace_buffer_storage
,
387 &((struct si_context
*)ctx
)->b
.tc
);
393 static bool si_have_tgsi_compute(struct si_screen
*sscreen
)
395 /* Old kernels disallowed some register writes for SI
396 * that are used for indirect dispatches. */
397 return (sscreen
->b
.chip_class
>= CIK
||
398 sscreen
->b
.info
.drm_major
== 3 ||
399 (sscreen
->b
.info
.drm_major
== 2 &&
400 sscreen
->b
.info
.drm_minor
>= 45));
403 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
405 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
408 /* Supported features (boolean caps). */
409 case PIPE_CAP_ACCELERATED
:
410 case PIPE_CAP_TWO_SIDED_STENCIL
:
411 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
412 case PIPE_CAP_ANISOTROPIC_FILTER
:
413 case PIPE_CAP_POINT_SPRITE
:
414 case PIPE_CAP_OCCLUSION_QUERY
:
415 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
416 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
417 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
418 case PIPE_CAP_TEXTURE_SWIZZLE
:
419 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
420 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
421 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
422 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
423 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
424 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
425 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
427 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
428 case PIPE_CAP_PRIMITIVE_RESTART
:
429 case PIPE_CAP_CONDITIONAL_RENDER
:
430 case PIPE_CAP_TEXTURE_BARRIER
:
431 case PIPE_CAP_INDEP_BLEND_ENABLE
:
432 case PIPE_CAP_INDEP_BLEND_FUNC
:
433 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
434 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
435 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
436 case PIPE_CAP_START_INSTANCE
:
437 case PIPE_CAP_NPOT_TEXTURES
:
438 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
439 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
440 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
441 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
442 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
443 case PIPE_CAP_TGSI_INSTANCEID
:
444 case PIPE_CAP_COMPUTE
:
445 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
446 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
447 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
448 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
449 case PIPE_CAP_CUBE_MAP_ARRAY
:
450 case PIPE_CAP_SAMPLE_SHADING
:
451 case PIPE_CAP_DRAW_INDIRECT
:
452 case PIPE_CAP_CLIP_HALFZ
:
453 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
454 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
455 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
456 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
457 case PIPE_CAP_TGSI_TEXCOORD
:
458 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
459 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
460 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
461 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
462 case PIPE_CAP_SHAREABLE_SHADERS
:
463 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
464 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
465 case PIPE_CAP_TEXTURE_QUERY_LOD
:
466 case PIPE_CAP_TEXTURE_GATHER_SM5
:
467 case PIPE_CAP_TGSI_TXQS
:
468 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
469 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
470 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
471 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
472 case PIPE_CAP_INVALIDATE_BUFFER
:
473 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
474 case PIPE_CAP_QUERY_MEMORY_INFO
:
475 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
476 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
477 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
478 case PIPE_CAP_GENERATE_MIPMAP
:
479 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
480 case PIPE_CAP_STRING_MARKER
:
481 case PIPE_CAP_CLEAR_TEXTURE
:
482 case PIPE_CAP_CULL_DISTANCE
:
483 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
484 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
485 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
486 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
487 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
488 case PIPE_CAP_DOUBLES
:
489 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
490 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
491 case PIPE_CAP_BINDLESS_TEXTURE
:
495 case PIPE_CAP_INT64_DIVMOD
:
496 case PIPE_CAP_TGSI_CLOCK
:
497 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
498 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
501 case PIPE_CAP_TGSI_VOTE
:
502 return HAVE_LLVM
>= 0x0400;
504 case PIPE_CAP_TGSI_BALLOT
:
505 return HAVE_LLVM
>= 0x0500;
507 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
508 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
510 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
511 return (sscreen
->b
.info
.drm_major
== 2 &&
512 sscreen
->b
.info
.drm_minor
>= 43) ||
513 sscreen
->b
.info
.drm_major
== 3;
515 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
516 /* 2D tiling on CIK is supported since DRM 2.35.0 */
517 return sscreen
->b
.chip_class
< CIK
||
518 (sscreen
->b
.info
.drm_major
== 2 &&
519 sscreen
->b
.info
.drm_minor
>= 35) ||
520 sscreen
->b
.info
.drm_major
== 3;
522 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
523 return R600_MAP_BUFFER_ALIGNMENT
;
525 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
526 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
527 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
528 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
529 case PIPE_CAP_MAX_VERTEX_STREAMS
:
530 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
533 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
534 if (si_have_tgsi_compute(sscreen
))
538 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
539 return MIN2(sscreen
->b
.info
.max_alloc_size
, INT_MAX
);
541 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
542 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
543 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
544 /* SI doesn't support unaligned loads.
545 * CIK needs DRM 2.50.0 on radeon. */
546 return sscreen
->b
.chip_class
== SI
||
547 (sscreen
->b
.info
.drm_major
== 2 &&
548 sscreen
->b
.info
.drm_minor
< 50);
550 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
551 /* TODO: GFX9 hangs. */
552 if (sscreen
->b
.chip_class
>= GFX9
)
554 /* Disable on SI due to VM faults in CP DMA. Enable once these
555 * faults are mitigated in software.
557 if (sscreen
->b
.chip_class
>= CIK
&&
558 sscreen
->b
.info
.drm_major
== 3 &&
559 sscreen
->b
.info
.drm_minor
>= 13)
560 return RADEON_SPARSE_PAGE_SIZE
;
563 /* Unsupported features. */
564 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
565 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
566 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
567 case PIPE_CAP_USER_VERTEX_BUFFERS
:
568 case PIPE_CAP_FAKE_SW_MSAA
:
569 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
570 case PIPE_CAP_VERTEXID_NOBASE
:
571 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
572 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
573 case PIPE_CAP_NATIVE_FENCE_FD
:
574 case PIPE_CAP_TGSI_FS_FBFETCH
:
575 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
577 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
578 case PIPE_CAP_POST_DEPTH_COVERAGE
:
581 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
582 return si_have_tgsi_compute(sscreen
);
584 case PIPE_CAP_DRAW_PARAMETERS
:
585 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
586 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
587 return sscreen
->has_draw_indirect_multi
;
589 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
592 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
593 return sscreen
->b
.chip_class
<= VI
?
594 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
597 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
598 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
601 /* Geometry shader output. */
602 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
604 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
607 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
611 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
612 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
613 return 15; /* 16384 */
614 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
615 /* textures support 8192, but layered rendering supports 2048 */
617 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
618 /* textures support 8192, but layered rendering supports 2048 */
621 /* Viewports and render targets. */
622 case PIPE_CAP_MAX_VIEWPORTS
:
623 return R600_MAX_VIEWPORTS
;
624 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
625 case PIPE_CAP_MAX_RENDER_TARGETS
:
628 /* Timer queries, present when the clock frequency is non zero. */
629 case PIPE_CAP_QUERY_TIMESTAMP
:
630 case PIPE_CAP_QUERY_TIME_ELAPSED
:
631 return sscreen
->b
.info
.clock_crystal_freq
!= 0;
633 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
634 case PIPE_CAP_MIN_TEXEL_OFFSET
:
637 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
638 case PIPE_CAP_MAX_TEXEL_OFFSET
:
641 case PIPE_CAP_ENDIANNESS
:
642 return PIPE_ENDIAN_LITTLE
;
644 case PIPE_CAP_VENDOR_ID
:
645 return ATI_VENDOR_ID
;
646 case PIPE_CAP_DEVICE_ID
:
647 return sscreen
->b
.info
.pci_id
;
648 case PIPE_CAP_VIDEO_MEMORY
:
649 return sscreen
->b
.info
.vram_size
>> 20;
650 case PIPE_CAP_PCI_GROUP
:
651 return sscreen
->b
.info
.pci_domain
;
652 case PIPE_CAP_PCI_BUS
:
653 return sscreen
->b
.info
.pci_bus
;
654 case PIPE_CAP_PCI_DEVICE
:
655 return sscreen
->b
.info
.pci_dev
;
656 case PIPE_CAP_PCI_FUNCTION
:
657 return sscreen
->b
.info
.pci_func
;
662 static int si_get_shader_param(struct pipe_screen
* pscreen
,
663 enum pipe_shader_type shader
,
664 enum pipe_shader_cap param
)
666 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
670 case PIPE_SHADER_FRAGMENT
:
671 case PIPE_SHADER_VERTEX
:
672 case PIPE_SHADER_GEOMETRY
:
673 case PIPE_SHADER_TESS_CTRL
:
674 case PIPE_SHADER_TESS_EVAL
:
676 case PIPE_SHADER_COMPUTE
:
678 case PIPE_SHADER_CAP_PREFERRED_IR
:
679 return PIPE_SHADER_IR_NATIVE
;
681 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
682 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
684 if (si_have_tgsi_compute(sscreen
))
685 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
690 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
691 uint64_t max_const_buffer_size
;
692 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
693 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
694 &max_const_buffer_size
);
695 return MIN2(max_const_buffer_size
, INT_MAX
);
698 /* If compute shaders don't require a special value
699 * for this cap, we can return the same value we
700 * do for other shader types. */
710 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
711 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
712 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
713 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
714 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
716 case PIPE_SHADER_CAP_MAX_INPUTS
:
717 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
718 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
719 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
720 case PIPE_SHADER_CAP_MAX_TEMPS
:
721 return 256; /* Max native temporaries. */
722 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
723 return 4096 * sizeof(float[4]); /* actually only memory limits this */
724 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
725 return SI_NUM_CONST_BUFFERS
;
726 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
727 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
728 return SI_NUM_SAMPLERS
;
729 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
730 return SI_NUM_SHADER_BUFFERS
;
731 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
732 return SI_NUM_IMAGES
;
733 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
735 case PIPE_SHADER_CAP_PREFERRED_IR
:
736 return PIPE_SHADER_IR_TGSI
;
737 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
740 /* Supported boolean features. */
741 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
742 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
743 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
744 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
745 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
746 case PIPE_SHADER_CAP_INTEGERS
:
747 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
748 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
749 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
752 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
753 /* TODO: Indirection of geometry shader input dimension is not
756 return shader
!= PIPE_SHADER_GEOMETRY
;
758 /* Unsupported boolean features. */
759 case PIPE_SHADER_CAP_SUBROUTINES
:
760 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
761 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
762 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
768 static void si_destroy_screen(struct pipe_screen
* pscreen
)
770 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
771 struct si_shader_part
*parts
[] = {
773 sscreen
->tcs_epilogs
,
780 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
783 util_queue_destroy(&sscreen
->shader_compiler_queue
);
784 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
786 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm
); i
++)
788 LLVMDisposeTargetMachine(sscreen
->tm
[i
]);
790 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm_low_priority
); i
++)
791 if (sscreen
->tm_low_priority
[i
])
792 LLVMDisposeTargetMachine(sscreen
->tm_low_priority
[i
]);
794 /* Free shader parts. */
795 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
797 struct si_shader_part
*part
= parts
[i
];
799 parts
[i
] = part
->next
;
800 radeon_shader_binary_clean(&part
->binary
);
804 mtx_destroy(&sscreen
->shader_parts_mutex
);
805 si_destroy_shader_cache(sscreen
);
806 r600_destroy_common_screen(&sscreen
->b
);
809 static bool si_init_gs_info(struct si_screen
*sscreen
)
811 switch (sscreen
->b
.family
) {
820 sscreen
->gs_table_depth
= 16;
834 sscreen
->gs_table_depth
= 32;
841 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
843 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
849 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
850 if (!strcmp(family
, r600_get_llvm_processor_name(i
))) {
851 /* Override family and chip_class. */
852 sscreen
->b
.family
= sscreen
->b
.info
.family
= i
;
854 if (i
>= CHIP_VEGA10
)
855 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= GFX9
;
856 else if (i
>= CHIP_TONGA
)
857 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= VI
;
858 else if (i
>= CHIP_BONAIRE
)
859 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= CIK
;
861 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= SI
;
863 /* Don't submit any IBs. */
864 setenv("RADEON_NOOP", "1", 1);
869 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
873 static void si_test_vmfault(struct si_screen
*sscreen
)
875 struct pipe_context
*ctx
= sscreen
->b
.aux_context
;
876 struct si_context
*sctx
= (struct si_context
*)ctx
;
877 struct pipe_resource
*buf
=
878 pipe_buffer_create(&sscreen
->b
.b
, 0, PIPE_USAGE_DEFAULT
, 64);
881 puts("Buffer allocation failed.");
885 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
887 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_CP
) {
888 si_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0);
889 ctx
->flush(ctx
, NULL
, 0);
890 puts("VM fault test: CP - done.");
892 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_SDMA
) {
893 sctx
->b
.dma_clear_buffer(ctx
, buf
, 0, 4, 0);
894 ctx
->flush(ctx
, NULL
, 0);
895 puts("VM fault test: SDMA - done.");
897 if (sscreen
->b
.debug_flags
& DBG_TEST_VMFAULT_SHADER
) {
898 util_test_constant_buffer(ctx
, buf
);
899 puts("VM fault test: Shader - done.");
904 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
906 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
907 unsigned num_threads
, num_compiler_threads
, num_compiler_threads_lowprio
, i
;
913 /* Set functions first. */
914 sscreen
->b
.b
.context_create
= si_pipe_create_context
;
915 sscreen
->b
.b
.destroy
= si_destroy_screen
;
916 sscreen
->b
.b
.get_param
= si_get_param
;
917 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
918 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
920 si_init_screen_state_functions(sscreen
);
922 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
923 !si_init_gs_info(sscreen
) ||
924 !si_init_shader_cache(sscreen
)) {
929 /* Only enable as many threads as we have target machines, but at most
930 * the number of CPUs - 1 if there is more than one.
932 num_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
933 num_threads
= MAX2(1, num_threads
- 1);
934 num_compiler_threads
= MIN2(num_threads
, ARRAY_SIZE(sscreen
->tm
));
935 num_compiler_threads_lowprio
=
936 MIN2(num_threads
, ARRAY_SIZE(sscreen
->tm_low_priority
));
938 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "si_shader",
939 32, num_compiler_threads
, 0)) {
940 si_destroy_shader_cache(sscreen
);
945 /* The queue must be large enough so that adding optimized shaders
946 * doesn't stall draw calls when the queue is full. Especially varying
947 * packing generates a very high volume of optimized shader compilation
950 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
952 1024, num_compiler_threads
,
953 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
954 si_destroy_shader_cache(sscreen
);
959 si_handle_env_var_force_family(sscreen
);
961 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
962 si_init_perfcounters(sscreen
);
964 /* Hawaii has a bug with offchip buffers > 256 that can be worked
965 * around by setting 4K granularity.
967 sscreen
->tess_offchip_block_dw_size
=
968 sscreen
->b
.family
== CHIP_HAWAII
? 4096 : 8192;
970 sscreen
->has_distributed_tess
=
971 sscreen
->b
.chip_class
>= VI
&&
972 sscreen
->b
.info
.max_se
>= 2;
974 sscreen
->has_draw_indirect_multi
=
975 (sscreen
->b
.family
>= CHIP_POLARIS10
) ||
976 (sscreen
->b
.chip_class
== VI
&&
977 sscreen
->b
.info
.pfp_fw_version
>= 121 &&
978 sscreen
->b
.info
.me_fw_version
>= 87) ||
979 (sscreen
->b
.chip_class
== CIK
&&
980 sscreen
->b
.info
.pfp_fw_version
>= 211 &&
981 sscreen
->b
.info
.me_fw_version
>= 173) ||
982 (sscreen
->b
.chip_class
== SI
&&
983 sscreen
->b
.info
.pfp_fw_version
>= 121 &&
984 sscreen
->b
.info
.me_fw_version
>= 87);
986 sscreen
->has_ds_bpermute
= sscreen
->b
.chip_class
>= VI
;
987 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->b
.family
>= CHIP_POLARIS10
&&
988 sscreen
->b
.family
<= CHIP_POLARIS12
) ||
989 sscreen
->b
.family
== CHIP_VEGA10
||
990 sscreen
->b
.family
== CHIP_RAVEN
;
992 sscreen
->b
.has_cp_dma
= true;
993 sscreen
->b
.has_streamout
= true;
995 /* Some chips have RB+ registers, but don't support RB+. Those must
998 if (sscreen
->b
.family
== CHIP_STONEY
||
999 sscreen
->b
.chip_class
>= GFX9
) {
1000 sscreen
->b
.has_rbplus
= true;
1002 sscreen
->b
.rbplus_allowed
=
1003 !(sscreen
->b
.debug_flags
& DBG_NO_RB_PLUS
) &&
1004 (sscreen
->b
.family
== CHIP_STONEY
||
1005 sscreen
->b
.family
== CHIP_RAVEN
);
1008 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1009 sscreen
->use_monolithic_shaders
=
1010 (sscreen
->b
.debug_flags
& DBG_MONOLITHIC_SHADERS
) != 0;
1012 sscreen
->b
.barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
1013 SI_CONTEXT_INV_VMEM_L1
;
1014 if (sscreen
->b
.chip_class
<= VI
)
1015 sscreen
->b
.barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_GLOBAL_L2
;
1017 sscreen
->b
.barrier_flags
.compute_to_L2
= SI_CONTEXT_CS_PARTIAL_FLUSH
;
1019 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1020 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
1022 for (i
= 0; i
< num_compiler_threads
; i
++)
1023 sscreen
->tm
[i
] = si_create_llvm_target_machine(sscreen
);
1024 for (i
= 0; i
< num_compiler_threads_lowprio
; i
++)
1025 sscreen
->tm_low_priority
[i
] = si_create_llvm_target_machine(sscreen
);
1027 /* Create the auxiliary context. This must be done last. */
1028 sscreen
->b
.aux_context
= si_create_context(&sscreen
->b
.b
, 0);
1030 if (sscreen
->b
.debug_flags
& DBG_TEST_DMA
)
1031 r600_test_dma(&sscreen
->b
);
1033 if (sscreen
->b
.debug_flags
& (DBG_TEST_VMFAULT_CP
|
1034 DBG_TEST_VMFAULT_SDMA
|
1035 DBG_TEST_VMFAULT_SHADER
))
1036 si_test_vmfault(sscreen
);
1038 return &sscreen
->b
.b
;