src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_table, NULL);
  48         r600_resource_reference(&sctx->scratch_buffer, NULL);
  49         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  50
  51         si_pm4_free_state(sctx, sctx->init_config, ~0);
  52         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  53         si_pm4_delete_state(sctx, tf_ring, sctx->tf_state);
  54         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  55                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  56
  57         if (sctx->pstipple_sampler_state)
  58                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  59         if (sctx->dummy_pixel_shader) {
  60                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  61         }
  62         if (sctx->fixed_func_tcs_shader)
  63                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader);
  64         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  65         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  66         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  67         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  68         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  69
  70         util_blitter_destroy(sctx->blitter);
  71
  72         si_pm4_cleanup(sctx);
  73
  74         r600_common_context_cleanup(&sctx->b);
  75
  76 #if HAVE_LLVM >= 0x0306
  77         LLVMDisposeTargetMachine(sctx->tm);
  78 #endif
  79
  80         FREE(sctx);
  81 }
  82
  83 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  84 {
  85         struct si_context *sctx = CALLOC_STRUCT(si_context);
  86         struct si_screen* sscreen = (struct si_screen *)screen;
  87         struct radeon_winsys *ws = sscreen->b.ws;
  88         LLVMTargetRef r600_target;
  89 #if HAVE_LLVM >= 0x0306
  90         const char *triple = "amdgcn--";
  91 #endif
  92         int shader, i;
  93
  94         if (sctx == NULL)
  95                 return NULL;
  96
  97         sctx->b.b.screen = screen; /* this must be set first */
  98         sctx->b.b.priv = priv;
  99         sctx->b.b.destroy = si_destroy_context;
 100         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 101
 102         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 103                 goto fail;
 104
 105         si_init_blit_functions(sctx);
 106         si_init_compute_functions(sctx);
 107
 108         if (sscreen->b.info.has_uvd) {
 109                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 110                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 111         } else {
 112                 sctx->b.b.create_video_codec = vl_create_decoder;
 113                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 114         }
 115
 116         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
 117                                              sctx, sscreen->b.trace_bo ?
 118                                                 sscreen->b.trace_bo->cs_buf : NULL);
 119         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 120
 121         si_init_all_descriptors(sctx);
 122
 123         /* Initialize cache_flush. */
 124         sctx->cache_flush = si_atom_cache_flush;
 125         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 126
 127         sctx->msaa_sample_locs = si_atom_msaa_sample_locs;
 128         sctx->atoms.s.msaa_sample_locs = &sctx->msaa_sample_locs;
 129
 130         sctx->msaa_config = si_atom_msaa_config;
 131         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 132
 133         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 134         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 135
 136         si_init_state_functions(sctx);
 137         si_init_shader_functions(sctx);
 138
 139         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 140                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 141
 142         sctx->blitter = util_blitter_create(&sctx->b.b);
 143         if (sctx->blitter == NULL)
 144                 goto fail;
 145         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 146
 147         /* these must be last */
 148         si_begin_new_cs(sctx);
 149         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 150
 151         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 152          * with a NULL buffer). We need to use a dummy buffer instead. */
 153         if (sctx->b.chip_class == CIK) {
 154                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 155                                                                  PIPE_USAGE_DEFAULT, 16);
 156                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 157
 158                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 159                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 160                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 161                                                               &sctx->null_const_buf);
 162                         }
 163                 }
 164
 165                 /* Clear the NULL constant buffer, because loads should return zeros. */
 166                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 167                                      sctx->null_const_buf.buffer->width0, 0, false);
 168         }
 169
 170         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 171          * this for non-cs shaders.  Using the wrong value here can result in
 172          * GPU lockups, but the maximum value seems to always work.
 173          */
 174         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 175
 176 #if HAVE_LLVM >= 0x0306
 177         /* Initialize LLVM TargetMachine */
 178         r600_target = radeon_llvm_get_r600_target(triple);
 179         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 180                                            r600_get_llvm_processor_name(sscreen->b.family),
 181                                            "+DumpCode,+vgpr-spilling",
 182                                            LLVMCodeGenLevelDefault,
 183                                            LLVMRelocDefault,
 184                                            LLVMCodeModelDefault);
 185 #endif
 186
 187         return &sctx->b.b;
 188 fail:
 189         si_destroy_context(&sctx->b.b);
 190         return NULL;
 191 }
 192
 193 /*
 194  * pipe_screen
 195  */
 196
 197 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 198 {
 199         struct si_screen *sscreen = (struct si_screen *)pscreen;
 200
 201         switch (param) {
 202         /* Supported features (boolean caps). */
 203         case PIPE_CAP_TWO_SIDED_STENCIL:
 204         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 205         case PIPE_CAP_ANISOTROPIC_FILTER:
 206         case PIPE_CAP_POINT_SPRITE:
 207         case PIPE_CAP_OCCLUSION_QUERY:
 208         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 209         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 210         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 211         case PIPE_CAP_TEXTURE_SWIZZLE:
 212         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 213         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 214         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 215         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 216         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 217         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 218         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 219         case PIPE_CAP_SM3:
 220         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 221         case PIPE_CAP_PRIMITIVE_RESTART:
 222         case PIPE_CAP_CONDITIONAL_RENDER:
 223         case PIPE_CAP_TEXTURE_BARRIER:
 224         case PIPE_CAP_INDEP_BLEND_ENABLE:
 225         case PIPE_CAP_INDEP_BLEND_FUNC:
 226         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 227         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 228         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 229         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 230         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 231         case PIPE_CAP_USER_INDEX_BUFFERS:
 232         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 233         case PIPE_CAP_START_INSTANCE:
 234         case PIPE_CAP_NPOT_TEXTURES:
 235         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 236         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 237         case PIPE_CAP_TGSI_INSTANCEID:
 238         case PIPE_CAP_COMPUTE:
 239         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 240         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 241         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 242         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 243         case PIPE_CAP_CUBE_MAP_ARRAY:
 244         case PIPE_CAP_SAMPLE_SHADING:
 245         case PIPE_CAP_DRAW_INDIRECT:
 246         case PIPE_CAP_CLIP_HALFZ:
 247         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 248         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 249         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 250         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 251         case PIPE_CAP_TGSI_TEXCOORD:
 252                 return 1;
 253
 254         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 255                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 256
 257         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 258                 return sscreen->b.info.drm_major == 2 && sscreen->b.info.drm_minor >= 43;
 259
 260         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 261                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 262                 return sscreen->b.chip_class < CIK ||
 263                        sscreen->b.info.drm_minor >= 35;
 264
 265         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 266                 return R600_MAP_BUFFER_ALIGNMENT;
 267
 268         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 269         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 270                 return 4;
 271
 272         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 273                 return 330;
 274
 275         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 276                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 277
 278         case PIPE_CAP_TEXTURE_QUERY_LOD:
 279         case PIPE_CAP_TEXTURE_GATHER_SM5:
 280                 return HAVE_LLVM >= 0x0305;
 281         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 282                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 283
 284         /* Unsupported features. */
 285         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 286         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 287         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 288         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 289         case PIPE_CAP_USER_VERTEX_BUFFERS:
 290         case PIPE_CAP_FAKE_SW_MSAA:
 291         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 292         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 293         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 294         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 295         case PIPE_CAP_VERTEXID_NOBASE:
 296         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 297                 return 0;
 298
 299         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 300                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 301
 302         /* Stream output. */
 303         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 304                 return sscreen->b.has_streamout ? 4 : 0;
 305         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 306                 return sscreen->b.has_streamout ? 1 : 0;
 307         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 308         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 309                 return sscreen->b.has_streamout ? 32*4 : 0;
 310
 311         /* Geometry shader output. */
 312         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 313                 return 1024;
 314         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 315                 return 4095;
 316         case PIPE_CAP_MAX_VERTEX_STREAMS:
 317                 return 1;
 318
 319         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 320                 return 2048;
 321
 322         /* Texturing. */
 323         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 324         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 325                 return 15; /* 16384 */
 326         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 327                 /* textures support 8192, but layered rendering supports 2048 */
 328                 return 12;
 329         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 330                 /* textures support 8192, but layered rendering supports 2048 */
 331                 return 2048;
 332
 333         /* Render targets. */
 334         case PIPE_CAP_MAX_RENDER_TARGETS:
 335                 return 8;
 336
 337         case PIPE_CAP_MAX_VIEWPORTS:
 338                 return 16;
 339
 340         /* Timer queries, present when the clock frequency is non zero. */
 341         case PIPE_CAP_QUERY_TIMESTAMP:
 342         case PIPE_CAP_QUERY_TIME_ELAPSED:
 343                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 344
 345         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 346         case PIPE_CAP_MIN_TEXEL_OFFSET:
 347                 return -32;
 348
 349         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 350         case PIPE_CAP_MAX_TEXEL_OFFSET:
 351                 return 31;
 352
 353         case PIPE_CAP_ENDIANNESS:
 354                 return PIPE_ENDIAN_LITTLE;
 355
 356         case PIPE_CAP_VENDOR_ID:
 357                 return 0x1002;
 358         case PIPE_CAP_DEVICE_ID:
 359                 return sscreen->b.info.pci_id;
 360         case PIPE_CAP_ACCELERATED:
 361                 return 1;
 362         case PIPE_CAP_VIDEO_MEMORY:
 363                 return sscreen->b.info.vram_size >> 20;
 364         case PIPE_CAP_UMA:
 365                 return 0;
 366         }
 367         return 0;
 368 }
 369
 370 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 371 {
 372         switch(shader)
 373         {
 374         case PIPE_SHADER_FRAGMENT:
 375         case PIPE_SHADER_VERTEX:
 376         case PIPE_SHADER_GEOMETRY:
 377                 break;
 378         case PIPE_SHADER_COMPUTE:
 379                 switch (param) {
 380                 case PIPE_SHADER_CAP_PREFERRED_IR:
 381 #if HAVE_LLVM < 0x0306
 382                         return PIPE_SHADER_IR_LLVM;
 383 #else
 384                         return PIPE_SHADER_IR_NATIVE;
 385 #endif
 386                 case PIPE_SHADER_CAP_DOUBLES:
 387                         return HAVE_LLVM >= 0x0307;
 388
 389                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 390                         uint64_t max_const_buffer_size;
 391                         pscreen->get_compute_param(pscreen,
 392                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 393                                 &max_const_buffer_size);
 394                         return max_const_buffer_size;
 395                 }
 396                 default:
 397                         /* If compute shaders don't require a special value
 398                          * for this cap, we can return the same value we
 399                          * do for other shader types. */
 400                         break;
 401                 }
 402                 break;
 403         default:
 404                 /* TODO: support tessellation */
 405                 return 0;
 406         }
 407
 408         switch (param) {
 409         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 410         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 411         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 412         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 413                 return 16384;
 414         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 415                 return 32;
 416         case PIPE_SHADER_CAP_MAX_INPUTS:
 417                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 418         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 419                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 420         case PIPE_SHADER_CAP_MAX_TEMPS:
 421                 return 256; /* Max native temporaries. */
 422         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 423                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 424         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 425                 return SI_NUM_USER_CONST_BUFFERS;
 426         case PIPE_SHADER_CAP_MAX_PREDS:
 427                 return 0; /* FIXME */
 428         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 429                 return 1;
 430         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 431                 return 1;
 432         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 433                 /* Indirection of geometry shader input dimension is not
 434                  * handled yet
 435                  */
 436                 return shader < PIPE_SHADER_GEOMETRY;
 437         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 438         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 439         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 440                 return 1;
 441         case PIPE_SHADER_CAP_INTEGERS:
 442                 return 1;
 443         case PIPE_SHADER_CAP_SUBROUTINES:
 444                 return 0;
 445         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 446         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 447                 return 16;
 448         case PIPE_SHADER_CAP_PREFERRED_IR:
 449                 return PIPE_SHADER_IR_TGSI;
 450         case PIPE_SHADER_CAP_DOUBLES:
 451                 return HAVE_LLVM >= 0x0307;
 452         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 453         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 454                 return 0;
 455         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 456         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 457                 return 1;
 458         }
 459         return 0;
 460 }
 461
 462 static void si_destroy_screen(struct pipe_screen* pscreen)
 463 {
 464         struct si_screen *sscreen = (struct si_screen *)pscreen;
 465
 466         if (sscreen == NULL)
 467                 return;
 468
 469         if (!sscreen->b.ws->unref(sscreen->b.ws))
 470                 return;
 471
 472         r600_destroy_common_screen(&sscreen->b);
 473 }
 474
 475 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 476
 477 /* Initialize pipe config. This is especially important for GPUs
 478  * with 16 pipes and more where it's initialized incorrectly by
 479  * the TILING_CONFIG ioctl. */
 480 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 481 {
 482         unsigned mode2d;
 483
 484         /* This is okay, because there can be no 2D tiling without
 485          * the tile mode array, so we won't need the pipe config.
 486          * Return "success".
 487          */
 488         if (!sscreen->b.info.si_tile_mode_array_valid)
 489                 return true;
 490
 491         /* The same index is used for the 2D mode on CIK too. */
 492         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 493
 494         switch (G_009910_PIPE_CONFIG(mode2d)) {
 495         case V_02803C_ADDR_SURF_P2:
 496                 sscreen->b.tiling_info.num_channels = 2;
 497                 break;
 498         case V_02803C_X_ADDR_SURF_P4_8X16:
 499         case V_02803C_X_ADDR_SURF_P4_16X16:
 500         case V_02803C_X_ADDR_SURF_P4_16X32:
 501         case V_02803C_X_ADDR_SURF_P4_32X32:
 502                 sscreen->b.tiling_info.num_channels = 4;
 503                 break;
 504         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 505         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 506         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 507         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 508         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 509         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 510         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 511                 sscreen->b.tiling_info.num_channels = 8;
 512                 break;
 513         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 514         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 515                 sscreen->b.tiling_info.num_channels = 16;
 516                 break;
 517         default:
 518                 assert(0);
 519                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 520                         G_009910_PIPE_CONFIG(mode2d));
 521                 return false;
 522         }
 523         return true;
 524 }
 525
 526 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 527 {
 528         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 529
 530         if (sscreen == NULL) {
 531                 return NULL;
 532         }
 533
 534         /* Set functions first. */
 535         sscreen->b.b.context_create = si_create_context;
 536         sscreen->b.b.destroy = si_destroy_screen;
 537         sscreen->b.b.get_param = si_get_param;
 538         sscreen->b.b.get_shader_param = si_get_shader_param;
 539         sscreen->b.b.is_format_supported = si_is_format_supported;
 540         sscreen->b.b.resource_create = r600_resource_create_common;
 541
 542         if (!r600_common_screen_init(&sscreen->b, ws) ||
 543             !si_initialize_pipe_config(sscreen)) {
 544                 FREE(sscreen);
 545                 return NULL;
 546         }
 547
 548         sscreen->b.has_cp_dma = true;
 549         sscreen->b.has_streamout = true;
 550
 551         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 552                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 553
 554         /* Create the auxiliary context. This must be done last. */
 555         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 556
 557         return &sscreen->b.b;
 558 }