2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
26 #include "si_shader_internal.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/u_memory.h"
31 #include "util/u_suballoc.h"
32 #include "vl/vl_decoder.h"
33 #include "../ddebug/dd_util.h"
35 #define SI_LLVM_DEFAULT_FEATURES \
36 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals,-xnack"
41 static void si_destroy_context(struct pipe_context
*context
)
43 struct si_context
*sctx
= (struct si_context
*)context
;
46 /* Unreference the framebuffer normally to disable related logic
49 struct pipe_framebuffer_state fb
= {};
50 context
->set_framebuffer_state(context
, &fb
);
52 si_release_all_descriptors(sctx
);
54 if (sctx
->ce_suballocator
)
55 u_suballocator_destroy(sctx
->ce_suballocator
);
57 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
58 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
59 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
60 pipe_resource_reference(&sctx
->tess_offchip_ring
, NULL
);
61 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
62 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
63 free(sctx
->border_color_table
);
64 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
65 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
67 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
68 if (sctx
->init_config_gs_rings
)
69 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
70 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
71 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
73 if (sctx
->fixed_func_tcs_shader
.cso
)
74 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
.cso
);
75 if (sctx
->custom_dsa_flush
)
76 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
77 if (sctx
->custom_blend_resolve
)
78 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
79 if (sctx
->custom_blend_decompress
)
80 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
81 if (sctx
->custom_blend_fastclear
)
82 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fastclear
);
83 if (sctx
->custom_blend_dcc_decompress
)
84 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_dcc_decompress
);
87 util_blitter_destroy(sctx
->blitter
);
89 r600_common_context_cleanup(&sctx
->b
);
91 LLVMDisposeTargetMachine(sctx
->tm
);
93 r600_resource_reference(&sctx
->trace_buf
, NULL
);
94 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
95 radeon_clear_saved_cs(&sctx
->last_gfx
);
100 static enum pipe_reset_status
101 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
103 struct si_context
*sctx
= (struct si_context
*)ctx
;
105 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
108 /* Apitrace profiling:
109 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
110 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
111 * and remember its number.
112 * 3) In Mesa, enable queries and performance counters around that draw
113 * call and print the results.
114 * 4) glretrace --benchmark --markers ..
116 static void si_emit_string_marker(struct pipe_context
*ctx
,
117 const char *string
, int len
)
119 struct si_context
*sctx
= (struct si_context
*)ctx
;
121 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
124 static LLVMTargetMachineRef
125 si_create_llvm_target_machine(struct si_screen
*sscreen
)
127 const char *triple
= "amdgcn--";
129 return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple
), triple
,
130 r600_get_llvm_processor_name(sscreen
->b
.family
),
131 #if HAVE_LLVM >= 0x0308
132 sscreen
->b
.debug_flags
& DBG_SI_SCHED
?
133 SI_LLVM_DEFAULT_FEATURES
",+si-scheduler" :
135 SI_LLVM_DEFAULT_FEATURES
,
136 LLVMCodeGenLevelDefault
,
138 LLVMCodeModelDefault
);
141 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
142 void *priv
, unsigned flags
)
144 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
145 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
146 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
152 if (sscreen
->b
.debug_flags
& DBG_CHECK_VM
)
153 flags
|= PIPE_CONTEXT_DEBUG
;
155 if (flags
& PIPE_CONTEXT_DEBUG
)
156 sscreen
->record_llvm_ir
= true; /* racy but not critical */
158 sctx
->b
.b
.screen
= screen
; /* this must be set first */
159 sctx
->b
.b
.priv
= priv
;
160 sctx
->b
.b
.destroy
= si_destroy_context
;
161 sctx
->b
.b
.emit_string_marker
= si_emit_string_marker
;
162 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
163 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
164 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
166 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
, flags
))
169 if (sscreen
->b
.info
.drm_major
== 3)
170 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
172 si_init_blit_functions(sctx
);
173 si_init_compute_functions(sctx
);
174 si_init_cp_dma_functions(sctx
);
175 si_init_debug_functions(sctx
);
177 if (sscreen
->b
.info
.has_uvd
) {
178 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
179 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
181 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
182 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
185 sctx
->b
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
,
186 si_context_gfx_flush
, sctx
);
188 /* SI + AMDGPU + CE = GPU hang */
189 if (!(sscreen
->b
.debug_flags
& DBG_NO_CE
) && ws
->cs_add_const_ib
&&
190 sscreen
->b
.chip_class
!= SI
) {
191 sctx
->ce_ib
= ws
->cs_add_const_ib(sctx
->b
.gfx
.cs
);
195 if (ws
->cs_add_const_preamble_ib
) {
196 sctx
->ce_preamble_ib
=
197 ws
->cs_add_const_preamble_ib(sctx
->b
.gfx
.cs
);
199 if (!sctx
->ce_preamble_ib
)
203 sctx
->ce_suballocator
=
204 u_suballocator_create(&sctx
->b
.b
, 1024 * 1024,
205 0, PIPE_USAGE_DEFAULT
, false);
206 if (!sctx
->ce_suballocator
)
210 sctx
->b
.gfx
.flush
= si_context_gfx_flush
;
213 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
214 sizeof(*sctx
->border_color_table
));
215 if (!sctx
->border_color_table
)
218 sctx
->border_color_buffer
= (struct r600_resource
*)
219 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
220 SI_MAX_BORDER_COLORS
*
221 sizeof(*sctx
->border_color_table
));
222 if (!sctx
->border_color_buffer
)
225 sctx
->border_color_map
=
226 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
227 NULL
, PIPE_TRANSFER_WRITE
);
228 if (!sctx
->border_color_map
)
231 si_init_all_descriptors(sctx
);
232 si_init_state_functions(sctx
);
233 si_init_shader_functions(sctx
);
235 if (sctx
->b
.chip_class
>= CIK
)
236 cik_init_sdma_functions(sctx
);
238 si_init_dma_functions(sctx
);
240 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
241 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
243 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
244 if (sctx
->blitter
== NULL
)
246 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
248 sctx
->sample_mask
.sample_mask
= 0xffff;
250 /* these must be last */
251 si_begin_new_cs(sctx
);
252 r600_query_init_backend_mask(&sctx
->b
); /* this emits commands and must be last */
254 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
255 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
256 if (sctx
->b
.chip_class
== CIK
) {
257 sctx
->null_const_buf
.buffer
= pipe_buffer_create(screen
, PIPE_BIND_CONSTANT_BUFFER
,
258 PIPE_USAGE_DEFAULT
, 16);
259 if (!sctx
->null_const_buf
.buffer
)
261 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
263 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
264 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
265 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
266 &sctx
->null_const_buf
);
270 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
271 &sctx
->null_const_buf
);
272 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
273 &sctx
->null_const_buf
);
274 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
275 &sctx
->null_const_buf
);
276 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
277 &sctx
->null_const_buf
);
279 /* Clear the NULL constant buffer, because loads should return zeros. */
280 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
281 sctx
->null_const_buf
.buffer
->width0
, 0,
282 R600_COHERENCY_SHADER
);
285 uint64_t max_threads_per_block
;
286 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
287 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
288 &max_threads_per_block
);
290 /* The maximum number of scratch waves. Scratch space isn't divided
291 * evenly between CUs. The number is only a function of the number of CUs.
292 * We can decrease the constant to decrease the scratch buffer size.
294 * sctx->scratch_waves must be >= the maximum posible size of
295 * 1 threadgroup, so that the hw doesn't hang from being unable
298 * The recommended value is 4 per CU at most. Higher numbers don't
299 * bring much benefit, but they still occupy chip resources (think
300 * async compute). I've seen ~2% performance difference between 4 and 32.
302 sctx
->scratch_waves
= MAX2(32 * sscreen
->b
.info
.num_good_compute_units
,
303 max_threads_per_block
/ 64);
305 sctx
->tm
= si_create_llvm_target_machine(sscreen
);
309 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
310 si_destroy_context(&sctx
->b
.b
);
317 static bool si_have_tgsi_compute(struct si_screen
*sscreen
)
319 /* Old kernels disallowed some register writes for SI
320 * that are used for indirect dispatches. */
321 return HAVE_LLVM
>= 0x309 &&
322 (sscreen
->b
.chip_class
>= CIK
||
323 sscreen
->b
.info
.drm_major
== 3 ||
324 (sscreen
->b
.info
.drm_major
== 2 &&
325 sscreen
->b
.info
.drm_minor
>= 45));
328 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
330 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
333 /* Supported features (boolean caps). */
334 case PIPE_CAP_TWO_SIDED_STENCIL
:
335 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
336 case PIPE_CAP_ANISOTROPIC_FILTER
:
337 case PIPE_CAP_POINT_SPRITE
:
338 case PIPE_CAP_OCCLUSION_QUERY
:
339 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
340 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
341 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
342 case PIPE_CAP_TEXTURE_SWIZZLE
:
343 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
344 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
345 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
346 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
347 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
348 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
349 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
351 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
352 case PIPE_CAP_PRIMITIVE_RESTART
:
353 case PIPE_CAP_CONDITIONAL_RENDER
:
354 case PIPE_CAP_TEXTURE_BARRIER
:
355 case PIPE_CAP_INDEP_BLEND_ENABLE
:
356 case PIPE_CAP_INDEP_BLEND_FUNC
:
357 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
358 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
359 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
360 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
361 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
362 case PIPE_CAP_USER_INDEX_BUFFERS
:
363 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
364 case PIPE_CAP_START_INSTANCE
:
365 case PIPE_CAP_NPOT_TEXTURES
:
366 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
367 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
368 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
369 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
370 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
371 case PIPE_CAP_TGSI_INSTANCEID
:
372 case PIPE_CAP_COMPUTE
:
373 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
374 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
375 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
376 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
377 case PIPE_CAP_CUBE_MAP_ARRAY
:
378 case PIPE_CAP_SAMPLE_SHADING
:
379 case PIPE_CAP_DRAW_INDIRECT
:
380 case PIPE_CAP_CLIP_HALFZ
:
381 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
382 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
383 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
384 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
385 case PIPE_CAP_TGSI_TEXCOORD
:
386 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
387 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
388 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
389 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
390 case PIPE_CAP_SHAREABLE_SHADERS
:
391 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
392 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
393 case PIPE_CAP_TEXTURE_QUERY_LOD
:
394 case PIPE_CAP_TEXTURE_GATHER_SM5
:
395 case PIPE_CAP_TGSI_TXQS
:
396 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
397 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
398 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
399 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
400 case PIPE_CAP_INVALIDATE_BUFFER
:
401 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
402 case PIPE_CAP_QUERY_MEMORY_INFO
:
403 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
404 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
405 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
406 case PIPE_CAP_GENERATE_MIPMAP
:
407 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
408 case PIPE_CAP_STRING_MARKER
:
409 case PIPE_CAP_CLEAR_TEXTURE
:
410 case PIPE_CAP_CULL_DISTANCE
:
411 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
414 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
415 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
417 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
418 return (sscreen
->b
.info
.drm_major
== 2 &&
419 sscreen
->b
.info
.drm_minor
>= 43) ||
420 sscreen
->b
.info
.drm_major
== 3;
422 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
423 /* 2D tiling on CIK is supported since DRM 2.35.0 */
424 return sscreen
->b
.chip_class
< CIK
||
425 (sscreen
->b
.info
.drm_major
== 2 &&
426 sscreen
->b
.info
.drm_minor
>= 35) ||
427 sscreen
->b
.info
.drm_major
== 3;
429 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
430 return R600_MAP_BUFFER_ALIGNMENT
;
432 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
433 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
434 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
436 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
437 return HAVE_LLVM
>= 0x0309 ? 4 : 0;
439 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
440 if (si_have_tgsi_compute(sscreen
))
442 return HAVE_LLVM
>= 0x0309 ? 420 :
443 HAVE_LLVM
>= 0x0307 ? 410 : 330;
445 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
446 return MIN2(sscreen
->b
.info
.max_alloc_size
, INT_MAX
);
448 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
451 /* Unsupported features. */
452 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
453 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
454 case PIPE_CAP_USER_VERTEX_BUFFERS
:
455 case PIPE_CAP_FAKE_SW_MSAA
:
456 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
457 case PIPE_CAP_VERTEXID_NOBASE
:
458 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
459 case PIPE_CAP_TGSI_VOTE
:
460 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
463 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
464 return si_have_tgsi_compute(sscreen
);
466 case PIPE_CAP_DRAW_PARAMETERS
:
467 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
468 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
469 return sscreen
->has_draw_indirect_multi
;
471 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
474 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
475 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
478 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
479 return sscreen
->b
.has_streamout
? 4 : 0;
480 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
481 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
482 return sscreen
->b
.has_streamout
? 1 : 0;
483 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
484 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
485 return sscreen
->b
.has_streamout
? 32*4 : 0;
487 /* Geometry shader output. */
488 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
490 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
492 case PIPE_CAP_MAX_VERTEX_STREAMS
:
495 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
499 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
500 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
501 return 15; /* 16384 */
502 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
503 /* textures support 8192, but layered rendering supports 2048 */
505 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
506 /* textures support 8192, but layered rendering supports 2048 */
509 /* Render targets. */
510 case PIPE_CAP_MAX_RENDER_TARGETS
:
513 case PIPE_CAP_MAX_VIEWPORTS
:
514 return R600_MAX_VIEWPORTS
;
515 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
518 /* Timer queries, present when the clock frequency is non zero. */
519 case PIPE_CAP_QUERY_TIMESTAMP
:
520 case PIPE_CAP_QUERY_TIME_ELAPSED
:
521 return sscreen
->b
.info
.clock_crystal_freq
!= 0;
523 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
524 case PIPE_CAP_MIN_TEXEL_OFFSET
:
527 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
528 case PIPE_CAP_MAX_TEXEL_OFFSET
:
531 case PIPE_CAP_ENDIANNESS
:
532 return PIPE_ENDIAN_LITTLE
;
534 case PIPE_CAP_VENDOR_ID
:
535 return ATI_VENDOR_ID
;
536 case PIPE_CAP_DEVICE_ID
:
537 return sscreen
->b
.info
.pci_id
;
538 case PIPE_CAP_ACCELERATED
:
540 case PIPE_CAP_VIDEO_MEMORY
:
541 return sscreen
->b
.info
.vram_size
>> 20;
544 case PIPE_CAP_PCI_GROUP
:
545 return sscreen
->b
.info
.pci_domain
;
546 case PIPE_CAP_PCI_BUS
:
547 return sscreen
->b
.info
.pci_bus
;
548 case PIPE_CAP_PCI_DEVICE
:
549 return sscreen
->b
.info
.pci_dev
;
550 case PIPE_CAP_PCI_FUNCTION
:
551 return sscreen
->b
.info
.pci_func
;
556 static int si_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
558 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
562 case PIPE_SHADER_FRAGMENT
:
563 case PIPE_SHADER_VERTEX
:
564 case PIPE_SHADER_GEOMETRY
:
566 case PIPE_SHADER_TESS_CTRL
:
567 case PIPE_SHADER_TESS_EVAL
:
568 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
569 if (HAVE_LLVM
== 0x0306 && MESA_LLVM_VERSION_PATCH
< 2)
572 case PIPE_SHADER_COMPUTE
:
574 case PIPE_SHADER_CAP_PREFERRED_IR
:
575 return PIPE_SHADER_IR_NATIVE
;
577 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
578 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
580 if (si_have_tgsi_compute(sscreen
))
581 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
585 case PIPE_SHADER_CAP_DOUBLES
:
586 return HAVE_LLVM
>= 0x0307;
588 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
589 uint64_t max_const_buffer_size
;
590 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
591 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
592 &max_const_buffer_size
);
593 return MIN2(max_const_buffer_size
, INT_MAX
);
596 /* If compute shaders don't require a special value
597 * for this cap, we can return the same value we
598 * do for other shader types. */
608 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
609 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
610 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
611 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
612 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
614 case PIPE_SHADER_CAP_MAX_INPUTS
:
615 return shader
== PIPE_SHADER_VERTEX
? SI_NUM_VERTEX_BUFFERS
: 32;
616 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
617 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
618 case PIPE_SHADER_CAP_MAX_TEMPS
:
619 return 256; /* Max native temporaries. */
620 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
621 return 4096 * sizeof(float[4]); /* actually only memory limits this */
622 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
623 return SI_NUM_CONST_BUFFERS
;
624 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
625 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
626 return SI_NUM_SAMPLERS
;
627 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
628 return HAVE_LLVM
>= 0x0309 ? SI_NUM_SHADER_BUFFERS
: 0;
629 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
630 return HAVE_LLVM
>= 0x0309 ? SI_NUM_IMAGES
: 0;
631 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
633 case PIPE_SHADER_CAP_PREFERRED_IR
:
634 return PIPE_SHADER_IR_TGSI
;
635 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
638 /* Supported boolean features. */
639 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
640 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
641 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
642 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
643 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
644 case PIPE_SHADER_CAP_INTEGERS
:
645 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
646 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
649 case PIPE_SHADER_CAP_DOUBLES
:
650 return HAVE_LLVM
>= 0x0307;
652 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
653 /* TODO: Indirection of geometry shader input dimension is not
656 return shader
!= PIPE_SHADER_GEOMETRY
;
658 /* Unsupported boolean features. */
659 case PIPE_SHADER_CAP_MAX_PREDS
:
660 case PIPE_SHADER_CAP_SUBROUTINES
:
661 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
662 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
663 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
669 static void si_destroy_screen(struct pipe_screen
* pscreen
)
671 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
672 struct si_shader_part
*parts
[] = {
675 sscreen
->tcs_epilogs
,
685 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
688 if (util_queue_is_initialized(&sscreen
->shader_compiler_queue
))
689 util_queue_destroy(&sscreen
->shader_compiler_queue
);
691 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm
); i
++)
693 LLVMDisposeTargetMachine(sscreen
->tm
[i
]);
695 /* Free shader parts. */
696 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
698 struct si_shader_part
*part
= parts
[i
];
700 parts
[i
] = part
->next
;
701 radeon_shader_binary_clean(&part
->binary
);
705 pipe_mutex_destroy(sscreen
->shader_parts_mutex
);
706 si_destroy_shader_cache(sscreen
);
707 r600_destroy_common_screen(&sscreen
->b
);
710 static bool si_init_gs_info(struct si_screen
*sscreen
)
712 switch (sscreen
->b
.family
) {
721 sscreen
->gs_table_depth
= 16;
732 sscreen
->gs_table_depth
= 32;
739 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
741 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
747 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
748 if (!strcmp(family
, r600_get_llvm_processor_name(i
))) {
749 /* Override family and chip_class. */
750 sscreen
->b
.family
= sscreen
->b
.info
.family
= i
;
753 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= VI
;
754 else if (i
>= CHIP_BONAIRE
)
755 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= CIK
;
757 sscreen
->b
.chip_class
= sscreen
->b
.info
.chip_class
= SI
;
759 /* Don't submit any IBs. */
760 setenv("RADEON_NOOP", "1", 1);
765 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
769 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
771 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
772 unsigned num_cpus
, num_compiler_threads
, i
;
778 /* Set functions first. */
779 sscreen
->b
.b
.context_create
= si_create_context
;
780 sscreen
->b
.b
.destroy
= si_destroy_screen
;
781 sscreen
->b
.b
.get_param
= si_get_param
;
782 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
783 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
785 si_init_screen_state_functions(sscreen
);
787 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
788 !si_init_gs_info(sscreen
) ||
789 !si_init_shader_cache(sscreen
)) {
794 si_handle_env_var_force_family(sscreen
);
796 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
797 si_init_perfcounters(sscreen
);
799 /* Hawaii has a bug with offchip buffers > 256 that can be worked
800 * around by setting 4K granularity.
802 sscreen
->tess_offchip_block_dw_size
=
803 sscreen
->b
.family
== CHIP_HAWAII
? 4096 : 8192;
805 sscreen
->has_distributed_tess
=
806 sscreen
->b
.chip_class
>= VI
&&
807 sscreen
->b
.info
.max_se
>= 2;
809 sscreen
->has_draw_indirect_multi
=
810 (sscreen
->b
.family
>= CHIP_POLARIS10
) ||
811 (sscreen
->b
.chip_class
== VI
&&
812 sscreen
->b
.info
.pfp_fw_version
>= 121 &&
813 sscreen
->b
.info
.me_fw_version
>= 87) ||
814 (sscreen
->b
.chip_class
== CIK
&&
815 sscreen
->b
.info
.pfp_fw_version
>= 211 &&
816 sscreen
->b
.info
.me_fw_version
>= 173) ||
817 (sscreen
->b
.chip_class
== SI
&&
818 sscreen
->b
.info
.pfp_fw_version
>= 121 &&
819 sscreen
->b
.info
.me_fw_version
>= 87);
821 sscreen
->has_ds_bpermute
= HAVE_LLVM
>= 0x0309 &&
822 sscreen
->b
.chip_class
>= VI
;
824 sscreen
->b
.has_cp_dma
= true;
825 sscreen
->b
.has_streamout
= true;
826 pipe_mutex_init(sscreen
->shader_parts_mutex
);
827 sscreen
->use_monolithic_shaders
=
828 HAVE_LLVM
< 0x0308 ||
829 (sscreen
->b
.debug_flags
& DBG_MONOLITHIC_SHADERS
) != 0;
831 sscreen
->b
.barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
832 SI_CONTEXT_INV_VMEM_L1
|
833 SI_CONTEXT_INV_GLOBAL_L2
;
834 sscreen
->b
.barrier_flags
.compute_to_L2
= SI_CONTEXT_CS_PARTIAL_FLUSH
;
836 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
837 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
839 /* Only enable as many threads as we have target machines and CPUs. */
840 num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
841 num_compiler_threads
= MIN2(num_cpus
, ARRAY_SIZE(sscreen
->tm
));
843 for (i
= 0; i
< num_compiler_threads
; i
++)
844 sscreen
->tm
[i
] = si_create_llvm_target_machine(sscreen
);
846 util_queue_init(&sscreen
->shader_compiler_queue
, "si_shader",
847 32, num_compiler_threads
);
849 /* Create the auxiliary context. This must be done last. */
850 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
, 0);
852 if (sscreen
->b
.debug_flags
& DBG_TEST_DMA
)
853 r600_test_dma(&sscreen
->b
);
855 return &sscreen
->b
.b
;