src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_log.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_suballoc.h"
  34 #include "util/u_tests.h"
  35 #include "util/xmlconfig.h"
  36 #include "vl/vl_decoder.h"
  37 #include "../ddebug/dd_util.h"
  38
  39 #include "compiler/nir/nir.h"
  40
  41 /*
  42  * pipe_context
  43  */
  44 static void si_destroy_context(struct pipe_context *context)
  45 {
  46         struct si_context *sctx = (struct si_context *)context;
  47         int i;
  48
  49         /* Unreference the framebuffer normally to disable related logic
  50          * properly.
  51          */
  52         struct pipe_framebuffer_state fb = {};
  53         if (context->set_framebuffer_state)
  54                 context->set_framebuffer_state(context, &fb);
  55
  56         si_release_all_descriptors(sctx);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_fmask_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  83         if (sctx->custom_blend_eliminate_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87         if (sctx->vs_blit_pos)
  88                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos);
  89         if (sctx->vs_blit_pos_layered)
  90                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos_layered);
  91         if (sctx->vs_blit_color)
  92                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color);
  93         if (sctx->vs_blit_color_layered)
  94                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color_layered);
  95         if (sctx->vs_blit_texcoord)
  96                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_texcoord);
  97
  98         if (sctx->blitter)
  99                 util_blitter_destroy(sctx->blitter);
 100
 101         si_common_context_cleanup(&sctx->b);
 102
 103         LLVMDisposeTargetMachine(sctx->tm);
 104
 105         si_saved_cs_reference(&sctx->current_saved_cs, NULL);
 106
 107         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 108         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 109
 110         util_dynarray_fini(&sctx->resident_tex_handles);
 111         util_dynarray_fini(&sctx->resident_img_handles);
 112         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 113         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 114         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 115         FREE(sctx);
 116 }
 117
 118 static enum pipe_reset_status
 119 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 120 {
 121         struct si_context *sctx = (struct si_context *)ctx;
 122
 123         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 124 }
 125
 126 /* Apitrace profiling:
 127  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 128  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 129  *      and remember its number.
 130  *   3) In Mesa, enable queries and performance counters around that draw
 131  *      call and print the results.
 132  *   4) glretrace --benchmark --markers ..
 133  */
 134 static void si_emit_string_marker(struct pipe_context *ctx,
 135                                   const char *string, int len)
 136 {
 137         struct si_context *sctx = (struct si_context *)ctx;
 138
 139         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 140
 141         if (sctx->b.log)
 142                 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
 143 }
 144
 145 static LLVMTargetMachineRef
 146 si_create_llvm_target_machine(struct si_screen *sscreen)
 147 {
 148         const char *triple = "amdgcn--";
 149         char features[256];
 150
 151         snprintf(features, sizeof(features),
 152                  "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
 153                  sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
 154                  sscreen->llvm_has_working_vgpr_indexing ? "" : ",-promote-alloca",
 155                  sscreen->b.debug_flags & DBG(SI_SCHED) ? ",+si-scheduler" : "");
 156
 157         return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
 158                                        si_get_llvm_processor_name(sscreen->b.family),
 159                                        features,
 160                                        LLVMCodeGenLevelDefault,
 161                                        LLVMRelocDefault,
 162                                        LLVMCodeModelDefault);
 163 }
 164
 165 static void si_set_log_context(struct pipe_context *ctx,
 166                                struct u_log_context *log)
 167 {
 168         struct si_context *sctx = (struct si_context *)ctx;
 169         sctx->b.log = log;
 170
 171         if (log)
 172                 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
 173 }
 174
 175 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 176                                               unsigned flags)
 177 {
 178         struct si_context *sctx = CALLOC_STRUCT(si_context);
 179         struct si_screen* sscreen = (struct si_screen *)screen;
 180         struct radeon_winsys *ws = sscreen->b.ws;
 181         int shader, i;
 182
 183         if (!sctx)
 184                 return NULL;
 185
 186         if (flags & PIPE_CONTEXT_DEBUG)
 187                 sscreen->record_llvm_ir = true; /* racy but not critical */
 188
 189         sctx->b.b.screen = screen; /* this must be set first */
 190         sctx->b.b.priv = NULL;
 191         sctx->b.b.destroy = si_destroy_context;
 192         sctx->b.b.emit_string_marker = si_emit_string_marker;
 193         sctx->b.b.set_log_context = si_set_log_context;
 194         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 195         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 196         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 197
 198         if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
 199                 goto fail;
 200
 201         if (sscreen->b.info.drm_major == 3)
 202                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 203
 204         si_init_blit_functions(sctx);
 205         si_init_compute_functions(sctx);
 206         si_init_cp_dma_functions(sctx);
 207         si_init_debug_functions(sctx);
 208         si_init_msaa_functions(sctx);
 209         si_init_streamout_functions(sctx);
 210
 211         if (sscreen->b.info.has_hw_decode) {
 212                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 213                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 214         } else {
 215                 sctx->b.b.create_video_codec = vl_create_decoder;
 216                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 217         }
 218
 219         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 220                                        si_context_gfx_flush, sctx);
 221         sctx->b.gfx.flush = si_context_gfx_flush;
 222
 223         /* Border colors. */
 224         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 225                                           sizeof(*sctx->border_color_table));
 226         if (!sctx->border_color_table)
 227                 goto fail;
 228
 229         sctx->border_color_buffer = (struct r600_resource*)
 230                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 231                                    SI_MAX_BORDER_COLORS *
 232                                    sizeof(*sctx->border_color_table));
 233         if (!sctx->border_color_buffer)
 234                 goto fail;
 235
 236         sctx->border_color_map =
 237                 ws->buffer_map(sctx->border_color_buffer->buf,
 238                                NULL, PIPE_TRANSFER_WRITE);
 239         if (!sctx->border_color_map)
 240                 goto fail;
 241
 242         si_init_all_descriptors(sctx);
 243         si_init_state_functions(sctx);
 244         si_init_shader_functions(sctx);
 245         si_init_viewport_functions(sctx);
 246         si_init_ia_multi_vgt_param_table(sctx);
 247
 248         if (sctx->b.chip_class >= CIK)
 249                 cik_init_sdma_functions(sctx);
 250         else
 251                 si_init_dma_functions(sctx);
 252
 253         if (sscreen->b.debug_flags & DBG(FORCE_DMA))
 254                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 255
 256         sctx->blitter = util_blitter_create(&sctx->b.b);
 257         if (sctx->blitter == NULL)
 258                 goto fail;
 259         sctx->blitter->draw_rectangle = si_draw_rectangle;
 260         sctx->blitter->skip_viewport_restore = true;
 261
 262         sctx->sample_mask.sample_mask = 0xffff;
 263
 264         /* these must be last */
 265         si_begin_new_cs(sctx);
 266
 267         if (sctx->b.chip_class >= GFX9) {
 268                 sctx->wait_mem_scratch = (struct r600_resource*)
 269                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 270                 if (!sctx->wait_mem_scratch)
 271                         goto fail;
 272
 273                 /* Initialize the memory. */
 274                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 275                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 276                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 277                             S_370_WR_CONFIRM(1) |
 278                             S_370_ENGINE_SEL(V_370_ME));
 279                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 280                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 281                 radeon_emit(cs, sctx->wait_mem_number);
 282         }
 283
 284         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 285          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 286         if (sctx->b.chip_class == CIK) {
 287                 sctx->null_const_buf.buffer =
 288                         si_aligned_buffer_create(screen,
 289                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 290                                                    PIPE_USAGE_DEFAULT, 16,
 291                                                    sctx->screen->b.info.tcc_cache_line_size);
 292                 if (!sctx->null_const_buf.buffer)
 293                         goto fail;
 294                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 295
 296                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 297                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 298                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 299                                                               &sctx->null_const_buf);
 300                         }
 301                 }
 302
 303                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 304                                  &sctx->null_const_buf);
 305                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 306                                  &sctx->null_const_buf);
 307                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 308                                  &sctx->null_const_buf);
 309                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 310                                  &sctx->null_const_buf);
 311                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 312                                  &sctx->null_const_buf);
 313
 314                 /* Clear the NULL constant buffer, because loads should return zeros. */
 315                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 316                                      sctx->null_const_buf.buffer->width0, 0,
 317                                      R600_COHERENCY_SHADER);
 318         }
 319
 320         uint64_t max_threads_per_block;
 321         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 322                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 323                                   &max_threads_per_block);
 324
 325         /* The maximum number of scratch waves. Scratch space isn't divided
 326          * evenly between CUs. The number is only a function of the number of CUs.
 327          * We can decrease the constant to decrease the scratch buffer size.
 328          *
 329          * sctx->scratch_waves must be >= the maximum posible size of
 330          * 1 threadgroup, so that the hw doesn't hang from being unable
 331          * to start any.
 332          *
 333          * The recommended value is 4 per CU at most. Higher numbers don't
 334          * bring much benefit, but they still occupy chip resources (think
 335          * async compute). I've seen ~2% performance difference between 4 and 32.
 336          */
 337         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 338                                    max_threads_per_block / 64);
 339
 340         sctx->tm = si_create_llvm_target_machine(sscreen);
 341
 342         /* Bindless handles. */
 343         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 344                                                     _mesa_key_pointer_equal);
 345         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 346                                                     _mesa_key_pointer_equal);
 347
 348         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 349         util_dynarray_init(&sctx->resident_img_handles, NULL);
 350         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 351         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 352         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 353
 354         return &sctx->b.b;
 355 fail:
 356         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 357         si_destroy_context(&sctx->b.b);
 358         return NULL;
 359 }
 360
 361 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 362                                                    void *priv, unsigned flags)
 363 {
 364         struct si_screen *sscreen = (struct si_screen *)screen;
 365         struct pipe_context *ctx;
 366
 367         if (sscreen->b.debug_flags & DBG(CHECK_VM))
 368                 flags |= PIPE_CONTEXT_DEBUG;
 369
 370         ctx = si_create_context(screen, flags);
 371
 372         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 373                 return ctx;
 374
 375         /* Clover (compute-only) is unsupported.
 376          *
 377          * Since the threaded context creates shader states from the non-driver
 378          * thread, asynchronous compilation is required for create_{shader}_-
 379          * state not to use pipe_context. Debug contexts (ddebug) disable
 380          * asynchronous compilation, so don't use the threaded context with
 381          * those.
 382          */
 383         if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
 384                 return ctx;
 385
 386         /* When shaders are logged to stderr, asynchronous compilation is
 387          * disabled too. */
 388         if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
 389                 return ctx;
 390
 391         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 392                                        si_replace_buffer_storage,
 393                                        &((struct si_context*)ctx)->b.tc);
 394 }
 395
 396 /*
 397  * pipe_screen
 398  */
 399 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 400 {
 401         /* Old kernels disallowed some register writes for SI
 402          * that are used for indirect dispatches. */
 403         return (sscreen->b.chip_class >= CIK ||
 404                 sscreen->b.info.drm_major == 3 ||
 405                 (sscreen->b.info.drm_major == 2 &&
 406                  sscreen->b.info.drm_minor >= 45));
 407 }
 408
 409 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 410 {
 411         struct si_screen *sscreen = (struct si_screen *)pscreen;
 412
 413         switch (param) {
 414         /* Supported features (boolean caps). */
 415         case PIPE_CAP_ACCELERATED:
 416         case PIPE_CAP_TWO_SIDED_STENCIL:
 417         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 418         case PIPE_CAP_ANISOTROPIC_FILTER:
 419         case PIPE_CAP_POINT_SPRITE:
 420         case PIPE_CAP_OCCLUSION_QUERY:
 421         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 422         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 423         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 424         case PIPE_CAP_TEXTURE_SWIZZLE:
 425         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 426         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 427         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 428         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 429         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 430         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 431         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 432         case PIPE_CAP_SM3:
 433         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 434         case PIPE_CAP_PRIMITIVE_RESTART:
 435         case PIPE_CAP_CONDITIONAL_RENDER:
 436         case PIPE_CAP_TEXTURE_BARRIER:
 437         case PIPE_CAP_INDEP_BLEND_ENABLE:
 438         case PIPE_CAP_INDEP_BLEND_FUNC:
 439         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 440         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 441         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 442         case PIPE_CAP_START_INSTANCE:
 443         case PIPE_CAP_NPOT_TEXTURES:
 444         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 445         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 446         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 447         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 448         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 449         case PIPE_CAP_TGSI_INSTANCEID:
 450         case PIPE_CAP_COMPUTE:
 451         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 452         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 453         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 454         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 455         case PIPE_CAP_CUBE_MAP_ARRAY:
 456         case PIPE_CAP_SAMPLE_SHADING:
 457         case PIPE_CAP_DRAW_INDIRECT:
 458         case PIPE_CAP_CLIP_HALFZ:
 459         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 460         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 461         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 462         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 463         case PIPE_CAP_TGSI_TEXCOORD:
 464         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 465         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 466         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 467         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 468         case PIPE_CAP_SHAREABLE_SHADERS:
 469         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 470         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 471         case PIPE_CAP_TEXTURE_QUERY_LOD:
 472         case PIPE_CAP_TEXTURE_GATHER_SM5:
 473         case PIPE_CAP_TGSI_TXQS:
 474         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 475         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 476         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 477         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 478         case PIPE_CAP_INVALIDATE_BUFFER:
 479         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 480         case PIPE_CAP_QUERY_MEMORY_INFO:
 481         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 482         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 483         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 484         case PIPE_CAP_GENERATE_MIPMAP:
 485         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 486         case PIPE_CAP_STRING_MARKER:
 487         case PIPE_CAP_CLEAR_TEXTURE:
 488         case PIPE_CAP_CULL_DISTANCE:
 489         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 490         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 491         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 492         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 493         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 494         case PIPE_CAP_DOUBLES:
 495         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 496         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 497         case PIPE_CAP_BINDLESS_TEXTURE:
 498         case PIPE_CAP_QUERY_TIMESTAMP:
 499         case PIPE_CAP_QUERY_TIME_ELAPSED:
 500         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 501         case PIPE_CAP_QUERY_SO_OVERFLOW:
 502         case PIPE_CAP_MEMOBJ:
 503         case PIPE_CAP_LOAD_CONSTBUF:
 504         case PIPE_CAP_INT64:
 505         case PIPE_CAP_INT64_DIVMOD:
 506         case PIPE_CAP_TGSI_CLOCK:
 507         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 508         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 509         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 510                 return 1;
 511
 512         case PIPE_CAP_TGSI_VOTE:
 513                 return HAVE_LLVM >= 0x0400;
 514
 515         case PIPE_CAP_TGSI_BALLOT:
 516                 return HAVE_LLVM >= 0x0500;
 517
 518         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 519                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 520
 521         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 522                 return (sscreen->b.info.drm_major == 2 &&
 523                         sscreen->b.info.drm_minor >= 43) ||
 524                        sscreen->b.info.drm_major == 3;
 525
 526         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 527                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 528                 return sscreen->b.chip_class < CIK ||
 529                        (sscreen->b.info.drm_major == 2 &&
 530                         sscreen->b.info.drm_minor >= 35) ||
 531                        sscreen->b.info.drm_major == 3;
 532
 533         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 534                 return R600_MAP_BUFFER_ALIGNMENT;
 535
 536         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 537         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 538         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 539         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 540         case PIPE_CAP_MAX_VERTEX_STREAMS:
 541         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 542                 return 4;
 543
 544         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 545                 if (sscreen->b.debug_flags & DBG(NIR))
 546                         return 140; /* no geometry and tessellation shaders yet */
 547                 if (si_have_tgsi_compute(sscreen))
 548                         return 450;
 549                 return 420;
 550
 551         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 552                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 553
 554         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 555         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 556         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 557                 /* SI doesn't support unaligned loads.
 558                  * CIK needs DRM 2.50.0 on radeon. */
 559                 return sscreen->b.chip_class == SI ||
 560                        (sscreen->b.info.drm_major == 2 &&
 561                         sscreen->b.info.drm_minor < 50);
 562
 563         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 564                 /* TODO: GFX9 hangs. */
 565                 if (sscreen->b.chip_class >= GFX9)
 566                         return 0;
 567                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 568                  * faults are mitigated in software.
 569                  */
 570                 if (sscreen->b.chip_class >= CIK &&
 571                     sscreen->b.info.drm_major == 3 &&
 572                     sscreen->b.info.drm_minor >= 13)
 573                         return RADEON_SPARSE_PAGE_SIZE;
 574                 return 0;
 575
 576         /* Unsupported features. */
 577         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 578         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 579         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 580         case PIPE_CAP_USER_VERTEX_BUFFERS:
 581         case PIPE_CAP_FAKE_SW_MSAA:
 582         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 583         case PIPE_CAP_VERTEXID_NOBASE:
 584         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 585         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 586         case PIPE_CAP_TGSI_FS_FBFETCH:
 587         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 588         case PIPE_CAP_UMA:
 589         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 590         case PIPE_CAP_POST_DEPTH_COVERAGE:
 591         case PIPE_CAP_TILE_RASTER_ORDER:
 592                 return 0;
 593
 594         case PIPE_CAP_NATIVE_FENCE_FD:
 595                 return sscreen->b.info.has_sync_file;
 596
 597         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 598                 return si_have_tgsi_compute(sscreen);
 599
 600         case PIPE_CAP_DRAW_PARAMETERS:
 601         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 602         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 603                 return sscreen->has_draw_indirect_multi;
 604
 605         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 606                 return 30;
 607
 608         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 609                 return sscreen->b.chip_class <= VI ?
 610                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 611
 612         /* Stream output. */
 613         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 614         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 615                 return 32*4;
 616
 617         /* Geometry shader output. */
 618         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 619                 return 1024;
 620         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 621                 return 4095;
 622
 623         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 624                 return 2048;
 625
 626         /* Texturing. */
 627         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 628         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 629                 return 15; /* 16384 */
 630         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 631                 /* textures support 8192, but layered rendering supports 2048 */
 632                 return 12;
 633         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 634                 /* textures support 8192, but layered rendering supports 2048 */
 635                 return 2048;
 636
 637         /* Viewports and render targets. */
 638         case PIPE_CAP_MAX_VIEWPORTS:
 639                 return SI_MAX_VIEWPORTS;
 640         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 641         case PIPE_CAP_MAX_RENDER_TARGETS:
 642                 return 8;
 643
 644         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 645         case PIPE_CAP_MIN_TEXEL_OFFSET:
 646                 return -32;
 647
 648         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 649         case PIPE_CAP_MAX_TEXEL_OFFSET:
 650                 return 31;
 651
 652         case PIPE_CAP_ENDIANNESS:
 653                 return PIPE_ENDIAN_LITTLE;
 654
 655         case PIPE_CAP_VENDOR_ID:
 656                 return ATI_VENDOR_ID;
 657         case PIPE_CAP_DEVICE_ID:
 658                 return sscreen->b.info.pci_id;
 659         case PIPE_CAP_VIDEO_MEMORY:
 660                 return sscreen->b.info.vram_size >> 20;
 661         case PIPE_CAP_PCI_GROUP:
 662                 return sscreen->b.info.pci_domain;
 663         case PIPE_CAP_PCI_BUS:
 664                 return sscreen->b.info.pci_bus;
 665         case PIPE_CAP_PCI_DEVICE:
 666                 return sscreen->b.info.pci_dev;
 667         case PIPE_CAP_PCI_FUNCTION:
 668                 return sscreen->b.info.pci_func;
 669         }
 670         return 0;
 671 }
 672
 673 static int si_get_shader_param(struct pipe_screen* pscreen,
 674                                enum pipe_shader_type shader,
 675                                enum pipe_shader_cap param)
 676 {
 677         struct si_screen *sscreen = (struct si_screen *)pscreen;
 678
 679         switch(shader)
 680         {
 681         case PIPE_SHADER_FRAGMENT:
 682         case PIPE_SHADER_VERTEX:
 683         case PIPE_SHADER_GEOMETRY:
 684         case PIPE_SHADER_TESS_CTRL:
 685         case PIPE_SHADER_TESS_EVAL:
 686                 break;
 687         case PIPE_SHADER_COMPUTE:
 688                 switch (param) {
 689                 case PIPE_SHADER_CAP_PREFERRED_IR:
 690                         return PIPE_SHADER_IR_NATIVE;
 691
 692                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 693                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 694
 695                         if (si_have_tgsi_compute(sscreen))
 696                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 697
 698                         return ir;
 699                 }
 700
 701                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 702                         uint64_t max_const_buffer_size;
 703                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 704                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 705                                 &max_const_buffer_size);
 706                         return MIN2(max_const_buffer_size, INT_MAX);
 707                 }
 708                 default:
 709                         /* If compute shaders don't require a special value
 710                          * for this cap, we can return the same value we
 711                          * do for other shader types. */
 712                         break;
 713                 }
 714                 break;
 715         default:
 716                 return 0;
 717         }
 718
 719         switch (param) {
 720         /* Shader limits. */
 721         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 722         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 723         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 724         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 725         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 726                 return 16384;
 727         case PIPE_SHADER_CAP_MAX_INPUTS:
 728                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 729         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 730                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 731         case PIPE_SHADER_CAP_MAX_TEMPS:
 732                 return 256; /* Max native temporaries. */
 733         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 734                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 735         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 736                 return SI_NUM_CONST_BUFFERS;
 737         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 738         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 739                 return SI_NUM_SAMPLERS;
 740         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 741                 return SI_NUM_SHADER_BUFFERS;
 742         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 743                 return SI_NUM_IMAGES;
 744         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 745                 return 32;
 746         case PIPE_SHADER_CAP_PREFERRED_IR:
 747                 if (sscreen->b.debug_flags & DBG(NIR) &&
 748                     (shader == PIPE_SHADER_VERTEX ||
 749                      shader == PIPE_SHADER_FRAGMENT))
 750                         return PIPE_SHADER_IR_NIR;
 751                 return PIPE_SHADER_IR_TGSI;
 752         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 753                 return 4;
 754
 755         /* Supported boolean features. */
 756         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 757         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 758         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 759         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 760         case PIPE_SHADER_CAP_INTEGERS:
 761         case PIPE_SHADER_CAP_INT64_ATOMICS:
 762         case PIPE_SHADER_CAP_FP16:
 763         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 764         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 765         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 766         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 767         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 768         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 769                 return 1;
 770
 771         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 772                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 773                 return shader != PIPE_SHADER_GEOMETRY &&
 774                        (sscreen->llvm_has_working_vgpr_indexing ||
 775                         /* TCS and TES load inputs directly from LDS or
 776                          * offchip memory, so indirect indexing is trivial. */
 777                         shader == PIPE_SHADER_TESS_CTRL ||
 778                         shader == PIPE_SHADER_TESS_EVAL);
 779
 780         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 781                 return sscreen->llvm_has_working_vgpr_indexing ||
 782                        /* TCS stores outputs directly to memory. */
 783                        shader == PIPE_SHADER_TESS_CTRL;
 784
 785         /* Unsupported boolean features. */
 786         case PIPE_SHADER_CAP_SUBROUTINES:
 787         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 788                 return 0;
 789         }
 790         return 0;
 791 }
 792
 793 static const struct nir_shader_compiler_options nir_options = {
 794         .vertex_id_zero_based = true,
 795         .lower_scmp = true,
 796         .lower_flrp32 = true,
 797         .lower_fsat = true,
 798         .lower_fdiv = true,
 799         .lower_sub = true,
 800         .lower_ffma = true,
 801         .lower_pack_snorm_2x16 = true,
 802         .lower_pack_snorm_4x8 = true,
 803         .lower_pack_unorm_2x16 = true,
 804         .lower_pack_unorm_4x8 = true,
 805         .lower_unpack_snorm_2x16 = true,
 806         .lower_unpack_snorm_4x8 = true,
 807         .lower_unpack_unorm_2x16 = true,
 808         .lower_unpack_unorm_4x8 = true,
 809         .lower_extract_byte = true,
 810         .lower_extract_word = true,
 811         .max_unroll_iterations = 32,
 812         .native_integers = true,
 813 };
 814
 815 static const void *
 816 si_get_compiler_options(struct pipe_screen *screen,
 817                         enum pipe_shader_ir ir,
 818                         enum pipe_shader_type shader)
 819 {
 820         assert(ir == PIPE_SHADER_IR_NIR);
 821         return &nir_options;
 822 }
 823
 824 static void si_destroy_screen(struct pipe_screen* pscreen)
 825 {
 826         struct si_screen *sscreen = (struct si_screen *)pscreen;
 827         struct si_shader_part *parts[] = {
 828                 sscreen->vs_prologs,
 829                 sscreen->tcs_epilogs,
 830                 sscreen->gs_prologs,
 831                 sscreen->ps_prologs,
 832                 sscreen->ps_epilogs
 833         };
 834         unsigned i;
 835
 836         if (!sscreen->b.ws->unref(sscreen->b.ws))
 837                 return;
 838
 839         util_queue_destroy(&sscreen->shader_compiler_queue);
 840         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 841
 842         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 843                 if (sscreen->tm[i])
 844                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 845
 846         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 847                 if (sscreen->tm_low_priority[i])
 848                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 849
 850         /* Free shader parts. */
 851         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 852                 while (parts[i]) {
 853                         struct si_shader_part *part = parts[i];
 854
 855                         parts[i] = part->next;
 856                         si_radeon_shader_binary_clean(&part->binary);
 857                         FREE(part);
 858                 }
 859         }
 860         mtx_destroy(&sscreen->shader_parts_mutex);
 861         si_destroy_shader_cache(sscreen);
 862         si_destroy_common_screen(&sscreen->b);
 863 }
 864
 865 static bool si_init_gs_info(struct si_screen *sscreen)
 866 {
 867         switch (sscreen->b.family) {
 868         case CHIP_OLAND:
 869         case CHIP_HAINAN:
 870         case CHIP_KAVERI:
 871         case CHIP_KABINI:
 872         case CHIP_MULLINS:
 873         case CHIP_ICELAND:
 874         case CHIP_CARRIZO:
 875         case CHIP_STONEY:
 876                 sscreen->gs_table_depth = 16;
 877                 return true;
 878         case CHIP_TAHITI:
 879         case CHIP_PITCAIRN:
 880         case CHIP_VERDE:
 881         case CHIP_BONAIRE:
 882         case CHIP_HAWAII:
 883         case CHIP_TONGA:
 884         case CHIP_FIJI:
 885         case CHIP_POLARIS10:
 886         case CHIP_POLARIS11:
 887         case CHIP_POLARIS12:
 888         case CHIP_VEGA10:
 889         case CHIP_RAVEN:
 890                 sscreen->gs_table_depth = 32;
 891                 return true;
 892         default:
 893                 return false;
 894         }
 895 }
 896
 897 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 898 {
 899         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 900         unsigned i;
 901
 902         if (!family)
 903                 return;
 904
 905         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 906                 if (!strcmp(family, si_get_llvm_processor_name(i))) {
 907                         /* Override family and chip_class. */
 908                         sscreen->b.family = sscreen->b.info.family = i;
 909
 910                         if (i >= CHIP_VEGA10)
 911                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 912                         else if (i >= CHIP_TONGA)
 913                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 914                         else if (i >= CHIP_BONAIRE)
 915                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 916                         else
 917                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 918
 919                         /* Don't submit any IBs. */
 920                         setenv("RADEON_NOOP", "1", 1);
 921                         return;
 922                 }
 923         }
 924
 925         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 926         exit(1);
 927 }
 928
 929 static void si_test_vmfault(struct si_screen *sscreen)
 930 {
 931         struct pipe_context *ctx = sscreen->b.aux_context;
 932         struct si_context *sctx = (struct si_context *)ctx;
 933         struct pipe_resource *buf =
 934                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 935
 936         if (!buf) {
 937                 puts("Buffer allocation failed.");
 938                 exit(1);
 939         }
 940
 941         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 942
 943         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_CP)) {
 944                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 945                 ctx->flush(ctx, NULL, 0);
 946                 puts("VM fault test: CP - done.");
 947         }
 948         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SDMA)) {
 949                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 950                 ctx->flush(ctx, NULL, 0);
 951                 puts("VM fault test: SDMA - done.");
 952         }
 953         if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SHADER)) {
 954                 util_test_constant_buffer(ctx, buf);
 955                 puts("VM fault test: Shader - done.");
 956         }
 957         exit(0);
 958 }
 959
 960 static void radeonsi_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 961 {
 962         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 963 }
 964
 965 static void radeonsi_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 966 {
 967         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 968
 969         ac_compute_device_uuid(&rscreen->info, uuid, PIPE_UUID_SIZE);
 970 }
 971
 972 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 973                                            const struct pipe_screen_config *config)
 974 {
 975         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 976         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 977
 978         if (!sscreen) {
 979                 return NULL;
 980         }
 981
 982         /* Set functions first. */
 983         sscreen->b.b.context_create = si_pipe_create_context;
 984         sscreen->b.b.destroy = si_destroy_screen;
 985         sscreen->b.b.get_param = si_get_param;
 986         sscreen->b.b.get_shader_param = si_get_shader_param;
 987         sscreen->b.b.get_compiler_options = si_get_compiler_options;
 988         sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
 989         sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
 990         sscreen->b.b.resource_create = si_resource_create_common;
 991
 992         si_init_screen_state_functions(sscreen);
 993
 994         /* Set these flags in debug_flags early, so that the shader cache takes
 995          * them into account.
 996          */
 997         if (driQueryOptionb(config->options,
 998                             "glsl_correct_derivatives_after_discard"))
 999                 sscreen->b.debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1000         if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
1001                 sscreen->b.debug_flags |= DBG(SI_SCHED);
1002
1003         if (!si_common_screen_init(&sscreen->b, ws) ||
1004             !si_init_gs_info(sscreen) ||
1005             !si_init_shader_cache(sscreen)) {
1006                 FREE(sscreen);
1007                 return NULL;
1008         }
1009
1010         /* Only enable as many threads as we have target machines, but at most
1011          * the number of CPUs - 1 if there is more than one.
1012          */
1013         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
1014         num_threads = MAX2(1, num_threads - 1);
1015         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1016         num_compiler_threads_lowprio =
1017                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1018
1019         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1020                              32, num_compiler_threads,
1021                              UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1022                 si_destroy_shader_cache(sscreen);
1023                 FREE(sscreen);
1024                 return NULL;
1025         }
1026
1027         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1028                              "si_shader_low",
1029                              32, num_compiler_threads_lowprio,
1030                              UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1031                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1032                si_destroy_shader_cache(sscreen);
1033                FREE(sscreen);
1034                return NULL;
1035         }
1036
1037         si_handle_env_var_force_family(sscreen);
1038
1039         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1040                 si_init_perfcounters(sscreen);
1041
1042         /* Hawaii has a bug with offchip buffers > 256 that can be worked
1043          * around by setting 4K granularity.
1044          */
1045         sscreen->tess_offchip_block_dw_size =
1046                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1047
1048         /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1049          * on SI. */
1050         sscreen->has_clear_state = sscreen->b.chip_class >= CIK;
1051
1052         sscreen->has_distributed_tess =
1053                 sscreen->b.chip_class >= VI &&
1054                 sscreen->b.info.max_se >= 2;
1055
1056         sscreen->has_draw_indirect_multi =
1057                 (sscreen->b.family >= CHIP_POLARIS10) ||
1058                 (sscreen->b.chip_class == VI &&
1059                  sscreen->b.info.pfp_fw_version >= 121 &&
1060                  sscreen->b.info.me_fw_version >= 87) ||
1061                 (sscreen->b.chip_class == CIK &&
1062                  sscreen->b.info.pfp_fw_version >= 211 &&
1063                  sscreen->b.info.me_fw_version >= 173) ||
1064                 (sscreen->b.chip_class == SI &&
1065                  sscreen->b.info.pfp_fw_version >= 79 &&
1066                  sscreen->b.info.me_fw_version >= 142);
1067
1068         sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
1069                                          sscreen->b.info.max_se >= 2 &&
1070                                          !(sscreen->b.debug_flags & DBG(NO_OUT_OF_ORDER));
1071         sscreen->assume_no_z_fights =
1072                 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1073         sscreen->commutative_blend_add =
1074                 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1075         sscreen->clear_db_cache_before_clear =
1076                 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1077         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1078                                             sscreen->b.family <= CHIP_POLARIS12) ||
1079                                            sscreen->b.family == CHIP_VEGA10 ||
1080                                            sscreen->b.family == CHIP_RAVEN;
1081
1082         if (sscreen->b.debug_flags & DBG(DPBB)) {
1083                 sscreen->dpbb_allowed = true;
1084         } else {
1085                 /* Only enable primitive binning on Raven by default. */
1086                 sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
1087                                         !(sscreen->b.debug_flags & DBG(NO_DPBB));
1088         }
1089
1090         if (sscreen->b.debug_flags & DBG(DFSM)) {
1091                 sscreen->dfsm_allowed = sscreen->dpbb_allowed;
1092         } else {
1093                 sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1094                                         !(sscreen->b.debug_flags & DBG(NO_DFSM));
1095         }
1096
1097         /* While it would be nice not to have this flag, we are constrained
1098          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1099          * on GFX9.
1100          */
1101         sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1102
1103         sscreen->b.has_cp_dma = true;
1104         sscreen->b.has_streamout = true;
1105
1106         /* Some chips have RB+ registers, but don't support RB+. Those must
1107          * always disable it.
1108          */
1109         if (sscreen->b.family == CHIP_STONEY ||
1110             sscreen->b.chip_class >= GFX9) {
1111                 sscreen->b.has_rbplus = true;
1112
1113                 sscreen->b.rbplus_allowed =
1114                         !(sscreen->b.debug_flags & DBG(NO_RB_PLUS)) &&
1115                         (sscreen->b.family == CHIP_STONEY ||
1116                          sscreen->b.family == CHIP_RAVEN);
1117         }
1118
1119         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1120         sscreen->use_monolithic_shaders =
1121                 (sscreen->b.debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1122
1123         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1124                                             SI_CONTEXT_INV_VMEM_L1;
1125         if (sscreen->b.chip_class <= VI) {
1126                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1127                 sscreen->b.barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1128         }
1129
1130         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1131
1132         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1133                 sscreen->b.debug_flags |= DBG_ALL_SHADERS;
1134
1135         for (i = 0; i < num_compiler_threads; i++)
1136                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1137         for (i = 0; i < num_compiler_threads_lowprio; i++)
1138                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1139
1140         /* Create the auxiliary context. This must be done last. */
1141         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1142
1143         if (sscreen->b.debug_flags & DBG(TEST_DMA))
1144                 si_test_dma(&sscreen->b);
1145
1146         if (sscreen->b.debug_flags & (DBG(TEST_VMFAULT_CP) |
1147                                       DBG(TEST_VMFAULT_SDMA) |
1148                                       DBG(TEST_VMFAULT_SHADER)))
1149                 si_test_vmfault(sscreen);
1150
1151         return &sscreen->b.b;
1152 }