2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
31 #include "ac_llvm_util.h"
32 #include "radeon/radeon_uvd.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
44 static const struct debug_named_value debug_options
[] = {
45 /* Shader logging options: */
46 { "vs", DBG(VS
), "Print vertex shaders" },
47 { "ps", DBG(PS
), "Print pixel shaders" },
48 { "gs", DBG(GS
), "Print geometry shaders" },
49 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
50 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
51 { "cs", DBG(CS
), "Print compute shaders" },
52 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
53 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
54 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
55 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
57 /* Shader compiler options the shader cache should be aware of: */
58 { "unsafemath", DBG(UNSAFE_MATH
), "Enable unsafe math shader optimizations" },
59 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
60 { "gisel", DBG(GISEL
), "Enable LLVM global instruction selector." },
62 /* Shader compiler options (with no effect on the shader cache): */
63 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
64 { "nir", DBG(NIR
), "Enable experimental NIR shaders" },
65 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
66 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
68 /* Information logging options: */
69 { "info", DBG(INFO
), "Print driver information" },
70 { "tex", DBG(TEX
), "Print texture info" },
71 { "compute", DBG(COMPUTE
), "Print compute info" },
72 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
75 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
76 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
77 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
78 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
79 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
80 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
82 /* 3D engine options: */
83 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
84 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
85 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
86 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
87 { "dpbb", DBG(DPBB
), "Enable DPBB." },
88 { "dfsm", DBG(DFSM
), "Enable DFSM." },
89 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
90 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
91 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
92 { "notiling", DBG(NO_TILING
), "Disable tiling" },
93 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
94 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
95 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
96 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
97 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
100 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
101 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
102 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
103 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
104 { "testdmaperf", DBG(TEST_DMA_PERF
), "Test DMA performance" },
105 { "testgds", DBG(TEST_GDS
), "Test GDS." },
106 { "testgdsmm", DBG(TEST_GDS_MM
), "Test GDS memory management." },
107 { "testgdsoamm", DBG(TEST_GDS_OA_MM
), "Test GDS OA memory management." },
109 DEBUG_NAMED_VALUE_END
/* must be last */
112 static void si_init_compiler(struct si_screen
*sscreen
,
113 struct ac_llvm_compiler
*compiler
)
115 /* Only create the less-optimizing version of the compiler on APUs
116 * predating Ryzen (Raven). */
117 bool create_low_opt_compiler
= !sscreen
->info
.has_dedicated_vram
&&
118 sscreen
->info
.chip_class
<= VI
;
120 enum ac_target_machine_options tm_options
=
121 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
122 (sscreen
->debug_flags
& DBG(GISEL
) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
123 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
124 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
125 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
126 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0) |
127 (create_low_opt_compiler
? AC_TM_CREATE_LOW_OPT
: 0);
130 ac_init_llvm_compiler(compiler
, sscreen
->info
.family
, tm_options
);
131 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
133 if (compiler
->low_opt_tm
)
134 compiler
->low_opt_passes
= ac_create_llvm_passes(compiler
->low_opt_tm
);
137 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
139 ac_destroy_llvm_passes(compiler
->passes
);
140 ac_destroy_llvm_passes(compiler
->low_opt_passes
);
141 ac_destroy_llvm_compiler(compiler
);
147 static void si_destroy_context(struct pipe_context
*context
)
149 struct si_context
*sctx
= (struct si_context
*)context
;
152 /* Unreference the framebuffer normally to disable related logic
155 struct pipe_framebuffer_state fb
= {};
156 if (context
->set_framebuffer_state
)
157 context
->set_framebuffer_state(context
, &fb
);
159 si_release_all_descriptors(sctx
);
161 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
162 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
163 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
164 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
165 pipe_resource_reference(&sctx
->sample_pos_buffer
, NULL
);
166 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
167 free(sctx
->border_color_table
);
168 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
169 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
170 r600_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
172 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
173 if (sctx
->init_config_gs_rings
)
174 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
175 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
176 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
178 if (sctx
->fixed_func_tcs_shader
.cso
)
179 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
180 if (sctx
->custom_dsa_flush
)
181 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
182 if (sctx
->custom_blend_resolve
)
183 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
184 if (sctx
->custom_blend_fmask_decompress
)
185 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
186 if (sctx
->custom_blend_eliminate_fastclear
)
187 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
188 if (sctx
->custom_blend_dcc_decompress
)
189 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
190 if (sctx
->vs_blit_pos
)
191 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
192 if (sctx
->vs_blit_pos_layered
)
193 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
194 if (sctx
->vs_blit_color
)
195 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
196 if (sctx
->vs_blit_color_layered
)
197 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
198 if (sctx
->vs_blit_texcoord
)
199 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
200 if (sctx
->cs_clear_buffer
)
201 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_buffer
);
202 if (sctx
->cs_copy_buffer
)
203 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_buffer
);
206 util_blitter_destroy(sctx
->blitter
);
208 /* Release DCC stats. */
209 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
210 assert(!sctx
->dcc_stats
[i
].query_active
);
212 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
213 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
214 sctx
->b
.destroy_query(&sctx
->b
,
215 sctx
->dcc_stats
[i
].ps_stats
[j
]);
217 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
220 if (sctx
->query_result_shader
)
221 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
224 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
226 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
228 sctx
->ws
->ctx_destroy(sctx
->ctx
);
230 if (sctx
->b
.stream_uploader
)
231 u_upload_destroy(sctx
->b
.stream_uploader
);
232 if (sctx
->b
.const_uploader
)
233 u_upload_destroy(sctx
->b
.const_uploader
);
234 if (sctx
->cached_gtt_allocator
)
235 u_upload_destroy(sctx
->cached_gtt_allocator
);
237 slab_destroy_child(&sctx
->pool_transfers
);
238 slab_destroy_child(&sctx
->pool_transfers_unsync
);
240 if (sctx
->allocator_zeroed_memory
)
241 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
243 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
244 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
245 r600_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
247 si_destroy_compiler(&sctx
->compiler
);
249 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
251 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
252 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
254 util_dynarray_fini(&sctx
->resident_tex_handles
);
255 util_dynarray_fini(&sctx
->resident_img_handles
);
256 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
257 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
258 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
262 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
264 struct si_context
*sctx
= (struct si_context
*)ctx
;
266 if (sctx
->screen
->info
.has_gpu_reset_status_query
)
267 return sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
269 if (sctx
->screen
->info
.has_gpu_reset_counter_query
) {
270 unsigned latest
= sctx
->ws
->query_value(sctx
->ws
,
271 RADEON_GPU_RESET_COUNTER
);
273 if (sctx
->gpu_reset_counter
== latest
)
274 return PIPE_NO_RESET
;
276 sctx
->gpu_reset_counter
= latest
;
277 return PIPE_UNKNOWN_CONTEXT_RESET
;
280 return PIPE_NO_RESET
;
283 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
284 const struct pipe_device_reset_callback
*cb
)
286 struct si_context
*sctx
= (struct si_context
*)ctx
;
289 sctx
->device_reset_callback
= *cb
;
291 memset(&sctx
->device_reset_callback
, 0,
292 sizeof(sctx
->device_reset_callback
));
295 bool si_check_device_reset(struct si_context
*sctx
)
297 enum pipe_reset_status status
;
299 if (!sctx
->device_reset_callback
.reset
)
302 if (!sctx
->b
.get_device_reset_status
)
305 status
= sctx
->b
.get_device_reset_status(&sctx
->b
);
306 if (status
== PIPE_NO_RESET
)
309 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
313 /* Apitrace profiling:
314 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
315 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
316 * and remember its number.
317 * 3) In Mesa, enable queries and performance counters around that draw
318 * call and print the results.
319 * 4) glretrace --benchmark --markers ..
321 static void si_emit_string_marker(struct pipe_context
*ctx
,
322 const char *string
, int len
)
324 struct si_context
*sctx
= (struct si_context
*)ctx
;
326 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
329 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
332 static void si_set_debug_callback(struct pipe_context
*ctx
,
333 const struct pipe_debug_callback
*cb
)
335 struct si_context
*sctx
= (struct si_context
*)ctx
;
336 struct si_screen
*screen
= sctx
->screen
;
338 util_queue_finish(&screen
->shader_compiler_queue
);
339 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
344 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
347 static void si_set_log_context(struct pipe_context
*ctx
,
348 struct u_log_context
*log
)
350 struct si_context
*sctx
= (struct si_context
*)ctx
;
354 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
357 static void si_set_context_param(struct pipe_context
*ctx
,
358 enum pipe_context_param param
,
361 struct radeon_winsys
*ws
= ((struct si_context
*)ctx
)->ws
;
364 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
:
365 ws
->pin_threads_to_L3_cache(ws
, value
);
371 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
374 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
375 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
376 struct radeon_winsys
*ws
= sscreen
->ws
;
378 bool stop_exec_on_failure
= (flags
& PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET
) != 0;
383 if (flags
& PIPE_CONTEXT_DEBUG
)
384 sscreen
->record_llvm_ir
= true; /* racy but not critical */
386 sctx
->b
.screen
= screen
; /* this must be set first */
388 sctx
->b
.destroy
= si_destroy_context
;
389 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
390 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
391 sctx
->b
.set_log_context
= si_set_log_context
;
392 sctx
->b
.set_context_param
= si_set_context_param
;
393 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
394 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
396 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
397 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
399 sctx
->ws
= sscreen
->ws
;
400 sctx
->family
= sscreen
->info
.family
;
401 sctx
->chip_class
= sscreen
->info
.chip_class
;
403 if (sscreen
->info
.has_gpu_reset_counter_query
) {
404 sctx
->gpu_reset_counter
=
405 sctx
->ws
->query_value(sctx
->ws
, RADEON_GPU_RESET_COUNTER
);
408 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
409 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
411 si_init_context_texture_functions(sctx
);
412 si_init_query_functions(sctx
);
414 if (sctx
->chip_class
== CIK
||
415 sctx
->chip_class
== VI
||
416 sctx
->chip_class
== GFX9
) {
417 sctx
->eop_bug_scratch
= r600_resource(
418 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
419 16 * sscreen
->info
.num_render_backends
));
420 if (!sctx
->eop_bug_scratch
)
424 sctx
->allocator_zeroed_memory
=
425 u_suballocator_create(&sctx
->b
, sscreen
->info
.gart_page_size
,
426 0, PIPE_USAGE_DEFAULT
,
427 SI_RESOURCE_FLAG_SO_FILLED_SIZE
, true);
428 if (!sctx
->allocator_zeroed_memory
)
431 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
432 0, PIPE_USAGE_STREAM
,
433 SI_RESOURCE_FLAG_READ_ONLY
);
434 if (!sctx
->b
.stream_uploader
)
437 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 128 * 1024,
438 0, PIPE_USAGE_DEFAULT
,
439 SI_RESOURCE_FLAG_32BIT
|
440 (sscreen
->cpdma_prefetch_writes_memory
?
441 0 : SI_RESOURCE_FLAG_READ_ONLY
));
442 if (!sctx
->b
.const_uploader
)
445 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
446 0, PIPE_USAGE_STAGING
, 0);
447 if (!sctx
->cached_gtt_allocator
)
450 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
454 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
455 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
456 (void*)si_flush_dma_cs
,
457 sctx
, stop_exec_on_failure
);
460 si_init_buffer_functions(sctx
);
461 si_init_clear_functions(sctx
);
462 si_init_blit_functions(sctx
);
463 si_init_compute_functions(sctx
);
464 si_init_compute_blit_functions(sctx
);
465 si_init_debug_functions(sctx
);
466 si_init_msaa_functions(sctx
);
467 si_init_streamout_functions(sctx
);
469 if (sscreen
->info
.has_hw_decode
) {
470 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
471 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
473 sctx
->b
.create_video_codec
= vl_create_decoder
;
474 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
477 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
, RING_GFX
,
478 (void*)si_flush_gfx_cs
, sctx
, stop_exec_on_failure
);
481 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
482 sizeof(*sctx
->border_color_table
));
483 if (!sctx
->border_color_table
)
486 sctx
->border_color_buffer
= r600_resource(
487 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
488 SI_MAX_BORDER_COLORS
*
489 sizeof(*sctx
->border_color_table
)));
490 if (!sctx
->border_color_buffer
)
493 sctx
->border_color_map
=
494 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
495 NULL
, PIPE_TRANSFER_WRITE
);
496 if (!sctx
->border_color_map
)
499 si_init_all_descriptors(sctx
);
500 si_init_fence_functions(sctx
);
501 si_init_state_functions(sctx
);
502 si_init_shader_functions(sctx
);
503 si_init_viewport_functions(sctx
);
505 if (sctx
->chip_class
>= CIK
)
506 cik_init_sdma_functions(sctx
);
508 si_init_dma_functions(sctx
);
510 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
511 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
513 bool dst_stream_policy
= SI_COMPUTE_DST_CACHE_POLICY
!= L2_LRU
;
514 sctx
->cs_clear_buffer
= si_create_dma_compute_shader(&sctx
->b
,
515 SI_COMPUTE_CLEAR_DW_PER_THREAD
,
516 dst_stream_policy
, false);
517 sctx
->cs_copy_buffer
= si_create_dma_compute_shader(&sctx
->b
,
518 SI_COMPUTE_COPY_DW_PER_THREAD
,
519 dst_stream_policy
, true);
521 sctx
->blitter
= util_blitter_create(&sctx
->b
);
522 if (sctx
->blitter
== NULL
)
524 sctx
->blitter
->skip_viewport_restore
= true;
526 si_init_draw_functions(sctx
);
528 sctx
->sample_mask
= 0xffff;
530 if (sctx
->chip_class
>= GFX9
) {
531 sctx
->wait_mem_scratch
= r600_resource(
532 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 4));
533 if (!sctx
->wait_mem_scratch
)
536 /* Initialize the memory. */
537 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
538 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
539 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
540 S_370_WR_CONFIRM(1) |
541 S_370_ENGINE_SEL(V_370_ME
));
542 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
);
543 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
>> 32);
544 radeon_emit(cs
, sctx
->wait_mem_number
);
545 radeon_add_to_buffer_list(sctx
, cs
, sctx
->wait_mem_scratch
,
546 RADEON_USAGE_WRITE
, RADEON_PRIO_FENCE
);
549 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
550 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
551 if (sctx
->chip_class
== CIK
) {
552 sctx
->null_const_buf
.buffer
=
553 pipe_aligned_buffer_create(screen
,
554 SI_RESOURCE_FLAG_32BIT
,
555 PIPE_USAGE_DEFAULT
, 16,
556 sctx
->screen
->info
.tcc_cache_line_size
);
557 if (!sctx
->null_const_buf
.buffer
)
559 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
561 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
562 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
563 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
564 &sctx
->null_const_buf
);
568 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
569 &sctx
->null_const_buf
);
570 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
571 &sctx
->null_const_buf
);
572 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
573 &sctx
->null_const_buf
);
574 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
575 &sctx
->null_const_buf
);
576 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
577 &sctx
->null_const_buf
);
580 uint64_t max_threads_per_block
;
581 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
582 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
583 &max_threads_per_block
);
585 /* The maximum number of scratch waves. Scratch space isn't divided
586 * evenly between CUs. The number is only a function of the number of CUs.
587 * We can decrease the constant to decrease the scratch buffer size.
589 * sctx->scratch_waves must be >= the maximum posible size of
590 * 1 threadgroup, so that the hw doesn't hang from being unable
593 * The recommended value is 4 per CU at most. Higher numbers don't
594 * bring much benefit, but they still occupy chip resources (think
595 * async compute). I've seen ~2% performance difference between 4 and 32.
597 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
598 max_threads_per_block
/ 64);
600 si_init_compiler(sscreen
, &sctx
->compiler
);
602 /* Bindless handles. */
603 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
604 _mesa_key_pointer_equal
);
605 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
606 _mesa_key_pointer_equal
);
608 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
609 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
610 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
611 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
612 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
614 sctx
->sample_pos_buffer
=
615 pipe_buffer_create(sctx
->b
.screen
, 0, PIPE_USAGE_DEFAULT
,
616 sizeof(sctx
->sample_positions
));
617 pipe_buffer_write(&sctx
->b
, sctx
->sample_pos_buffer
, 0,
618 sizeof(sctx
->sample_positions
), &sctx
->sample_positions
);
620 /* this must be last */
621 si_begin_new_gfx_cs(sctx
);
623 if (sctx
->chip_class
== CIK
) {
624 /* Clear the NULL constant buffer, because loads should return zeros. */
625 uint32_t clear_value
= 0;
626 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
627 sctx
->null_const_buf
.buffer
->width0
,
628 &clear_value
, 4, SI_COHERENCY_SHADER
);
632 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
633 si_destroy_context(&sctx
->b
);
637 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
638 void *priv
, unsigned flags
)
640 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
641 struct pipe_context
*ctx
;
643 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
644 flags
|= PIPE_CONTEXT_DEBUG
;
646 ctx
= si_create_context(screen
, flags
);
648 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
651 /* Clover (compute-only) is unsupported. */
652 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
655 /* When shaders are logged to stderr, asynchronous compilation is
657 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
660 /* Use asynchronous flushes only on amdgpu, since the radeon
661 * implementation for fence_server_sync is incomplete. */
662 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
663 si_replace_buffer_storage
,
664 sscreen
->info
.drm_major
>= 3 ? si_create_fence
: NULL
,
665 &((struct si_context
*)ctx
)->tc
);
671 static void si_destroy_screen(struct pipe_screen
* pscreen
)
673 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
674 struct si_shader_part
*parts
[] = {
676 sscreen
->tcs_epilogs
,
683 if (!sscreen
->ws
->unref(sscreen
->ws
))
686 util_queue_destroy(&sscreen
->shader_compiler_queue
);
687 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
689 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
690 si_destroy_compiler(&sscreen
->compiler
[i
]);
692 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
693 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
695 /* Free shader parts. */
696 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
698 struct si_shader_part
*part
= parts
[i
];
700 parts
[i
] = part
->next
;
701 ac_shader_binary_clean(&part
->binary
);
705 mtx_destroy(&sscreen
->shader_parts_mutex
);
706 si_destroy_shader_cache(sscreen
);
708 si_destroy_perfcounters(sscreen
);
709 si_gpu_load_kill_thread(sscreen
);
711 mtx_destroy(&sscreen
->gpu_load_mutex
);
712 mtx_destroy(&sscreen
->aux_context_lock
);
713 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
715 slab_destroy_parent(&sscreen
->pool_transfers
);
717 disk_cache_destroy(sscreen
->disk_shader_cache
);
718 sscreen
->ws
->destroy(sscreen
->ws
);
722 static void si_init_gs_info(struct si_screen
*sscreen
)
724 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
725 sscreen
->info
.family
);
728 static void si_test_vmfault(struct si_screen
*sscreen
)
730 struct pipe_context
*ctx
= sscreen
->aux_context
;
731 struct si_context
*sctx
= (struct si_context
*)ctx
;
732 struct pipe_resource
*buf
=
733 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
736 puts("Buffer allocation failed.");
740 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
742 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
743 si_cp_dma_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0,
744 SI_COHERENCY_NONE
, L2_BYPASS
);
745 ctx
->flush(ctx
, NULL
, 0);
746 puts("VM fault test: CP - done.");
748 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
749 si_sdma_clear_buffer(sctx
, buf
, 0, 4, 0);
750 ctx
->flush(ctx
, NULL
, 0);
751 puts("VM fault test: SDMA - done.");
753 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
754 util_test_constant_buffer(ctx
, buf
);
755 puts("VM fault test: Shader - done.");
760 static void si_test_gds_memory_management(struct si_context
*sctx
,
761 unsigned alloc_size
, unsigned alignment
,
762 enum radeon_bo_domain domain
)
764 struct radeon_winsys
*ws
= sctx
->ws
;
765 struct radeon_cmdbuf
*cs
[8];
766 struct pb_buffer
*gds_bo
[ARRAY_SIZE(cs
)];
768 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
769 cs
[i
] = ws
->cs_create(sctx
->ctx
, RING_COMPUTE
,
771 gds_bo
[i
] = ws
->buffer_create(ws
, alloc_size
, alignment
, domain
, 0);
775 for (unsigned iterations
= 0; iterations
< 20000; iterations
++) {
776 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
777 /* This clears GDS with CP DMA.
779 * We don't care if GDS is present. Just add some packet
780 * to make the GPU busy for a moment.
782 si_cp_dma_clear_buffer(sctx
, cs
[i
], NULL
, 0, alloc_size
, 0,
783 SI_CPDMA_SKIP_BO_LIST_UPDATE
|
784 SI_CPDMA_SKIP_CHECK_CS_SPACE
|
785 SI_CPDMA_SKIP_GFX_SYNC
, 0, 0);
787 ws
->cs_add_buffer(cs
[i
], gds_bo
[i
], domain
,
788 RADEON_USAGE_READWRITE
, 0);
789 ws
->cs_flush(cs
[i
], PIPE_FLUSH_ASYNC
, NULL
);
795 static void si_disk_cache_create(struct si_screen
*sscreen
)
797 /* Don't use the cache if shader dumping is enabled. */
798 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
801 struct mesa_sha1 ctx
;
802 unsigned char sha1
[20];
803 char cache_id
[20 * 2 + 1];
805 _mesa_sha1_init(&ctx
);
807 if (!disk_cache_get_function_identifier(si_disk_cache_create
, &ctx
) ||
808 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
,
812 _mesa_sha1_final(&ctx
, sha1
);
813 disk_cache_format_hex_id(cache_id
, sha1
, 20 * 2);
815 /* These flags affect shader compilation. */
816 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
821 uint64_t shader_debug_flags
= sscreen
->debug_flags
&
824 /* Add the high bits of 32-bit addresses, which affects
825 * how 32-bit addresses are expanded to 64 bits.
827 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
828 shader_debug_flags
|= (uint64_t)sscreen
->info
.address32_hi
<< 32;
830 sscreen
->disk_shader_cache
=
831 disk_cache_create(sscreen
->info
.name
,
836 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
,
837 const struct pipe_screen_config
*config
)
839 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
840 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
, i
;
847 ws
->query_info(ws
, &sscreen
->info
);
849 if (sscreen
->info
.chip_class
>= GFX9
) {
850 sscreen
->se_tile_repeat
= 32 * sscreen
->info
.max_se
;
852 ac_get_raster_config(&sscreen
->info
,
853 &sscreen
->pa_sc_raster_config
,
854 &sscreen
->pa_sc_raster_config_1
,
855 &sscreen
->se_tile_repeat
);
858 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
861 /* Set functions first. */
862 sscreen
->b
.context_create
= si_pipe_create_context
;
863 sscreen
->b
.destroy
= si_destroy_screen
;
865 si_init_screen_get_functions(sscreen
);
866 si_init_screen_buffer_functions(sscreen
);
867 si_init_screen_fence_functions(sscreen
);
868 si_init_screen_state_functions(sscreen
);
869 si_init_screen_texture_functions(sscreen
);
870 si_init_screen_query_functions(sscreen
);
872 /* Set these flags in debug_flags early, so that the shader cache takes
875 if (driQueryOptionb(config
->options
,
876 "glsl_correct_derivatives_after_discard"))
877 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
878 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
879 sscreen
->debug_flags
|= DBG(SI_SCHED
);
882 if (sscreen
->debug_flags
& DBG(INFO
))
883 ac_print_gpu_info(&sscreen
->info
);
885 slab_create_parent(&sscreen
->pool_transfers
,
886 sizeof(struct si_transfer
), 64);
888 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
889 if (sscreen
->force_aniso
>= 0) {
890 printf("radeonsi: Forcing anisotropy filter to %ix\n",
891 /* round down to a power of two */
892 1 << util_logbase2(sscreen
->force_aniso
));
895 (void) mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
896 (void) mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
898 si_init_gs_info(sscreen
);
899 if (!si_init_shader_cache(sscreen
)) {
904 si_disk_cache_create(sscreen
);
906 /* Determine the number of shader compiler threads. */
907 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
909 if (hw_threads
>= 12) {
910 num_comp_hi_threads
= hw_threads
* 3 / 4;
911 num_comp_lo_threads
= hw_threads
/ 3;
912 } else if (hw_threads
>= 6) {
913 num_comp_hi_threads
= hw_threads
- 2;
914 num_comp_lo_threads
= hw_threads
/ 2;
915 } else if (hw_threads
>= 2) {
916 num_comp_hi_threads
= hw_threads
- 1;
917 num_comp_lo_threads
= hw_threads
/ 2;
919 num_comp_hi_threads
= 1;
920 num_comp_lo_threads
= 1;
923 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
924 ARRAY_SIZE(sscreen
->compiler
));
925 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
926 ARRAY_SIZE(sscreen
->compiler_lowp
));
928 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "sh",
929 64, num_comp_hi_threads
,
930 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
931 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
)) {
932 si_destroy_shader_cache(sscreen
);
937 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
939 64, num_comp_lo_threads
,
940 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
941 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
|
942 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
943 si_destroy_shader_cache(sscreen
);
948 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
949 si_init_perfcounters(sscreen
);
951 /* Determine tessellation ring info. */
952 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= CIK
&&
953 sscreen
->info
.family
!= CHIP_CARRIZO
&&
954 sscreen
->info
.family
!= CHIP_STONEY
;
955 /* This must be one less than the maximum number due to a hw limitation.
956 * Various hardware bugs in SI, CIK, and GFX9 need this.
958 unsigned max_offchip_buffers_per_se
;
960 /* Only certain chips can use the maximum value. */
961 if (sscreen
->info
.family
== CHIP_VEGA12
||
962 sscreen
->info
.family
== CHIP_VEGA20
)
963 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
965 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
967 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
968 sscreen
->info
.max_se
;
969 unsigned offchip_granularity
;
971 /* Hawaii has a bug with offchip buffers > 256 that can be worked
972 * around by setting 4K granularity.
974 if (sscreen
->info
.family
== CHIP_HAWAII
) {
975 sscreen
->tess_offchip_block_dw_size
= 4096;
976 offchip_granularity
= V_03093C_X_4K_DWORDS
;
978 sscreen
->tess_offchip_block_dw_size
= 8192;
979 offchip_granularity
= V_03093C_X_8K_DWORDS
;
982 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
983 assert(((sscreen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
984 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
985 sscreen
->tess_offchip_block_dw_size
* 4;
987 if (sscreen
->info
.chip_class
>= CIK
) {
988 if (sscreen
->info
.chip_class
>= VI
)
989 --max_offchip_buffers
;
990 sscreen
->vgt_hs_offchip_param
=
991 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
992 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
994 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
995 sscreen
->vgt_hs_offchip_param
=
996 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
999 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1000 * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1001 * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
1002 sscreen
->has_clear_state
= sscreen
->info
.chip_class
>= CIK
&&
1003 sscreen
->info
.drm_major
== 3;
1005 sscreen
->has_distributed_tess
=
1006 sscreen
->info
.chip_class
>= VI
&&
1007 sscreen
->info
.max_se
>= 2;
1009 sscreen
->has_draw_indirect_multi
=
1010 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
1011 (sscreen
->info
.chip_class
== VI
&&
1012 sscreen
->info
.pfp_fw_version
>= 121 &&
1013 sscreen
->info
.me_fw_version
>= 87) ||
1014 (sscreen
->info
.chip_class
== CIK
&&
1015 sscreen
->info
.pfp_fw_version
>= 211 &&
1016 sscreen
->info
.me_fw_version
>= 173) ||
1017 (sscreen
->info
.chip_class
== SI
&&
1018 sscreen
->info
.pfp_fw_version
>= 79 &&
1019 sscreen
->info
.me_fw_version
>= 142);
1021 sscreen
->has_out_of_order_rast
= sscreen
->info
.chip_class
>= VI
&&
1022 sscreen
->info
.max_se
>= 2 &&
1023 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
1024 sscreen
->assume_no_z_fights
=
1025 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
1026 sscreen
->commutative_blend_add
=
1027 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
1028 sscreen
->clear_db_cache_before_clear
=
1029 driQueryOptionb(config
->options
, "radeonsi_clear_db_cache_before_clear");
1030 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->info
.family
>= CHIP_POLARIS10
&&
1031 sscreen
->info
.family
<= CHIP_POLARIS12
) ||
1032 sscreen
->info
.family
== CHIP_VEGA10
||
1033 sscreen
->info
.family
== CHIP_RAVEN
;
1034 sscreen
->has_ls_vgpr_init_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
1035 sscreen
->info
.family
== CHIP_RAVEN
;
1036 sscreen
->has_dcc_constant_encode
= sscreen
->info
.family
== CHIP_RAVEN2
;
1038 /* Only enable primitive binning on APUs by default. */
1039 sscreen
->dpbb_allowed
= sscreen
->info
.family
== CHIP_RAVEN
||
1040 sscreen
->info
.family
== CHIP_RAVEN2
;
1042 sscreen
->dfsm_allowed
= sscreen
->info
.family
== CHIP_RAVEN
||
1043 sscreen
->info
.family
== CHIP_RAVEN2
;
1045 /* Process DPBB enable flags. */
1046 if (sscreen
->debug_flags
& DBG(DPBB
)) {
1047 sscreen
->dpbb_allowed
= true;
1048 if (sscreen
->debug_flags
& DBG(DFSM
))
1049 sscreen
->dfsm_allowed
= true;
1052 /* Process DPBB disable flags. */
1053 if (sscreen
->debug_flags
& DBG(NO_DPBB
)) {
1054 sscreen
->dpbb_allowed
= false;
1055 sscreen
->dfsm_allowed
= false;
1056 } else if (sscreen
->debug_flags
& DBG(NO_DFSM
)) {
1057 sscreen
->dfsm_allowed
= false;
1060 /* While it would be nice not to have this flag, we are constrained
1061 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1064 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
<= VI
;
1066 /* Some chips have RB+ registers, but don't support RB+. Those must
1067 * always disable it.
1069 if (sscreen
->info
.family
== CHIP_STONEY
||
1070 sscreen
->info
.chip_class
>= GFX9
) {
1071 sscreen
->has_rbplus
= true;
1073 sscreen
->rbplus_allowed
=
1074 !(sscreen
->debug_flags
& DBG(NO_RB_PLUS
)) &&
1075 (sscreen
->info
.family
== CHIP_STONEY
||
1076 sscreen
->info
.family
== CHIP_VEGA12
||
1077 sscreen
->info
.family
== CHIP_RAVEN
||
1078 sscreen
->info
.family
== CHIP_RAVEN2
);
1081 sscreen
->dcc_msaa_allowed
=
1082 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1084 sscreen
->cpdma_prefetch_writes_memory
= sscreen
->info
.chip_class
<= VI
;
1086 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1087 sscreen
->use_monolithic_shaders
=
1088 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1090 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
1091 SI_CONTEXT_INV_VMEM_L1
;
1092 if (sscreen
->info
.chip_class
<= VI
) {
1093 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_GLOBAL_L2
;
1094 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1097 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1098 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1105 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1107 * s >= z >= c (ignoring this only wastes memory)
1112 * Only MSAA color and depth buffers are overriden.
1114 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1115 const char *eqaa
= debug_get_option("EQAA", NULL
);
1118 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1119 sscreen
->eqaa_force_coverage_samples
= s
;
1120 sscreen
->eqaa_force_z_samples
= z
;
1121 sscreen
->eqaa_force_color_samples
= f
;
1125 for (i
= 0; i
< num_comp_hi_threads
; i
++)
1126 si_init_compiler(sscreen
, &sscreen
->compiler
[i
]);
1127 for (i
= 0; i
< num_comp_lo_threads
; i
++)
1128 si_init_compiler(sscreen
, &sscreen
->compiler_lowp
[i
]);
1130 /* Create the auxiliary context. This must be done last. */
1131 sscreen
->aux_context
= si_create_context(&sscreen
->b
, 0);
1133 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1134 si_test_dma(sscreen
);
1136 if (sscreen
->debug_flags
& DBG(TEST_DMA_PERF
)) {
1137 si_test_dma_perf(sscreen
);
1140 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1141 DBG(TEST_VMFAULT_SDMA
) |
1142 DBG(TEST_VMFAULT_SHADER
)))
1143 si_test_vmfault(sscreen
);
1145 if (sscreen
->debug_flags
& DBG(TEST_GDS
))
1146 si_test_gds((struct si_context
*)sscreen
->aux_context
);
1148 if (sscreen
->debug_flags
& DBG(TEST_GDS_MM
)) {
1149 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1150 32 * 1024, 4, RADEON_DOMAIN_GDS
);
1152 if (sscreen
->debug_flags
& DBG(TEST_GDS_OA_MM
)) {
1153 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1154 4, 1, RADEON_DOMAIN_OA
);