2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
28 #include "radeon/radeon_llvm_emit.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/u_memory.h"
31 #include "vl/vl_decoder.h"
36 static void si_destroy_context(struct pipe_context
*context
)
38 struct si_context
*sctx
= (struct si_context
*)context
;
40 si_release_all_descriptors(sctx
);
42 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
43 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
44 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
45 r600_resource_reference(&sctx
->border_color_table
, NULL
);
46 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
47 sctx
->b
.ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
49 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
50 si_pm4_delete_state(sctx
, gs_rings
, sctx
->gs_rings
);
51 si_pm4_delete_state(sctx
, gs_onoff
, sctx
->gs_on
);
52 si_pm4_delete_state(sctx
, gs_onoff
, sctx
->gs_off
);
54 if (sctx
->pstipple_sampler_state
)
55 sctx
->b
.b
.delete_sampler_state(&sctx
->b
.b
, sctx
->pstipple_sampler_state
);
56 if (sctx
->dummy_pixel_shader
) {
57 sctx
->b
.b
.delete_fs_state(&sctx
->b
.b
, sctx
->dummy_pixel_shader
);
59 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
60 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
61 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
62 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fastclear
);
63 util_unreference_framebuffer_state(&sctx
->framebuffer
.state
);
65 util_blitter_destroy(sctx
->blitter
);
69 r600_common_context_cleanup(&sctx
->b
);
71 #if HAVE_LLVM >= 0x0306
72 LLVMDisposeTargetMachine(sctx
->tm
);
78 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
, void *priv
)
80 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
81 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
82 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
83 LLVMTargetRef r600_target
;
84 #if HAVE_LLVM >= 0x0306
85 const char *triple
= "amdgcn--";
92 sctx
->b
.b
.screen
= screen
; /* this must be set first */
93 sctx
->b
.b
.priv
= priv
;
94 sctx
->b
.b
.destroy
= si_destroy_context
;
95 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
97 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
))
100 si_init_blit_functions(sctx
);
101 si_init_compute_functions(sctx
);
103 if (sscreen
->b
.info
.has_uvd
) {
104 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
105 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
107 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
108 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
111 sctx
->b
.rings
.gfx
.cs
= ws
->cs_create(ws
, RING_GFX
, si_context_gfx_flush
,
112 sctx
, sscreen
->b
.trace_bo
?
113 sscreen
->b
.trace_bo
->cs_buf
: NULL
);
114 sctx
->b
.rings
.gfx
.flush
= si_context_gfx_flush
;
116 si_init_all_descriptors(sctx
);
118 /* Initialize cache_flush. */
119 sctx
->cache_flush
= si_atom_cache_flush
;
120 sctx
->atoms
.s
.cache_flush
= &sctx
->cache_flush
;
122 sctx
->msaa_sample_locs
= si_atom_msaa_sample_locs
;
123 sctx
->atoms
.s
.msaa_sample_locs
= &sctx
->msaa_sample_locs
;
125 sctx
->msaa_config
= si_atom_msaa_config
;
126 sctx
->atoms
.s
.msaa_config
= &sctx
->msaa_config
;
128 sctx
->atoms
.s
.streamout_begin
= &sctx
->b
.streamout
.begin_atom
;
129 sctx
->atoms
.s
.streamout_enable
= &sctx
->b
.streamout
.enable_atom
;
131 switch (sctx
->b
.chip_class
) {
134 si_init_state_functions(sctx
);
135 si_init_shader_functions(sctx
);
136 si_init_config(sctx
);
139 R600_ERR("Unsupported chip class %d.\n", sctx
->b
.chip_class
);
143 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
144 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
146 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
147 if (sctx
->blitter
== NULL
)
149 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
151 /* these must be last */
152 si_begin_new_cs(sctx
);
153 r600_query_init_backend_mask(&sctx
->b
); /* this emits commands and must be last */
155 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
156 * with a NULL buffer). We need to use a dummy buffer instead. */
157 if (sctx
->b
.chip_class
== CIK
) {
158 sctx
->null_const_buf
.buffer
= pipe_buffer_create(screen
, PIPE_BIND_CONSTANT_BUFFER
,
159 PIPE_USAGE_DEFAULT
, 16);
160 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
162 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
163 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
164 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
165 &sctx
->null_const_buf
);
169 /* Clear the NULL constant buffer, because loads should return zeros. */
170 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
171 sctx
->null_const_buf
.buffer
->width0
, 0, false);
174 /* XXX: This is the maximum value allowed. I'm not sure how to compute
175 * this for non-cs shaders. Using the wrong value here can result in
176 * GPU lockups, but the maximum value seems to always work.
178 sctx
->scratch_waves
= 32 * sscreen
->b
.info
.max_compute_units
;
180 #if HAVE_LLVM >= 0x0306
181 /* Initialize LLVM TargetMachine */
182 r600_target
= radeon_llvm_get_r600_target(triple
);
183 sctx
->tm
= LLVMCreateTargetMachine(r600_target
, triple
,
184 r600_get_llvm_processor_name(sscreen
->b
.family
),
185 "+DumpCode,+vgpr-spilling",
186 LLVMCodeGenLevelDefault
,
188 LLVMCodeModelDefault
);
193 si_destroy_context(&sctx
->b
.b
);
201 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
203 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
206 /* Supported features (boolean caps). */
207 case PIPE_CAP_TWO_SIDED_STENCIL
:
208 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
209 case PIPE_CAP_ANISOTROPIC_FILTER
:
210 case PIPE_CAP_POINT_SPRITE
:
211 case PIPE_CAP_OCCLUSION_QUERY
:
212 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
213 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
214 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
215 case PIPE_CAP_TEXTURE_SWIZZLE
:
216 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
217 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
218 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
219 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
220 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
221 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
222 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
224 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
225 case PIPE_CAP_PRIMITIVE_RESTART
:
226 case PIPE_CAP_CONDITIONAL_RENDER
:
227 case PIPE_CAP_TEXTURE_BARRIER
:
228 case PIPE_CAP_INDEP_BLEND_ENABLE
:
229 case PIPE_CAP_INDEP_BLEND_FUNC
:
230 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
231 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
232 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
233 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
234 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
235 case PIPE_CAP_USER_INDEX_BUFFERS
:
236 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
237 case PIPE_CAP_START_INSTANCE
:
238 case PIPE_CAP_NPOT_TEXTURES
:
239 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
240 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
241 case PIPE_CAP_TGSI_INSTANCEID
:
242 case PIPE_CAP_COMPUTE
:
243 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
244 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
245 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
246 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
247 case PIPE_CAP_CUBE_MAP_ARRAY
:
248 case PIPE_CAP_SAMPLE_SHADING
:
249 case PIPE_CAP_DRAW_INDIRECT
:
250 case PIPE_CAP_CLIP_HALFZ
:
251 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
252 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
253 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
254 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
255 case PIPE_CAP_TGSI_TEXCOORD
:
258 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
259 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
261 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
262 return sscreen
->b
.info
.drm_major
== 2 && sscreen
->b
.info
.drm_minor
>= 43;
264 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
265 /* 2D tiling on CIK is supported since DRM 2.35.0 */
266 return sscreen
->b
.chip_class
< CIK
||
267 sscreen
->b
.info
.drm_minor
>= 35;
269 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
270 return R600_MAP_BUFFER_ALIGNMENT
;
272 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
273 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
276 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
279 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
280 return MIN2(sscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
282 case PIPE_CAP_TEXTURE_QUERY_LOD
:
283 case PIPE_CAP_TEXTURE_GATHER_SM5
:
284 return HAVE_LLVM
>= 0x0305;
285 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
286 return HAVE_LLVM
>= 0x0305 ? 4 : 0;
288 /* Unsupported features. */
289 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
290 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
291 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
292 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
293 case PIPE_CAP_USER_VERTEX_BUFFERS
:
294 case PIPE_CAP_FAKE_SW_MSAA
:
295 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
296 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
297 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
298 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
299 case PIPE_CAP_VERTEXID_NOBASE
:
302 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
303 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
306 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
307 return sscreen
->b
.has_streamout
? 4 : 0;
308 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
309 return sscreen
->b
.has_streamout
? 1 : 0;
310 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
311 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
312 return sscreen
->b
.has_streamout
? 32*4 : 0;
314 /* Geometry shader output. */
315 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
317 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
319 case PIPE_CAP_MAX_VERTEX_STREAMS
:
322 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
326 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
327 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
328 return 15; /* 16384 */
329 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
330 /* textures support 8192, but layered rendering supports 2048 */
332 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
333 /* textures support 8192, but layered rendering supports 2048 */
336 /* Render targets. */
337 case PIPE_CAP_MAX_RENDER_TARGETS
:
340 case PIPE_CAP_MAX_VIEWPORTS
:
343 /* Timer queries, present when the clock frequency is non zero. */
344 case PIPE_CAP_QUERY_TIMESTAMP
:
345 case PIPE_CAP_QUERY_TIME_ELAPSED
:
346 return sscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
348 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
349 case PIPE_CAP_MIN_TEXEL_OFFSET
:
352 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
353 case PIPE_CAP_MAX_TEXEL_OFFSET
:
356 case PIPE_CAP_ENDIANNESS
:
357 return PIPE_ENDIAN_LITTLE
;
359 case PIPE_CAP_VENDOR_ID
:
361 case PIPE_CAP_DEVICE_ID
:
362 return sscreen
->b
.info
.pci_id
;
363 case PIPE_CAP_ACCELERATED
:
365 case PIPE_CAP_VIDEO_MEMORY
:
366 return sscreen
->b
.info
.vram_size
>> 20;
373 static int si_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
377 case PIPE_SHADER_FRAGMENT
:
378 case PIPE_SHADER_VERTEX
:
379 case PIPE_SHADER_GEOMETRY
:
381 case PIPE_SHADER_COMPUTE
:
383 case PIPE_SHADER_CAP_PREFERRED_IR
:
384 #if HAVE_LLVM < 0x0306
385 return PIPE_SHADER_IR_LLVM
;
387 return PIPE_SHADER_IR_NATIVE
;
389 case PIPE_SHADER_CAP_DOUBLES
:
390 return HAVE_LLVM
>= 0x0307;
392 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
393 uint64_t max_const_buffer_size
;
394 pscreen
->get_compute_param(pscreen
,
395 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
396 &max_const_buffer_size
);
397 return max_const_buffer_size
;
400 /* If compute shaders don't require a special value
401 * for this cap, we can return the same value we
402 * do for other shader types. */
407 /* TODO: support tessellation */
412 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
413 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
414 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
415 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
417 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
419 case PIPE_SHADER_CAP_MAX_INPUTS
:
420 return shader
== PIPE_SHADER_VERTEX
? SI_NUM_VERTEX_BUFFERS
: 32;
421 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
422 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
423 case PIPE_SHADER_CAP_MAX_TEMPS
:
424 return 256; /* Max native temporaries. */
425 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
426 return 4096 * sizeof(float[4]); /* actually only memory limits this */
427 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
428 return SI_NUM_USER_CONST_BUFFERS
;
429 case PIPE_SHADER_CAP_MAX_PREDS
:
430 return 0; /* FIXME */
431 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
433 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
435 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
436 /* Indirection of geometry shader input dimension is not
439 return shader
< PIPE_SHADER_GEOMETRY
;
440 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
441 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
442 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
444 case PIPE_SHADER_CAP_INTEGERS
:
446 case PIPE_SHADER_CAP_SUBROUTINES
:
448 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
449 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
451 case PIPE_SHADER_CAP_PREFERRED_IR
:
452 return PIPE_SHADER_IR_TGSI
;
453 case PIPE_SHADER_CAP_DOUBLES
:
454 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
455 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
457 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
458 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
464 static void si_destroy_screen(struct pipe_screen
* pscreen
)
466 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
471 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
474 r600_destroy_common_screen(&sscreen
->b
);
477 #define SI_TILE_MODE_COLOR_2D_8BPP 14
479 /* Initialize pipe config. This is especially important for GPUs
480 * with 16 pipes and more where it's initialized incorrectly by
481 * the TILING_CONFIG ioctl. */
482 static bool si_initialize_pipe_config(struct si_screen
*sscreen
)
486 /* This is okay, because there can be no 2D tiling without
487 * the tile mode array, so we won't need the pipe config.
490 if (!sscreen
->b
.info
.si_tile_mode_array_valid
)
493 /* The same index is used for the 2D mode on CIK too. */
494 mode2d
= sscreen
->b
.info
.si_tile_mode_array
[SI_TILE_MODE_COLOR_2D_8BPP
];
496 switch (G_009910_PIPE_CONFIG(mode2d
)) {
497 case V_02803C_ADDR_SURF_P2
:
498 sscreen
->b
.tiling_info
.num_channels
= 2;
500 case V_02803C_X_ADDR_SURF_P4_8X16
:
501 case V_02803C_X_ADDR_SURF_P4_16X16
:
502 case V_02803C_X_ADDR_SURF_P4_16X32
:
503 case V_02803C_X_ADDR_SURF_P4_32X32
:
504 sscreen
->b
.tiling_info
.num_channels
= 4;
506 case V_02803C_X_ADDR_SURF_P8_16X16_8X16
:
507 case V_02803C_X_ADDR_SURF_P8_16X32_8X16
:
508 case V_02803C_X_ADDR_SURF_P8_32X32_8X16
:
509 case V_02803C_X_ADDR_SURF_P8_16X32_16X16
:
510 case V_02803C_X_ADDR_SURF_P8_32X32_16X16
:
511 case V_02803C_X_ADDR_SURF_P8_32X32_16X32
:
512 case V_02803C_X_ADDR_SURF_P8_32X64_32X32
:
513 sscreen
->b
.tiling_info
.num_channels
= 8;
515 case V_02803C_X_ADDR_SURF_P16_32X32_8X16
:
516 case V_02803C_X_ADDR_SURF_P16_32X32_16X16
:
517 sscreen
->b
.tiling_info
.num_channels
= 16;
521 fprintf(stderr
, "radeonsi: Unknown pipe config %i.\n",
522 G_009910_PIPE_CONFIG(mode2d
));
528 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
530 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
532 if (sscreen
== NULL
) {
536 /* Set functions first. */
537 sscreen
->b
.b
.context_create
= si_create_context
;
538 sscreen
->b
.b
.destroy
= si_destroy_screen
;
539 sscreen
->b
.b
.get_param
= si_get_param
;
540 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
541 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
542 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
544 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
545 !si_initialize_pipe_config(sscreen
)) {
550 sscreen
->b
.has_cp_dma
= true;
551 sscreen
->b
.has_streamout
= true;
553 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE
))
554 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
556 /* Create the auxiliary context. This must be done last. */
557 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
);
559 return &sscreen
->b
.b
;