src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "util/u_tests.h"
  34 #include "vl/vl_decoder.h"
  35 #include "../ddebug/dd_util.h"
  36
  37 /*
  38  * pipe_context
  39  */
  40 static void si_destroy_context(struct pipe_context *context)
  41 {
  42         struct si_context *sctx = (struct si_context *)context;
  43         int i;
  44
  45         /* Unreference the framebuffer normally to disable related logic
  46          * properly.
  47          */
  48         struct pipe_framebuffer_state fb = {};
  49         if (context->set_framebuffer_state)
  50                 context->set_framebuffer_state(context, &fb);
  51
  52         si_release_all_descriptors(sctx);
  53
  54         if (sctx->ce_suballocator)
  55                 u_suballocator_destroy(sctx->ce_suballocator);
  56
  57         r600_resource_reference(&sctx->ce_ram_saved_buffer, NULL);
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_fmask_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  83         if (sctx->custom_blend_eliminate_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87
  88         if (sctx->blitter)
  89                 util_blitter_destroy(sctx->blitter);
  90
  91         r600_common_context_cleanup(&sctx->b);
  92
  93         LLVMDisposeTargetMachine(sctx->tm);
  94
  95         r600_resource_reference(&sctx->trace_buf, NULL);
  96         r600_resource_reference(&sctx->last_trace_buf, NULL);
  97         radeon_clear_saved_cs(&sctx->last_gfx);
  98
  99         pb_slabs_deinit(&sctx->bindless_descriptor_slabs);
 100         util_dynarray_fini(&sctx->bindless_descriptors);
 101
 102         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 103         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 104
 105         util_dynarray_fini(&sctx->resident_tex_handles);
 106         util_dynarray_fini(&sctx->resident_img_handles);
 107         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 108         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 109         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 110         FREE(sctx);
 111 }
 112
 113 static enum pipe_reset_status
 114 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 115 {
 116         struct si_context *sctx = (struct si_context *)ctx;
 117
 118         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 119 }
 120
 121 /* Apitrace profiling:
 122  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 123  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 124  *      and remember its number.
 125  *   3) In Mesa, enable queries and performance counters around that draw
 126  *      call and print the results.
 127  *   4) glretrace --benchmark --markers ..
 128  */
 129 static void si_emit_string_marker(struct pipe_context *ctx,
 130                                   const char *string, int len)
 131 {
 132         struct si_context *sctx = (struct si_context *)ctx;
 133
 134         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 135 }
 136
 137 static LLVMTargetMachineRef
 138 si_create_llvm_target_machine(struct si_screen *sscreen)
 139 {
 140         const char *triple = "amdgcn--";
 141         char features[256];
 142
 143         snprintf(features, sizeof(features),
 144                  "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
 145                  sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
 146                  sscreen->llvm_has_working_vgpr_indexing ? "" : ",-promote-alloca",
 147                  sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
 148
 149         return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
 150                                        r600_get_llvm_processor_name(sscreen->b.family),
 151                                        features,
 152                                        LLVMCodeGenLevelDefault,
 153                                        LLVMRelocDefault,
 154                                        LLVMCodeModelDefault);
 155 }
 156
 157 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 158                                               unsigned flags)
 159 {
 160         struct si_context *sctx = CALLOC_STRUCT(si_context);
 161         struct si_screen* sscreen = (struct si_screen *)screen;
 162         struct radeon_winsys *ws = sscreen->b.ws;
 163         int shader, i;
 164
 165         if (!sctx)
 166                 return NULL;
 167
 168         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 169                 flags |= PIPE_CONTEXT_DEBUG;
 170
 171         if (flags & PIPE_CONTEXT_DEBUG)
 172                 sscreen->record_llvm_ir = true; /* racy but not critical */
 173
 174         sctx->b.b.screen = screen; /* this must be set first */
 175         sctx->b.b.priv = NULL;
 176         sctx->b.b.destroy = si_destroy_context;
 177         sctx->b.b.emit_string_marker = si_emit_string_marker;
 178         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 179         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 180         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 181
 182         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 183                 goto fail;
 184
 185         if (sscreen->b.info.drm_major == 3)
 186                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 187
 188         si_init_blit_functions(sctx);
 189         si_init_compute_functions(sctx);
 190         si_init_cp_dma_functions(sctx);
 191         si_init_debug_functions(sctx);
 192
 193         if (sscreen->b.info.has_hw_decode) {
 194                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 195                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 196         } else {
 197                 sctx->b.b.create_video_codec = vl_create_decoder;
 198                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 199         }
 200
 201         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 202                                        si_context_gfx_flush, sctx);
 203
 204         /* SI + AMDGPU + CE = GPU hang */
 205         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
 206             sscreen->b.chip_class != SI &&
 207             /* These can't use CE due to a power gating bug in the kernel. */
 208             sscreen->b.family != CHIP_CARRIZO &&
 209             sscreen->b.family != CHIP_STONEY) {
 210                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 211                 if (!sctx->ce_ib)
 212                         goto fail;
 213
 214                 if (ws->cs_add_const_preamble_ib) {
 215                         sctx->ce_preamble_ib =
 216                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 217
 218                         if (!sctx->ce_preamble_ib)
 219                                 goto fail;
 220                 }
 221
 222                 sctx->ce_suballocator =
 223                         u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
 224                                               PIPE_USAGE_DEFAULT,
 225                                               R600_RESOURCE_FLAG_UNMAPPABLE, false);
 226                 if (!sctx->ce_suballocator)
 227                         goto fail;
 228         }
 229
 230         sctx->b.gfx.flush = si_context_gfx_flush;
 231
 232         /* Border colors. */
 233         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 234                                           sizeof(*sctx->border_color_table));
 235         if (!sctx->border_color_table)
 236                 goto fail;
 237
 238         sctx->border_color_buffer = (struct r600_resource*)
 239                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 240                                    SI_MAX_BORDER_COLORS *
 241                                    sizeof(*sctx->border_color_table));
 242         if (!sctx->border_color_buffer)
 243                 goto fail;
 244
 245         sctx->border_color_map =
 246                 ws->buffer_map(sctx->border_color_buffer->buf,
 247                                NULL, PIPE_TRANSFER_WRITE);
 248         if (!sctx->border_color_map)
 249                 goto fail;
 250
 251         si_init_all_descriptors(sctx);
 252         si_init_state_functions(sctx);
 253         si_init_shader_functions(sctx);
 254         si_init_ia_multi_vgt_param_table(sctx);
 255
 256         if (sctx->b.chip_class >= CIK)
 257                 cik_init_sdma_functions(sctx);
 258         else
 259                 si_init_dma_functions(sctx);
 260
 261         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 262                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 263
 264         sctx->blitter = util_blitter_create(&sctx->b.b);
 265         if (sctx->blitter == NULL)
 266                 goto fail;
 267         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 268
 269         sctx->sample_mask.sample_mask = 0xffff;
 270
 271         /* these must be last */
 272         si_begin_new_cs(sctx);
 273
 274         if (sctx->b.chip_class >= GFX9) {
 275                 sctx->wait_mem_scratch = (struct r600_resource*)
 276                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 277                 if (!sctx->wait_mem_scratch)
 278                         goto fail;
 279
 280                 /* Initialize the memory. */
 281                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 282                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 283                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 284                             S_370_WR_CONFIRM(1) |
 285                             S_370_ENGINE_SEL(V_370_ME));
 286                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 287                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 288                 radeon_emit(cs, sctx->wait_mem_number);
 289         }
 290
 291         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 292          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 293         if (sctx->b.chip_class == CIK) {
 294                 sctx->null_const_buf.buffer =
 295                         r600_aligned_buffer_create(screen,
 296                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 297                                                    PIPE_USAGE_DEFAULT, 16,
 298                                                    sctx->screen->b.info.tcc_cache_line_size);
 299                 if (!sctx->null_const_buf.buffer)
 300                         goto fail;
 301                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 302
 303                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 304                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 305                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 306                                                               &sctx->null_const_buf);
 307                         }
 308                 }
 309
 310                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 311                                  &sctx->null_const_buf);
 312                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 313                                  &sctx->null_const_buf);
 314                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 315                                  &sctx->null_const_buf);
 316                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 317                                  &sctx->null_const_buf);
 318                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 319                                  &sctx->null_const_buf);
 320
 321                 /* Clear the NULL constant buffer, because loads should return zeros. */
 322                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 323                                      sctx->null_const_buf.buffer->width0, 0,
 324                                      R600_COHERENCY_SHADER);
 325         }
 326
 327         uint64_t max_threads_per_block;
 328         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 329                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 330                                   &max_threads_per_block);
 331
 332         /* The maximum number of scratch waves. Scratch space isn't divided
 333          * evenly between CUs. The number is only a function of the number of CUs.
 334          * We can decrease the constant to decrease the scratch buffer size.
 335          *
 336          * sctx->scratch_waves must be >= the maximum posible size of
 337          * 1 threadgroup, so that the hw doesn't hang from being unable
 338          * to start any.
 339          *
 340          * The recommended value is 4 per CU at most. Higher numbers don't
 341          * bring much benefit, but they still occupy chip resources (think
 342          * async compute). I've seen ~2% performance difference between 4 and 32.
 343          */
 344         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 345                                    max_threads_per_block / 64);
 346
 347         sctx->tm = si_create_llvm_target_machine(sscreen);
 348
 349         /* Create a slab allocator for all bindless descriptors. */
 350         if (!pb_slabs_init(&sctx->bindless_descriptor_slabs, 6, 6, 1, sctx,
 351                            si_bindless_descriptor_can_reclaim_slab,
 352                            si_bindless_descriptor_slab_alloc,
 353                            si_bindless_descriptor_slab_free))
 354                 goto fail;
 355
 356         util_dynarray_init(&sctx->bindless_descriptors, NULL);
 357
 358         /* Bindless handles. */
 359         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 360                                                     _mesa_key_pointer_equal);
 361         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 362                                                     _mesa_key_pointer_equal);
 363
 364         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 365         util_dynarray_init(&sctx->resident_img_handles, NULL);
 366         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 367         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 368         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 369
 370         return &sctx->b.b;
 371 fail:
 372         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 373         si_destroy_context(&sctx->b.b);
 374         return NULL;
 375 }
 376
 377 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 378                                                    void *priv, unsigned flags)
 379 {
 380         struct si_screen *sscreen = (struct si_screen *)screen;
 381         struct pipe_context *ctx = si_create_context(screen, flags);
 382
 383         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 384                 return ctx;
 385
 386         /* Clover (compute-only) is unsupported.
 387          *
 388          * Since the threaded context creates shader states from the non-driver
 389          * thread, asynchronous compilation is required for create_{shader}_-
 390          * state not to use pipe_context. Debug contexts (ddebug) disable
 391          * asynchronous compilation, so don't use the threaded context with
 392          * those.
 393          */
 394         if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
 395                 return ctx;
 396
 397         /* When shaders are logged to stderr, asynchronous compilation is
 398          * disabled too. */
 399         if (sscreen->b.debug_flags & (DBG_VS | DBG_TCS | DBG_TES | DBG_GS |
 400                                       DBG_PS | DBG_CS))
 401                 return ctx;
 402
 403         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 404                                        r600_replace_buffer_storage,
 405                                        &((struct si_context*)ctx)->b.tc);
 406 }
 407
 408 /*
 409  * pipe_screen
 410  */
 411 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 412 {
 413         /* Old kernels disallowed some register writes for SI
 414          * that are used for indirect dispatches. */
 415         return (sscreen->b.chip_class >= CIK ||
 416                 sscreen->b.info.drm_major == 3 ||
 417                 (sscreen->b.info.drm_major == 2 &&
 418                  sscreen->b.info.drm_minor >= 45));
 419 }
 420
 421 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 422 {
 423         struct si_screen *sscreen = (struct si_screen *)pscreen;
 424
 425         switch (param) {
 426         /* Supported features (boolean caps). */
 427         case PIPE_CAP_ACCELERATED:
 428         case PIPE_CAP_TWO_SIDED_STENCIL:
 429         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 430         case PIPE_CAP_ANISOTROPIC_FILTER:
 431         case PIPE_CAP_POINT_SPRITE:
 432         case PIPE_CAP_OCCLUSION_QUERY:
 433         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 434         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 435         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 436         case PIPE_CAP_TEXTURE_SWIZZLE:
 437         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 438         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 439         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 440         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 441         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 442         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 443         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 444         case PIPE_CAP_SM3:
 445         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 446         case PIPE_CAP_PRIMITIVE_RESTART:
 447         case PIPE_CAP_CONDITIONAL_RENDER:
 448         case PIPE_CAP_TEXTURE_BARRIER:
 449         case PIPE_CAP_INDEP_BLEND_ENABLE:
 450         case PIPE_CAP_INDEP_BLEND_FUNC:
 451         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 452         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 453         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 454         case PIPE_CAP_START_INSTANCE:
 455         case PIPE_CAP_NPOT_TEXTURES:
 456         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 457         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 458         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 459         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 460         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 461         case PIPE_CAP_TGSI_INSTANCEID:
 462         case PIPE_CAP_COMPUTE:
 463         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 464         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 465         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 466         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 467         case PIPE_CAP_CUBE_MAP_ARRAY:
 468         case PIPE_CAP_SAMPLE_SHADING:
 469         case PIPE_CAP_DRAW_INDIRECT:
 470         case PIPE_CAP_CLIP_HALFZ:
 471         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 472         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 473         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 474         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 475         case PIPE_CAP_TGSI_TEXCOORD:
 476         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 477         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 478         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 479         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 480         case PIPE_CAP_SHAREABLE_SHADERS:
 481         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 482         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 483         case PIPE_CAP_TEXTURE_QUERY_LOD:
 484         case PIPE_CAP_TEXTURE_GATHER_SM5:
 485         case PIPE_CAP_TGSI_TXQS:
 486         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 487         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 488         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 489         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 490         case PIPE_CAP_INVALIDATE_BUFFER:
 491         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 492         case PIPE_CAP_QUERY_MEMORY_INFO:
 493         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 494         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 495         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 496         case PIPE_CAP_GENERATE_MIPMAP:
 497         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 498         case PIPE_CAP_STRING_MARKER:
 499         case PIPE_CAP_CLEAR_TEXTURE:
 500         case PIPE_CAP_CULL_DISTANCE:
 501         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 502         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 503         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 504         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 505         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 506         case PIPE_CAP_DOUBLES:
 507         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 508         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 509         case PIPE_CAP_BINDLESS_TEXTURE:
 510                 return 1;
 511
 512         case PIPE_CAP_INT64:
 513         case PIPE_CAP_INT64_DIVMOD:
 514         case PIPE_CAP_TGSI_CLOCK:
 515         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 516         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 517                 return 1;
 518
 519         case PIPE_CAP_TGSI_VOTE:
 520                 return HAVE_LLVM >= 0x0400;
 521
 522         case PIPE_CAP_TGSI_BALLOT:
 523                 return HAVE_LLVM >= 0x0500;
 524
 525         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 526                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 527
 528         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 529                 return (sscreen->b.info.drm_major == 2 &&
 530                         sscreen->b.info.drm_minor >= 43) ||
 531                        sscreen->b.info.drm_major == 3;
 532
 533         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 534                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 535                 return sscreen->b.chip_class < CIK ||
 536                        (sscreen->b.info.drm_major == 2 &&
 537                         sscreen->b.info.drm_minor >= 35) ||
 538                        sscreen->b.info.drm_major == 3;
 539
 540         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 541                 return R600_MAP_BUFFER_ALIGNMENT;
 542
 543         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 544         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 545         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 546         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 547         case PIPE_CAP_MAX_VERTEX_STREAMS:
 548         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 549                 return 4;
 550
 551         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 552                 if (si_have_tgsi_compute(sscreen))
 553                         return 450;
 554                 return 420;
 555
 556         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 557                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 558
 559         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 560         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 561         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 562                 /* SI doesn't support unaligned loads.
 563                  * CIK needs DRM 2.50.0 on radeon. */
 564                 return sscreen->b.chip_class == SI ||
 565                        (sscreen->b.info.drm_major == 2 &&
 566                         sscreen->b.info.drm_minor < 50);
 567
 568         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 569                 /* TODO: GFX9 hangs. */
 570                 if (sscreen->b.chip_class >= GFX9)
 571                         return 0;
 572                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 573                  * faults are mitigated in software.
 574                  */
 575                 if (sscreen->b.chip_class >= CIK &&
 576                     sscreen->b.info.drm_major == 3 &&
 577                     sscreen->b.info.drm_minor >= 13)
 578                         return RADEON_SPARSE_PAGE_SIZE;
 579                 return 0;
 580
 581         /* Unsupported features. */
 582         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 583         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 584         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 585         case PIPE_CAP_USER_VERTEX_BUFFERS:
 586         case PIPE_CAP_FAKE_SW_MSAA:
 587         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 588         case PIPE_CAP_VERTEXID_NOBASE:
 589         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 590         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 591         case PIPE_CAP_NATIVE_FENCE_FD:
 592         case PIPE_CAP_TGSI_FS_FBFETCH:
 593         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 594         case PIPE_CAP_UMA:
 595         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 596         case PIPE_CAP_POST_DEPTH_COVERAGE:
 597                 return 0;
 598
 599         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 600                 return si_have_tgsi_compute(sscreen);
 601
 602         case PIPE_CAP_DRAW_PARAMETERS:
 603         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 604         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 605                 return sscreen->has_draw_indirect_multi;
 606
 607         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 608                 return 30;
 609
 610         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 611                 return sscreen->b.chip_class <= VI ?
 612                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 613
 614         /* Stream output. */
 615         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 616         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 617                 return 32*4;
 618
 619         /* Geometry shader output. */
 620         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 621                 return 1024;
 622         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 623                 return 4095;
 624
 625         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 626                 return 2048;
 627
 628         /* Texturing. */
 629         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 630         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 631                 return 15; /* 16384 */
 632         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 633                 /* textures support 8192, but layered rendering supports 2048 */
 634                 return 12;
 635         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 636                 /* textures support 8192, but layered rendering supports 2048 */
 637                 return 2048;
 638
 639         /* Viewports and render targets. */
 640         case PIPE_CAP_MAX_VIEWPORTS:
 641                 return R600_MAX_VIEWPORTS;
 642         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 643         case PIPE_CAP_MAX_RENDER_TARGETS:
 644                 return 8;
 645
 646         /* Timer queries, present when the clock frequency is non zero. */
 647         case PIPE_CAP_QUERY_TIMESTAMP:
 648         case PIPE_CAP_QUERY_TIME_ELAPSED:
 649                 return sscreen->b.info.clock_crystal_freq != 0;
 650
 651         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 652         case PIPE_CAP_MIN_TEXEL_OFFSET:
 653                 return -32;
 654
 655         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 656         case PIPE_CAP_MAX_TEXEL_OFFSET:
 657                 return 31;
 658
 659         case PIPE_CAP_ENDIANNESS:
 660                 return PIPE_ENDIAN_LITTLE;
 661
 662         case PIPE_CAP_VENDOR_ID:
 663                 return ATI_VENDOR_ID;
 664         case PIPE_CAP_DEVICE_ID:
 665                 return sscreen->b.info.pci_id;
 666         case PIPE_CAP_VIDEO_MEMORY:
 667                 return sscreen->b.info.vram_size >> 20;
 668         case PIPE_CAP_PCI_GROUP:
 669                 return sscreen->b.info.pci_domain;
 670         case PIPE_CAP_PCI_BUS:
 671                 return sscreen->b.info.pci_bus;
 672         case PIPE_CAP_PCI_DEVICE:
 673                 return sscreen->b.info.pci_dev;
 674         case PIPE_CAP_PCI_FUNCTION:
 675                 return sscreen->b.info.pci_func;
 676         }
 677         return 0;
 678 }
 679
 680 static int si_get_shader_param(struct pipe_screen* pscreen,
 681                                enum pipe_shader_type shader,
 682                                enum pipe_shader_cap param)
 683 {
 684         struct si_screen *sscreen = (struct si_screen *)pscreen;
 685
 686         switch(shader)
 687         {
 688         case PIPE_SHADER_FRAGMENT:
 689         case PIPE_SHADER_VERTEX:
 690         case PIPE_SHADER_GEOMETRY:
 691         case PIPE_SHADER_TESS_CTRL:
 692         case PIPE_SHADER_TESS_EVAL:
 693                 break;
 694         case PIPE_SHADER_COMPUTE:
 695                 switch (param) {
 696                 case PIPE_SHADER_CAP_PREFERRED_IR:
 697                         return PIPE_SHADER_IR_NATIVE;
 698
 699                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 700                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 701
 702                         if (si_have_tgsi_compute(sscreen))
 703                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 704
 705                         return ir;
 706                 }
 707
 708                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 709                         uint64_t max_const_buffer_size;
 710                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 711                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 712                                 &max_const_buffer_size);
 713                         return MIN2(max_const_buffer_size, INT_MAX);
 714                 }
 715                 default:
 716                         /* If compute shaders don't require a special value
 717                          * for this cap, we can return the same value we
 718                          * do for other shader types. */
 719                         break;
 720                 }
 721                 break;
 722         default:
 723                 return 0;
 724         }
 725
 726         switch (param) {
 727         /* Shader limits. */
 728         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 729         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 730         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 731         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 732         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 733                 return 16384;
 734         case PIPE_SHADER_CAP_MAX_INPUTS:
 735                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 736         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 737                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 738         case PIPE_SHADER_CAP_MAX_TEMPS:
 739                 return 256; /* Max native temporaries. */
 740         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 741                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 742         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 743                 return SI_NUM_CONST_BUFFERS;
 744         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 745         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 746                 return SI_NUM_SAMPLERS;
 747         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 748                 return SI_NUM_SHADER_BUFFERS;
 749         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 750                 return SI_NUM_IMAGES;
 751         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 752                 return 32;
 753         case PIPE_SHADER_CAP_PREFERRED_IR:
 754                 return PIPE_SHADER_IR_TGSI;
 755         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 756                 return 3;
 757
 758         /* Supported boolean features. */
 759         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 760         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 761         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 762         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 763         case PIPE_SHADER_CAP_INTEGERS:
 764         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 765         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 766         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 767                 return 1;
 768
 769         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 770                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 771                 return shader != PIPE_SHADER_GEOMETRY &&
 772                        (sscreen->llvm_has_working_vgpr_indexing ||
 773                         /* TCS and TES load inputs directly from LDS or
 774                          * offchip memory, so indirect indexing is trivial. */
 775                         shader == PIPE_SHADER_TESS_CTRL ||
 776                         shader == PIPE_SHADER_TESS_EVAL);
 777
 778         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 779                 return sscreen->llvm_has_working_vgpr_indexing ||
 780                        /* TCS stores outputs directly to memory. */
 781                        shader == PIPE_SHADER_TESS_CTRL;
 782
 783         /* Unsupported boolean features. */
 784         case PIPE_SHADER_CAP_SUBROUTINES:
 785         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 786         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 787         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 788                 return 0;
 789         }
 790         return 0;
 791 }
 792
 793 static void si_destroy_screen(struct pipe_screen* pscreen)
 794 {
 795         struct si_screen *sscreen = (struct si_screen *)pscreen;
 796         struct si_shader_part *parts[] = {
 797                 sscreen->vs_prologs,
 798                 sscreen->tcs_epilogs,
 799                 sscreen->gs_prologs,
 800                 sscreen->ps_prologs,
 801                 sscreen->ps_epilogs
 802         };
 803         unsigned i;
 804
 805         if (!sscreen->b.ws->unref(sscreen->b.ws))
 806                 return;
 807
 808         util_queue_destroy(&sscreen->shader_compiler_queue);
 809         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 810
 811         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 812                 if (sscreen->tm[i])
 813                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 814
 815         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 816                 if (sscreen->tm_low_priority[i])
 817                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 818
 819         /* Free shader parts. */
 820         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 821                 while (parts[i]) {
 822                         struct si_shader_part *part = parts[i];
 823
 824                         parts[i] = part->next;
 825                         radeon_shader_binary_clean(&part->binary);
 826                         FREE(part);
 827                 }
 828         }
 829         mtx_destroy(&sscreen->shader_parts_mutex);
 830         si_destroy_shader_cache(sscreen);
 831         r600_destroy_common_screen(&sscreen->b);
 832 }
 833
 834 static bool si_init_gs_info(struct si_screen *sscreen)
 835 {
 836         switch (sscreen->b.family) {
 837         case CHIP_OLAND:
 838         case CHIP_HAINAN:
 839         case CHIP_KAVERI:
 840         case CHIP_KABINI:
 841         case CHIP_MULLINS:
 842         case CHIP_ICELAND:
 843         case CHIP_CARRIZO:
 844         case CHIP_STONEY:
 845                 sscreen->gs_table_depth = 16;
 846                 return true;
 847         case CHIP_TAHITI:
 848         case CHIP_PITCAIRN:
 849         case CHIP_VERDE:
 850         case CHIP_BONAIRE:
 851         case CHIP_HAWAII:
 852         case CHIP_TONGA:
 853         case CHIP_FIJI:
 854         case CHIP_POLARIS10:
 855         case CHIP_POLARIS11:
 856         case CHIP_POLARIS12:
 857         case CHIP_VEGA10:
 858         case CHIP_RAVEN:
 859                 sscreen->gs_table_depth = 32;
 860                 return true;
 861         default:
 862                 return false;
 863         }
 864 }
 865
 866 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 867 {
 868         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 869         unsigned i;
 870
 871         if (!family)
 872                 return;
 873
 874         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 875                 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
 876                         /* Override family and chip_class. */
 877                         sscreen->b.family = sscreen->b.info.family = i;
 878
 879                         if (i >= CHIP_VEGA10)
 880                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 881                         else if (i >= CHIP_TONGA)
 882                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 883                         else if (i >= CHIP_BONAIRE)
 884                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 885                         else
 886                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 887
 888                         /* Don't submit any IBs. */
 889                         setenv("RADEON_NOOP", "1", 1);
 890                         return;
 891                 }
 892         }
 893
 894         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 895         exit(1);
 896 }
 897
 898 static void si_test_vmfault(struct si_screen *sscreen)
 899 {
 900         struct pipe_context *ctx = sscreen->b.aux_context;
 901         struct si_context *sctx = (struct si_context *)ctx;
 902         struct pipe_resource *buf =
 903                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 904
 905         if (!buf) {
 906                 puts("Buffer allocation failed.");
 907                 exit(1);
 908         }
 909
 910         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 911
 912         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
 913                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 914                 ctx->flush(ctx, NULL, 0);
 915                 puts("VM fault test: CP - done.");
 916         }
 917         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
 918                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 919                 ctx->flush(ctx, NULL, 0);
 920                 puts("VM fault test: SDMA - done.");
 921         }
 922         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
 923                 util_test_constant_buffer(ctx, buf);
 924                 puts("VM fault test: Shader - done.");
 925         }
 926         exit(0);
 927 }
 928
 929 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 930                                            unsigned flags)
 931 {
 932         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 933         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 934
 935         if (!sscreen) {
 936                 return NULL;
 937         }
 938
 939         /* Set functions first. */
 940         sscreen->b.b.context_create = si_pipe_create_context;
 941         sscreen->b.b.destroy = si_destroy_screen;
 942         sscreen->b.b.get_param = si_get_param;
 943         sscreen->b.b.get_shader_param = si_get_shader_param;
 944         sscreen->b.b.resource_create = r600_resource_create_common;
 945
 946         si_init_screen_state_functions(sscreen);
 947
 948         if (!r600_common_screen_init(&sscreen->b, ws, flags) ||
 949             !si_init_gs_info(sscreen) ||
 950             !si_init_shader_cache(sscreen)) {
 951                 FREE(sscreen);
 952                 return NULL;
 953         }
 954
 955         /* Only enable as many threads as we have target machines, but at most
 956          * the number of CPUs - 1 if there is more than one.
 957          */
 958         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
 959         num_threads = MAX2(1, num_threads - 1);
 960         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
 961         num_compiler_threads_lowprio =
 962                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
 963
 964         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 965                              32, num_compiler_threads, 0)) {
 966                 si_destroy_shader_cache(sscreen);
 967                 FREE(sscreen);
 968                 return NULL;
 969         }
 970
 971         /* The queue must be large enough so that adding optimized shaders
 972          * doesn't stall draw calls when the queue is full. Especially varying
 973          * packing generates a very high volume of optimized shader compilation
 974          * jobs.
 975          */
 976         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
 977                              "si_shader_low",
 978                              1024, num_compiler_threads,
 979                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
 980                si_destroy_shader_cache(sscreen);
 981                FREE(sscreen);
 982                return NULL;
 983         }
 984
 985         si_handle_env_var_force_family(sscreen);
 986
 987         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 988                 si_init_perfcounters(sscreen);
 989
 990         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 991          * around by setting 4K granularity.
 992          */
 993         sscreen->tess_offchip_block_dw_size =
 994                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
 995
 996         sscreen->has_distributed_tess =
 997                 sscreen->b.chip_class >= VI &&
 998                 sscreen->b.info.max_se >= 2;
 999
1000         sscreen->has_draw_indirect_multi =
1001                 (sscreen->b.family >= CHIP_POLARIS10) ||
1002                 (sscreen->b.chip_class == VI &&
1003                  sscreen->b.info.pfp_fw_version >= 121 &&
1004                  sscreen->b.info.me_fw_version >= 87) ||
1005                 (sscreen->b.chip_class == CIK &&
1006                  sscreen->b.info.pfp_fw_version >= 211 &&
1007                  sscreen->b.info.me_fw_version >= 173) ||
1008                 (sscreen->b.chip_class == SI &&
1009                  sscreen->b.info.pfp_fw_version >= 121 &&
1010                  sscreen->b.info.me_fw_version >= 87);
1011
1012         sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
1013         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1014                                             sscreen->b.family <= CHIP_POLARIS12) ||
1015                                            sscreen->b.family == CHIP_VEGA10 ||
1016                                            sscreen->b.family == CHIP_RAVEN;
1017         /* While it would be nice not to have this flag, we are constrained
1018          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1019          * on GFX9.
1020          */
1021         sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1022
1023         sscreen->b.has_cp_dma = true;
1024         sscreen->b.has_streamout = true;
1025
1026         /* Some chips have RB+ registers, but don't support RB+. Those must
1027          * always disable it.
1028          */
1029         if (sscreen->b.family == CHIP_STONEY ||
1030             sscreen->b.chip_class >= GFX9) {
1031                 sscreen->b.has_rbplus = true;
1032
1033                 sscreen->b.rbplus_allowed =
1034                         !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
1035                         (sscreen->b.family == CHIP_STONEY ||
1036                          sscreen->b.family == CHIP_RAVEN);
1037         }
1038
1039         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1040         sscreen->use_monolithic_shaders =
1041                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
1042
1043         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1044                                             SI_CONTEXT_INV_VMEM_L1;
1045         if (sscreen->b.chip_class <= VI)
1046                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1047
1048         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1049
1050         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1051                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1052
1053         for (i = 0; i < num_compiler_threads; i++)
1054                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1055         for (i = 0; i < num_compiler_threads_lowprio; i++)
1056                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1057
1058         /* Create the auxiliary context. This must be done last. */
1059         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1060
1061         if (sscreen->b.debug_flags & DBG_TEST_DMA)
1062                 r600_test_dma(&sscreen->b);
1063
1064         if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
1065                                       DBG_TEST_VMFAULT_SDMA |
1066                                       DBG_TEST_VMFAULT_SHADER))
1067                 si_test_vmfault(sscreen);
1068
1069         return &sscreen->b.b;
1070 }