2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_MAX_POINT_SIZE 2048
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
56 /* Tunables for compute-based clear_buffer and copy_buffer: */
57 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
58 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
59 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61 /* Pipeline & streamout query controls. */
62 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
63 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
64 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
65 /* Instruction cache. */
66 #define SI_CONTEXT_INV_ICACHE (1 << 3)
67 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
68 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
69 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
70 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
71 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
72 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
73 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
74 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
75 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
76 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
77 * a CB or DB flush. */
78 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
79 /* Framebuffer caches. */
80 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
81 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
82 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
83 /* Engine synchronization. */
84 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
85 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
86 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
87 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
88 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
90 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
91 #define SI_PREFETCH_LS (1 << 1)
92 #define SI_PREFETCH_HS (1 << 2)
93 #define SI_PREFETCH_ES (1 << 3)
94 #define SI_PREFETCH_GS (1 << 4)
95 #define SI_PREFETCH_VS (1 << 5)
96 #define SI_PREFETCH_PS (1 << 6)
98 #define SI_MAX_BORDER_COLORS 4096
99 #define SI_MAX_VIEWPORTS 16
100 #define SIX_BITS 0x3F
101 #define SI_MAP_BUFFER_ALIGNMENT 64
102 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
104 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
105 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
106 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
107 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
108 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
109 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
110 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
111 #define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
115 /* Shader logging options: */
116 DBG_VS
= PIPE_SHADER_VERTEX
,
117 DBG_PS
= PIPE_SHADER_FRAGMENT
,
118 DBG_GS
= PIPE_SHADER_GEOMETRY
,
119 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
120 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
121 DBG_CS
= PIPE_SHADER_COMPUTE
,
127 /* Shader compiler options the shader cache should be aware of: */
128 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
133 /* Shader compiler options (with no effect on the shader cache): */
136 DBG_MONOLITHIC_SHADERS
,
139 /* Information logging options: */
145 /* Driver options: */
153 /* 3D engine options: */
173 DBG_TEST_VMFAULT_SDMA
,
174 DBG_TEST_VMFAULT_SHADER
,
179 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
180 #define DBG(name) (1ull << DBG_##name)
182 enum si_cache_policy
{
184 L2_STREAM
, /* same as SLC=1 */
185 L2_LRU
, /* same as SLC=0 */
189 SI_COHERENCY_NONE
, /* no cache flushes needed */
191 SI_COHERENCY_CB_META
,
197 struct u_suballocator
;
199 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
202 struct r600_resource
{
203 struct threaded_resource b
;
205 /* Winsys objects. */
206 struct pb_buffer
*buf
;
207 uint64_t gpu_address
;
208 /* Memory usage if the buffer placement is optimal. */
212 /* Resource properties. */
214 unsigned bo_alignment
;
215 enum radeon_bo_domain domains
;
216 enum radeon_bo_flag flags
;
217 unsigned bind_history
;
218 int max_forced_staging_uploads
;
220 /* The buffer range which is initialized (with a write transfer,
221 * streamout, DMA, or as a random access target). The rest of
222 * the buffer is considered invalid and can be mapped unsynchronized.
224 * This allows unsychronized mapping of a buffer range which hasn't
225 * been used yet. It's for applications which forget to use
226 * the unsynchronized map flag and expect the driver to figure it out.
228 struct util_range valid_buffer_range
;
230 /* For buffers only. This indicates that a write operation has been
231 * performed by TC L2, but the cache hasn't been flushed.
232 * Any hw block which doesn't use or bypasses TC L2 should check this
233 * flag and flush the cache before using the buffer.
235 * For example, TC L2 must be flushed if a buffer which has been
236 * modified by a shader store instruction is about to be used as
237 * an index buffer. The reason is that VGT DMA index fetching doesn't
242 /* Whether this resource is referenced by bindless handles. */
243 bool texture_handle_allocated
;
244 bool image_handle_allocated
;
246 /* Whether the resource has been exported via resource_get_handle. */
247 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
251 struct threaded_transfer b
;
252 struct r600_resource
*staging
;
257 struct r600_resource buffer
;
259 struct radeon_surf surface
;
261 struct si_texture
*flushed_depth_texture
;
263 /* Colorbuffer compression and fast clear. */
264 uint64_t fmask_offset
;
265 uint64_t cmask_offset
;
266 uint64_t cmask_base_address_reg
;
267 struct r600_resource
*cmask_buffer
;
268 uint64_t dcc_offset
; /* 0 = disabled */
269 unsigned cb_color_info
; /* fast clear enable bit */
270 unsigned color_clear_value
[2];
271 unsigned last_msaa_resolve_target_micro_mode
;
272 unsigned num_level0_transfers
;
274 /* Depth buffer compression and fast clear. */
275 uint64_t htile_offset
;
276 float depth_clear_value
;
277 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
278 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
279 enum pipe_format db_render_format
:16;
280 uint8_t stencil_clear_value
;
281 bool tc_compatible_htile
:1;
282 bool depth_cleared
:1; /* if it was cleared at least once */
283 bool stencil_cleared
:1; /* if it was cleared at least once */
284 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
286 bool db_compatible
:1;
290 /* We need to track DCC dirtiness, because st/dri usually calls
291 * flush_resource twice per frame (not a bug) and we don't wanna
292 * decompress DCC twice. Also, the dirty tracking must be done even
293 * if DCC isn't used, because it's required by the DCC usage analysis
294 * for a possible future enablement.
296 bool separate_dcc_dirty
:1;
297 /* Statistics gathering for the DCC enablement heuristic. */
298 bool dcc_gather_statistics
:1;
299 /* Counter that should be non-zero if the texture is bound to a
302 unsigned framebuffers_bound
;
303 /* Whether the texture is a displayable back buffer and needs DCC
304 * decompression, which is expensive. Therefore, it's enabled only
305 * if statistics suggest that it will pay off and it's allocated
306 * separately. It can't be bound as a sampler by apps. Limited to
307 * target == 2D and last_level == 0. If enabled, dcc_offset contains
308 * the absolute GPUVM address, not the relative one.
310 struct r600_resource
*dcc_separate_buffer
;
311 /* When DCC is temporarily disabled, the separate buffer is here. */
312 struct r600_resource
*last_dcc_separate_buffer
;
313 /* Estimate of how much this color buffer is written to in units of
314 * full-screen draws: ps_invocations / (width * height)
315 * Shader kills, late Z, and blending with trivial discards make it
316 * inaccurate (we need to count CB updates, not PS invocations).
318 unsigned ps_draw_ratio
;
319 /* The number of clears since the last DCC usage analysis. */
320 unsigned num_slow_clears
;
324 struct pipe_surface base
;
326 /* These can vary with block-compressed textures. */
330 bool color_initialized
:1;
331 bool depth_initialized
:1;
333 /* Misc. color flags. */
334 bool color_is_int8
:1;
335 bool color_is_int10
:1;
336 bool dcc_incompatible
:1;
338 /* Color registers. */
339 unsigned cb_color_info
;
340 unsigned cb_color_view
;
341 unsigned cb_color_attrib
;
342 unsigned cb_color_attrib2
; /* GFX9 and later */
343 unsigned cb_dcc_control
; /* VI and later */
344 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
345 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
346 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
347 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
350 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
351 uint64_t db_stencil_base
;
352 uint64_t db_htile_data_base
;
353 unsigned db_depth_info
;
355 unsigned db_z_info2
; /* GFX9+ */
356 unsigned db_depth_view
;
357 unsigned db_depth_size
;
358 unsigned db_depth_slice
;
359 unsigned db_stencil_info
;
360 unsigned db_stencil_info2
; /* GFX9+ */
361 unsigned db_htile_surface
;
364 struct si_mmio_counter
{
369 union si_mmio_counters
{
371 /* For global GPU load including SDMA. */
372 struct si_mmio_counter gpu
;
375 struct si_mmio_counter spi
;
376 struct si_mmio_counter gui
;
377 struct si_mmio_counter ta
;
378 struct si_mmio_counter gds
;
379 struct si_mmio_counter vgt
;
380 struct si_mmio_counter ia
;
381 struct si_mmio_counter sx
;
382 struct si_mmio_counter wd
;
383 struct si_mmio_counter bci
;
384 struct si_mmio_counter sc
;
385 struct si_mmio_counter pa
;
386 struct si_mmio_counter db
;
387 struct si_mmio_counter cp
;
388 struct si_mmio_counter cb
;
391 struct si_mmio_counter sdma
;
394 struct si_mmio_counter pfp
;
395 struct si_mmio_counter meq
;
396 struct si_mmio_counter me
;
397 struct si_mmio_counter surf_sync
;
398 struct si_mmio_counter cp_dma
;
399 struct si_mmio_counter scratch_ram
;
404 struct si_memory_object
{
405 struct pipe_memory_object b
;
406 struct pb_buffer
*buf
;
410 /* Saved CS data for debugging features. */
411 struct radeon_saved_cs
{
415 struct radeon_bo_list_item
*bo_list
;
420 struct pipe_screen b
;
421 struct radeon_winsys
*ws
;
422 struct disk_cache
*disk_shader_cache
;
424 struct radeon_info info
;
425 uint64_t debug_flags
;
426 char renderer_string
[183];
428 unsigned pa_sc_raster_config
;
429 unsigned pa_sc_raster_config_1
;
430 unsigned se_tile_repeat
;
431 unsigned gs_table_depth
;
432 unsigned tess_offchip_block_dw_size
;
433 unsigned tess_offchip_ring_size
;
434 unsigned tess_factor_ring_size
;
435 unsigned vgt_hs_offchip_param
;
436 unsigned eqaa_force_coverage_samples
;
437 unsigned eqaa_force_z_samples
;
438 unsigned eqaa_force_color_samples
;
439 bool has_clear_state
;
440 bool has_distributed_tess
;
441 bool has_draw_indirect_multi
;
442 bool has_out_of_order_rast
;
443 bool assume_no_z_fights
;
444 bool commutative_blend_add
;
445 bool clear_db_cache_before_clear
;
446 bool has_msaa_sample_loc_bug
;
447 bool has_ls_vgpr_init_bug
;
450 bool llvm_has_working_vgpr_indexing
;
452 /* Whether shaders are monolithic (1-part) or separate (3-part). */
453 bool use_monolithic_shaders
;
455 bool has_rbplus
; /* if RB+ registers exist */
456 bool rbplus_allowed
; /* if RB+ is allowed */
457 bool dcc_msaa_allowed
;
458 bool cpdma_prefetch_writes_memory
;
460 struct slab_parent_pool pool_transfers
;
462 /* Texture filter settings. */
463 int force_aniso
; /* -1 = disabled */
465 /* Auxiliary context. Mainly used to initialize resources.
466 * It must be locked prior to using and flushed before unlocking. */
467 struct pipe_context
*aux_context
;
468 mtx_t aux_context_lock
;
470 /* This must be in the screen, because UE4 uses one context for
471 * compilation and another one for rendering.
473 unsigned num_compilations
;
474 /* Along with ST_DEBUG=precompile, this should show if applications
475 * are loading shaders on demand. This is a monotonic counter.
477 unsigned num_shaders_created
;
478 unsigned num_shader_cache_hits
;
480 /* GPU load thread. */
481 mtx_t gpu_load_mutex
;
482 thrd_t gpu_load_thread
;
483 union si_mmio_counters mmio_counters
;
484 volatile unsigned gpu_load_stop_thread
; /* bool */
486 /* Performance counters. */
487 struct si_perfcounters
*perfcounters
;
489 /* If pipe_screen wants to recompute and re-emit the framebuffer,
490 * sampler, and image states of all contexts, it should atomically
493 * Each context will compare this with its own last known value of
494 * the counter before drawing and re-emit the states accordingly.
496 unsigned dirty_tex_counter
;
498 /* Atomically increment this counter when an existing texture's
499 * metadata is enabled or disabled in a way that requires changing
500 * contexts' compressed texture binding masks.
502 unsigned compressed_colortex_counter
;
505 /* Context flags to set so that all writes from earlier jobs
506 * in the CP are seen by L2 clients.
510 /* Context flags to set so that all writes from earlier jobs
511 * that end in L2 are seen by CP.
516 mtx_t shader_parts_mutex
;
517 struct si_shader_part
*vs_prologs
;
518 struct si_shader_part
*tcs_epilogs
;
519 struct si_shader_part
*gs_prologs
;
520 struct si_shader_part
*ps_prologs
;
521 struct si_shader_part
*ps_epilogs
;
523 /* Shader cache in memory.
525 * Design & limitations:
526 * - The shader cache is per screen (= per process), never saved to
527 * disk, and skips redundant shader compilations from TGSI to bytecode.
528 * - It can only be used with one-variant-per-shader support, in which
529 * case only the main (typically middle) part of shaders is cached.
530 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
531 * variants of VS and TES are cached, so LS and ES aren't.
532 * - GS and CS aren't cached, but it's certainly possible to cache
535 mtx_t shader_cache_mutex
;
536 struct hash_table
*shader_cache
;
538 /* Shader compiler queue for multithreaded compilation. */
539 struct util_queue shader_compiler_queue
;
540 /* Use at most 3 normal compiler threads on quadcore and better.
541 * Hyperthreaded CPUs report the number of threads, but we want
542 * the number of cores. We only need this many threads for shader-db. */
543 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
545 struct util_queue shader_compiler_queue_low_priority
;
546 /* Use at most 2 low priority threads on quadcore and better.
547 * We want to minimize the impact on multithreaded Mesa. */
548 struct ac_llvm_compiler compiler_lowp
[10];
551 struct si_blend_color
{
552 struct pipe_blend_color state
;
556 struct si_sampler_view
{
557 struct pipe_sampler_view base
;
558 /* [0..7] = image descriptor
559 * [4..7] = buffer descriptor */
561 uint32_t fmask_state
[8];
562 const struct legacy_surf_level
*base_level_info
;
565 bool is_stencil_sampler
;
567 bool dcc_incompatible
;
570 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
572 struct si_sampler_state
{
577 uint32_t integer_val
[4];
578 uint32_t upgraded_depth_val
[4];
581 struct si_cs_shader_state
{
582 struct si_compute
*program
;
583 struct si_compute
*emitted_program
;
590 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
591 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
593 /* The i-th bit is set if that element is enabled (non-NULL resource). */
594 unsigned enabled_mask
;
595 uint32_t needs_depth_decompress_mask
;
596 uint32_t needs_color_decompress_mask
;
600 struct pipe_image_view views
[SI_NUM_IMAGES
];
601 uint32_t needs_color_decompress_mask
;
602 unsigned enabled_mask
;
605 struct si_framebuffer
{
606 struct pipe_framebuffer_state state
;
607 unsigned colorbuf_enabled_4bit
;
608 unsigned spi_shader_col_format
;
609 unsigned spi_shader_col_format_alpha
;
610 unsigned spi_shader_col_format_blend
;
611 unsigned spi_shader_col_format_blend_alpha
;
612 ubyte nr_samples
:5; /* at most 16xAA */
613 ubyte log_samples
:3; /* at most 4 = 16xAA */
614 ubyte nr_color_samples
; /* at most 8xAA */
615 ubyte compressed_cb_mask
;
616 ubyte uncompressed_cb_mask
;
618 ubyte color_is_int10
;
620 ubyte dcc_overwrite_combiner_watermark
;
623 bool CB_has_shader_readable_metadata
;
624 bool DB_has_shader_readable_metadata
;
628 /* This is the list we want to support. */
629 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
630 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
631 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
634 struct si_signed_scissor
{
639 enum si_quant_mode quant_mode
;
644 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
647 struct si_viewports
{
649 unsigned depth_range_dirty_mask
;
650 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
651 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
654 struct si_clip_state
{
655 struct pipe_clip_state state
;
659 struct si_streamout_target
{
660 struct pipe_stream_output_target b
;
662 /* The buffer where BUFFER_FILLED_SIZE is stored. */
663 struct r600_resource
*buf_filled_size
;
664 unsigned buf_filled_size_offset
;
665 bool buf_filled_size_valid
;
667 unsigned stride_in_dw
;
670 struct si_streamout
{
673 unsigned enabled_mask
;
674 unsigned num_targets
;
675 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
677 unsigned append_bitmask
;
680 /* External state which comes from the vertex shader,
681 * it must be set explicitly when binding a shader. */
682 uint16_t *stride_in_dw
;
683 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
685 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
686 unsigned hw_enabled_mask
;
688 /* The state of VGT_STRMOUT_(CONFIG|EN). */
689 bool streamout_enabled
;
690 bool prims_gen_query_enabled
;
691 int num_prims_gen_queries
;
694 /* A shader state consists of the shader selector, which is a constant state
695 * object shared by multiple contexts and shouldn't be modified, and
696 * the current shader variant selected for this context.
698 struct si_shader_ctx_state
{
699 struct si_shader_selector
*cso
;
700 struct si_shader
*current
;
703 #define SI_NUM_VGT_PARAM_KEY_BITS 12
704 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
706 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
707 * Some fields are set by state-change calls, most are set by draw_vbo.
709 union si_vgt_param_key
{
711 #ifdef PIPE_ARCH_LITTLE_ENDIAN
713 unsigned uses_instancing
:1;
714 unsigned multi_instances_smaller_than_primgroup
:1;
715 unsigned primitive_restart
:1;
716 unsigned count_from_stream_output
:1;
717 unsigned line_stipple_enabled
:1;
718 unsigned uses_tess
:1;
719 unsigned tess_uses_prim_id
:1;
721 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
722 #else /* PIPE_ARCH_BIG_ENDIAN */
723 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
725 unsigned tess_uses_prim_id
:1;
726 unsigned uses_tess
:1;
727 unsigned line_stipple_enabled
:1;
728 unsigned count_from_stream_output
:1;
729 unsigned primitive_restart
:1;
730 unsigned multi_instances_smaller_than_primgroup
:1;
731 unsigned uses_instancing
:1;
738 struct si_texture_handle
742 struct pipe_sampler_view
*view
;
743 struct si_sampler_state sstate
;
746 struct si_image_handle
750 struct pipe_image_view view
;
754 struct pipe_reference reference
;
755 struct si_context
*ctx
;
756 struct radeon_saved_cs gfx
;
757 struct r600_resource
*trace_buf
;
760 unsigned gfx_last_dw
;
766 struct pipe_context b
; /* base class */
768 enum radeon_family family
;
769 enum chip_class chip_class
;
771 struct radeon_winsys
*ws
;
772 struct radeon_winsys_ctx
*ctx
;
773 struct radeon_cmdbuf
*gfx_cs
;
774 struct radeon_cmdbuf
*dma_cs
;
775 struct pipe_fence_handle
*last_gfx_fence
;
776 struct pipe_fence_handle
*last_sdma_fence
;
777 struct r600_resource
*eop_bug_scratch
;
778 struct u_upload_mgr
*cached_gtt_allocator
;
779 struct threaded_context
*tc
;
780 struct u_suballocator
*allocator_zeroed_memory
;
781 struct slab_child_pool pool_transfers
;
782 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
783 struct pipe_device_reset_callback device_reset_callback
;
784 struct u_log_context
*log
;
785 void *query_result_shader
;
786 struct blitter_context
*blitter
;
787 void *custom_dsa_flush
;
788 void *custom_blend_resolve
;
789 void *custom_blend_fmask_decompress
;
790 void *custom_blend_eliminate_fastclear
;
791 void *custom_blend_dcc_decompress
;
793 void *vs_blit_pos_layered
;
795 void *vs_blit_color_layered
;
796 void *vs_blit_texcoord
;
797 void *cs_clear_buffer
;
798 void *cs_copy_buffer
;
799 struct si_screen
*screen
;
800 struct pipe_debug_callback debug
;
801 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
802 struct si_shader_ctx_state fixed_func_tcs_shader
;
803 struct r600_resource
*wait_mem_scratch
;
804 unsigned wait_mem_number
;
805 uint16_t prefetch_L2_mask
;
807 bool gfx_flush_in_progress
:1;
808 bool gfx_last_ib_is_busy
:1;
809 bool compute_is_busy
:1;
811 unsigned num_gfx_cs_flushes
;
812 unsigned initial_gfx_cs_size
;
813 unsigned gpu_reset_counter
;
814 unsigned last_dirty_tex_counter
;
815 unsigned last_compressed_colortex_counter
;
816 unsigned last_num_draw_calls
;
817 unsigned flags
; /* flush flags */
818 /* Current unaccounted memory usage. */
822 /* Atoms (direct states). */
823 union si_state_atoms atoms
;
824 unsigned dirty_atoms
; /* mask */
825 /* PM4 states (precomputed immutable states) */
826 unsigned dirty_states
;
827 union si_state queued
;
828 union si_state emitted
;
830 /* Atom declarations. */
831 struct si_framebuffer framebuffer
;
832 unsigned sample_locs_num_samples
;
833 uint16_t sample_mask
;
834 unsigned last_cb_target_mask
;
835 struct si_blend_color blend_color
;
836 struct si_clip_state clip_state
;
837 struct si_shader_data shader_pointers
;
838 struct si_stencil_ref stencil_ref
;
839 struct si_scissors scissors
;
840 struct si_streamout streamout
;
841 struct si_viewports viewports
;
842 unsigned num_window_rectangles
;
843 bool window_rectangles_include
;
844 struct pipe_scissor_state window_rectangles
[4];
846 /* Precomputed states. */
847 struct si_pm4_state
*init_config
;
848 struct si_pm4_state
*init_config_gs_rings
;
849 bool init_config_has_vgt_flush
;
850 struct si_pm4_state
*vgt_shader_config
[4];
853 struct si_shader_ctx_state ps_shader
;
854 struct si_shader_ctx_state gs_shader
;
855 struct si_shader_ctx_state vs_shader
;
856 struct si_shader_ctx_state tcs_shader
;
857 struct si_shader_ctx_state tes_shader
;
858 struct si_cs_shader_state cs_shader_state
;
860 /* shader information */
861 struct si_vertex_elements
*vertex_elements
;
862 unsigned sprite_coord_enable
;
863 unsigned cs_max_waves_per_sh
;
865 bool do_update_shaders
;
867 /* vertex buffer descriptors */
868 uint32_t *vb_descriptors_gpu_list
;
869 struct r600_resource
*vb_descriptors_buffer
;
870 unsigned vb_descriptors_offset
;
872 /* shader descriptors */
873 struct si_descriptors descriptors
[SI_NUM_DESCS
];
874 unsigned descriptors_dirty
;
875 unsigned shader_pointers_dirty
;
876 unsigned shader_needs_decompress_mask
;
877 struct si_buffer_resources rw_buffers
;
878 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
879 struct si_samplers samplers
[SI_NUM_SHADERS
];
880 struct si_images images
[SI_NUM_SHADERS
];
882 /* other shader resources */
883 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
884 struct pipe_resource
*esgs_ring
;
885 struct pipe_resource
*gsvs_ring
;
886 struct pipe_resource
*tess_rings
;
887 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
888 struct r600_resource
*border_color_buffer
;
889 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
890 unsigned border_color_count
;
891 unsigned num_vs_blit_sgprs
;
892 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
893 uint32_t cs_user_data
[4];
895 /* Vertex and index buffers. */
896 bool vertex_buffers_dirty
;
897 bool vertex_buffer_pointer_dirty
;
898 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
900 /* MSAA config state. */
902 bool ps_uses_fbfetch
;
903 bool smoothing_enabled
;
905 /* DB render state. */
906 unsigned ps_db_shader_control
;
907 unsigned dbcb_copy_sample
;
908 bool dbcb_depth_copy_enabled
:1;
909 bool dbcb_stencil_copy_enabled
:1;
910 bool db_flush_depth_inplace
:1;
911 bool db_flush_stencil_inplace
:1;
912 bool db_depth_clear
:1;
913 bool db_depth_disable_expclear
:1;
914 bool db_stencil_clear
:1;
915 bool db_stencil_disable_expclear
:1;
916 bool occlusion_queries_disabled
:1;
917 bool generate_mipmap_for_depth
:1;
919 /* Emitted draw state. */
920 bool gs_tri_strip_adj_fix
:1;
923 int last_base_vertex
;
924 int last_start_instance
;
926 int last_sh_base_reg
;
927 int last_primitive_restart_en
;
928 int last_restart_index
;
930 int last_multi_vgt_param
;
932 unsigned last_sc_line_stipple
;
933 unsigned current_vs_state
;
934 unsigned last_vs_state
;
935 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
938 struct r600_resource
*scratch_buffer
;
939 unsigned scratch_waves
;
940 unsigned spi_tmpring_size
;
942 struct r600_resource
*compute_scratch_buffer
;
944 /* Emitted derived tessellation state. */
945 /* Local shader (VS), or HS if LS-HS are merged. */
946 struct si_shader
*last_ls
;
947 struct si_shader_selector
*last_tcs
;
948 int last_num_tcs_input_cp
;
949 int last_tes_sh_base
;
950 bool last_tess_uses_primid
;
951 unsigned last_num_patches
;
952 int last_ls_hs_config
;
956 struct si_saved_cs
*current_saved_cs
;
957 uint64_t dmesg_timestamp
;
958 unsigned apitrace_call_number
;
961 bool need_check_render_feedback
;
962 bool decompression_enabled
;
964 bool vs_writes_viewport_index
;
965 bool vs_disables_clipping_viewport
;
967 /* Precomputed IA_MULTI_VGT_PARAM */
968 union si_vgt_param_key ia_multi_vgt_param_key
;
969 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
971 /* Bindless descriptors. */
972 struct si_descriptors bindless_descriptors
;
973 struct util_idalloc bindless_used_slots
;
974 unsigned num_bindless_descriptors
;
975 bool bindless_descriptors_dirty
;
976 bool graphics_bindless_pointer_dirty
;
977 bool compute_bindless_pointer_dirty
;
979 /* Allocated bindless handles */
980 struct hash_table
*tex_handles
;
981 struct hash_table
*img_handles
;
983 /* Resident bindless handles */
984 struct util_dynarray resident_tex_handles
;
985 struct util_dynarray resident_img_handles
;
987 /* Resident bindless handles which need decompression */
988 struct util_dynarray resident_tex_needs_color_decompress
;
989 struct util_dynarray resident_img_needs_color_decompress
;
990 struct util_dynarray resident_tex_needs_depth_decompress
;
993 bool uses_bindless_samplers
;
994 bool uses_bindless_images
;
996 /* MSAA sample locations.
997 * The first index is the sample index.
998 * The second index is the coordinate: X, Y. */
1006 struct pipe_resource
*sample_pos_buffer
;
1009 unsigned num_draw_calls
;
1010 unsigned num_decompress_calls
;
1011 unsigned num_mrt_draw_calls
;
1012 unsigned num_prim_restart_calls
;
1013 unsigned num_spill_draw_calls
;
1014 unsigned num_compute_calls
;
1015 unsigned num_spill_compute_calls
;
1016 unsigned num_dma_calls
;
1017 unsigned num_cp_dma_calls
;
1018 unsigned num_vs_flushes
;
1019 unsigned num_ps_flushes
;
1020 unsigned num_cs_flushes
;
1021 unsigned num_cb_cache_flushes
;
1022 unsigned num_db_cache_flushes
;
1023 unsigned num_L2_invalidates
;
1024 unsigned num_L2_writebacks
;
1025 unsigned num_resident_handles
;
1026 uint64_t num_alloc_tex_transfer_bytes
;
1027 unsigned last_tex_ps_draw_ratio
; /* for query */
1028 unsigned context_roll_counter
;
1031 /* Maintain the list of active queries for pausing between IBs. */
1032 int num_occlusion_queries
;
1033 int num_perfect_occlusion_queries
;
1034 struct list_head active_queries
;
1035 unsigned num_cs_dw_queries_suspend
;
1037 /* Render condition. */
1038 struct pipe_query
*render_cond
;
1039 unsigned render_cond_mode
;
1040 bool render_cond_invert
;
1041 bool render_cond_force_off
; /* for u_blitter */
1043 /* Statistics gathering for the DCC enablement heuristic. It can't be
1044 * in si_texture because si_texture can be shared by multiple
1045 * contexts. This is for back buffers only. We shouldn't get too many
1048 * X11 DRI3 rotates among a finite set of back buffers. They should
1049 * all fit in this array. If they don't, separate DCC might never be
1050 * enabled by DCC stat gathering.
1053 struct si_texture
*tex
;
1054 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1055 struct pipe_query
*ps_stats
[3];
1056 /* If all slots are used and another slot is needed,
1057 * the least recently used slot is evicted based on this. */
1058 int64_t last_use_timestamp
;
1062 /* Copy one resource to another using async DMA. */
1063 void (*dma_copy
)(struct pipe_context
*ctx
,
1064 struct pipe_resource
*dst
,
1066 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1067 struct pipe_resource
*src
,
1069 const struct pipe_box
*src_box
);
1071 struct si_tracked_regs tracked_regs
;
1075 void cik_init_sdma_functions(struct si_context
*sctx
);
1078 enum si_blitter_op
/* bitmask */
1080 SI_SAVE_TEXTURES
= 1,
1081 SI_SAVE_FRAMEBUFFER
= 2,
1082 SI_SAVE_FRAGMENT_STATE
= 4,
1083 SI_DISABLE_RENDER_COND
= 8,
1086 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1087 void si_blitter_end(struct si_context
*sctx
);
1088 void si_init_blit_functions(struct si_context
*sctx
);
1089 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1090 void si_resource_copy_region(struct pipe_context
*ctx
,
1091 struct pipe_resource
*dst
,
1093 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1094 struct pipe_resource
*src
,
1096 const struct pipe_box
*src_box
);
1097 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1098 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1099 struct si_texture
*texture
,
1100 struct si_texture
*staging
,
1101 unsigned first_level
, unsigned last_level
,
1102 unsigned first_layer
, unsigned last_layer
,
1103 unsigned first_sample
, unsigned last_sample
);
1106 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1107 struct pb_buffer
*buf
,
1108 enum radeon_bo_usage usage
);
1109 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1110 struct r600_resource
*resource
,
1112 void si_init_resource_fields(struct si_screen
*sscreen
,
1113 struct r600_resource
*res
,
1114 uint64_t size
, unsigned alignment
);
1115 bool si_alloc_resource(struct si_screen
*sscreen
,
1116 struct r600_resource
*res
);
1117 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1118 unsigned flags
, unsigned usage
,
1119 unsigned size
, unsigned alignment
);
1120 struct r600_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1121 unsigned flags
, unsigned usage
,
1122 unsigned size
, unsigned alignment
);
1123 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1124 struct pipe_resource
*dst
,
1125 struct pipe_resource
*src
);
1126 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1127 void si_init_buffer_functions(struct si_context
*sctx
);
1130 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1131 bool vi_alpha_is_on_msb(enum pipe_format format
);
1132 void vi_dcc_clear_level(struct si_context
*sctx
,
1133 struct si_texture
*tex
,
1134 unsigned level
, unsigned clear_value
);
1135 void si_init_clear_functions(struct si_context
*sctx
);
1137 /* si_compute_blit.c */
1138 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1139 enum si_cache_policy cache_policy
);
1140 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1141 uint64_t offset
, uint64_t size
, uint32_t *clear_value
,
1142 uint32_t clear_value_size
, enum si_coherency coher
);
1143 void si_copy_buffer(struct si_context
*sctx
,
1144 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1145 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1146 void si_init_compute_blit_functions(struct si_context
*sctx
);
1149 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1150 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1151 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1152 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1153 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1154 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1155 SI_CPDMA_SKIP_SYNC_AFTER | \
1156 SI_CPDMA_SKIP_SYNC_BEFORE | \
1157 SI_CPDMA_SKIP_GFX_SYNC | \
1158 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1160 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1161 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1162 uint64_t offset
, uint64_t size
, unsigned value
,
1163 enum si_coherency coher
,
1164 enum si_cache_policy cache_policy
);
1165 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1166 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1167 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1168 unsigned user_flags
, enum si_coherency coher
,
1169 enum si_cache_policy cache_policy
);
1170 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1171 uint64_t offset
, unsigned size
);
1172 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1173 void si_test_gds(struct si_context
*sctx
);
1176 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1177 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1178 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1179 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1180 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1181 void si_log_hw_flush(struct si_context
*sctx
);
1182 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1183 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1184 void si_init_debug_functions(struct si_context
*sctx
);
1185 void si_check_vm_faults(struct si_context
*sctx
,
1186 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1187 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1190 void si_init_dma_functions(struct si_context
*sctx
);
1193 void si_dma_emit_timestamp(struct si_context
*sctx
, struct r600_resource
*dst
,
1195 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1196 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1197 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1198 struct r600_resource
*dst
, struct r600_resource
*src
);
1199 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1200 struct pipe_fence_handle
**fence
);
1201 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1202 uint64_t offset
, uint64_t size
, unsigned value
);
1205 void si_cp_release_mem(struct si_context
*ctx
,
1206 unsigned event
, unsigned event_flags
,
1207 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1208 struct r600_resource
*buf
, uint64_t va
,
1209 uint32_t new_fence
, unsigned query_type
);
1210 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1211 void si_cp_wait_mem(struct si_context
*ctx
,
1212 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
);
1213 void si_init_fence_functions(struct si_context
*ctx
);
1214 void si_init_screen_fence_functions(struct si_screen
*screen
);
1215 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1216 struct tc_unflushed_batch_token
*tc_token
);
1219 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1222 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1223 struct pipe_fence_handle
**fence
);
1224 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1225 void si_need_gfx_cs_space(struct si_context
*ctx
);
1227 /* r600_gpu_load.c */
1228 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1229 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1230 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1234 void si_init_compute_functions(struct si_context
*sctx
);
1236 /* r600_perfcounters.c */
1237 void si_perfcounters_destroy(struct si_screen
*sscreen
);
1239 /* si_perfcounters.c */
1240 void si_init_perfcounters(struct si_screen
*screen
);
1243 bool si_check_device_reset(struct si_context
*sctx
);
1246 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1247 void si_init_query_functions(struct si_context
*sctx
);
1248 void si_suspend_queries(struct si_context
*sctx
);
1249 void si_resume_queries(struct si_context
*sctx
);
1251 /* si_shaderlib_tgsi.c */
1252 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1253 unsigned num_layers
);
1254 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1255 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1256 unsigned num_dwords_per_thread
,
1257 bool dst_stream_cache_policy
, bool is_copy
);
1258 void *si_create_query_result_cs(struct si_context
*sctx
);
1261 void si_test_dma(struct si_screen
*sscreen
);
1263 /* si_test_clearbuffer.c */
1264 void si_test_dma_perf(struct si_screen
*sscreen
);
1267 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1268 const struct pipe_video_codec
*templ
);
1270 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1271 const struct pipe_video_buffer
*tmpl
);
1274 void si_update_vs_viewport_state(struct si_context
*ctx
);
1275 void si_init_viewport_functions(struct si_context
*ctx
);
1278 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1279 struct si_texture
*dst
,
1280 unsigned dst_level
, unsigned dstx
,
1281 unsigned dsty
, unsigned dstz
,
1282 struct si_texture
*src
,
1284 const struct pipe_box
*src_box
);
1285 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1286 struct si_texture
*tex
);
1287 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1288 struct si_texture
*tex
);
1289 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1290 struct pipe_resource
*texture
,
1291 struct si_texture
**staging
);
1292 void si_print_texture_info(struct si_screen
*sscreen
,
1293 struct si_texture
*tex
, struct u_log_context
*log
);
1294 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1295 const struct pipe_resource
*templ
);
1296 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1297 enum pipe_format format2
);
1298 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1300 enum pipe_format view_format
);
1301 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1302 struct pipe_resource
*tex
,
1304 enum pipe_format view_format
);
1305 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1306 struct pipe_resource
*texture
,
1307 const struct pipe_surface
*templ
,
1308 unsigned width0
, unsigned height0
,
1309 unsigned width
, unsigned height
);
1310 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1311 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1312 struct si_texture
*tex
);
1313 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1314 struct si_texture
*tex
);
1315 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1316 struct si_texture
*tex
);
1317 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1318 struct si_texture
*tex
);
1319 bool si_texture_disable_dcc(struct si_context
*sctx
,
1320 struct si_texture
*tex
);
1321 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1322 void si_init_context_texture_functions(struct si_context
*sctx
);
1329 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
1331 return (struct r600_resource
*)r
;
1335 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
1337 pipe_resource_reference((struct pipe_resource
**)ptr
,
1338 (struct pipe_resource
*)res
);
1342 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1344 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1348 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1350 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1353 static inline unsigned
1354 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1357 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1359 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1363 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1366 /* Add memory usage for need_gfx_cs_space */
1367 sctx
->vram
+= r600_resource(r
)->vram_usage
;
1368 sctx
->gtt
+= r600_resource(r
)->gart_usage
;
1373 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1375 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1378 static inline unsigned
1379 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1381 return 1 << (atom
- sctx
->atoms
.array
);
1385 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1387 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1390 sctx
->dirty_atoms
|= bit
;
1392 sctx
->dirty_atoms
&= ~bit
;
1396 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1398 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1402 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1404 si_set_atom_dirty(sctx
, atom
, true);
1407 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1409 if (sctx
->gs_shader
.cso
)
1410 return &sctx
->gs_shader
;
1411 if (sctx
->tes_shader
.cso
)
1412 return &sctx
->tes_shader
;
1414 return &sctx
->vs_shader
;
1417 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1419 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1421 return vs
->cso
? &vs
->cso
->info
: NULL
;
1424 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1426 if (sctx
->gs_shader
.cso
)
1427 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1429 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1430 return vs
->current
? vs
->current
: NULL
;
1433 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1436 return sscreen
->debug_flags
& (1 << processor
);
1439 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1441 return sctx
->streamout
.streamout_enabled
||
1442 sctx
->streamout
.prims_gen_query_enabled
;
1445 static inline unsigned
1446 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1448 unsigned alignment
, tcc_cache_line_size
;
1450 /* If the upload size is less than the cache line size (e.g. 16, 32),
1451 * the whole thing will fit into a cache line if we align it to its size.
1452 * The idea is that multiple small uploads can share a cache line.
1453 * If the upload size is greater, align it to the cache line size.
1455 alignment
= util_next_power_of_two(upload_size
);
1456 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1457 return MIN2(alignment
, tcc_cache_line_size
);
1461 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1463 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1464 si_destroy_saved_cs(*dst
);
1470 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1471 bool shaders_read_metadata
)
1473 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1474 SI_CONTEXT_INV_VMEM_L1
;
1476 if (sctx
->chip_class
>= GFX9
) {
1477 /* Single-sample color is coherent with shaders on GFX9, but
1478 * L2 metadata must be flushed if shaders read metadata.
1481 if (num_samples
>= 2)
1482 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1483 else if (shaders_read_metadata
)
1484 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1487 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1492 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1493 bool include_stencil
, bool shaders_read_metadata
)
1495 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1496 SI_CONTEXT_INV_VMEM_L1
;
1498 if (sctx
->chip_class
>= GFX9
) {
1499 /* Single-sample depth (not stencil) is coherent with shaders
1500 * on GFX9, but L2 metadata must be flushed if shaders read
1503 if (num_samples
>= 2 || include_stencil
)
1504 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1505 else if (shaders_read_metadata
)
1506 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1509 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1514 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1516 return (stencil_sampler
&& tex
->can_sample_s
) ||
1517 (!stencil_sampler
&& tex
->can_sample_z
);
1521 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1523 return tex
->htile_offset
&& level
== 0;
1527 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1529 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1530 return tex
->tc_compatible_htile
&& level
== 0;
1533 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1535 if (sctx
->ps_uses_fbfetch
)
1536 return sctx
->framebuffer
.nr_color_samples
;
1538 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1541 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1543 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1546 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1550 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1551 sctx
->queued
.named
.blend
->cb_target_mask
;
1553 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1554 colormask
&= ps
->colors_written_4bit
;
1555 else if (!ps
->colors_written_4bit
)
1556 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1561 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1562 (1 << PIPE_PRIM_LINE_LOOP) | \
1563 (1 << PIPE_PRIM_LINE_STRIP) | \
1564 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1565 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1567 static inline bool util_prim_is_lines(unsigned prim
)
1569 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1572 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1574 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1575 (1 << PIPE_PRIM_POINTS
))) != 0;
1579 * Return true if there is enough memory in VRAM and GTT for the buffers
1582 * \param vram VRAM memory size not added to the buffer list yet
1583 * \param gtt GTT memory size not added to the buffer list yet
1586 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1587 struct radeon_cmdbuf
*cs
,
1588 uint64_t vram
, uint64_t gtt
)
1590 vram
+= cs
->used_vram
;
1591 gtt
+= cs
->used_gart
;
1593 /* Anything that goes above the VRAM size should go to GTT. */
1594 if (vram
> screen
->info
.vram_size
)
1595 gtt
+= vram
- screen
->info
.vram_size
;
1597 /* Now we just need to check if we have enough GTT. */
1598 return gtt
< screen
->info
.gart_size
* 0.7;
1602 * Add a buffer to the buffer list for the given command stream (CS).
1604 * All buffers used by a CS must be added to the list. This tells the kernel
1605 * driver which buffers are used by GPU commands. Other buffers can
1606 * be swapped out (not accessible) during execution.
1608 * The buffer list becomes empty after every context flush and must be
1611 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1612 struct radeon_cmdbuf
*cs
,
1613 struct r600_resource
*rbo
,
1614 enum radeon_bo_usage usage
,
1615 enum radeon_bo_priority priority
)
1618 sctx
->ws
->cs_add_buffer(
1620 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1621 rbo
->domains
, priority
);
1625 * Same as above, but also checks memory usage and flushes the context
1628 * When this SHOULD NOT be used:
1630 * - if si_context_add_resource_size has been called for the buffer
1631 * followed by *_need_cs_space for checking the memory usage
1633 * - if si_need_dma_space has been called for the buffer
1635 * - when emitting state packets and draw packets (because preceding packets
1636 * can't be re-emitted at that point)
1638 * - if shader resource "enabled_mask" is not up-to-date or there is
1639 * a different constraint disallowing a context flush
1642 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1643 struct r600_resource
*rbo
,
1644 enum radeon_bo_usage usage
,
1645 enum radeon_bo_priority priority
,
1649 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1650 sctx
->vram
+ rbo
->vram_usage
,
1651 sctx
->gtt
+ rbo
->gart_usage
))
1652 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1654 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, rbo
, usage
, priority
);
1657 #define PRINT_ERR(fmt, args...) \
1658 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)