radeonsi: use PIPE_FORMAT_P010 for 10-bit VP9 decoding
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32 #include "util/u_threaded_context.h"
33
34 #if UTIL_ARCH_BIG_ENDIAN
35 #define SI_BIG_ENDIAN 1
36 #else
37 #define SI_BIG_ENDIAN 0
38 #endif
39
40 #define ATI_VENDOR_ID 0x1002
41 #define SI_PRIM_DISCARD_DEBUG 0
42 #define SI_NOT_QUERY 0xffffffff
43
44 /* The base vertex and primitive restart can be any number, but we must pick
45 * one which will mean "unknown" for the purpose of state tracking and
46 * the number shouldn't be a commonly-used one. */
47 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
48 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
49 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_MAX_POINT_SIZE 2048
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
55
56 /* Tunables for compute-based clear_buffer and copy_buffer: */
57 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
58 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
59 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
60
61 /* Pipeline & streamout query controls. */
62 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
63 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
64 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
65 /* Instruction cache. */
66 #define SI_CONTEXT_INV_ICACHE (1 << 3)
67 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
68 * GFX10: This also invalidates the L1 shader array cache. */
69 #define SI_CONTEXT_INV_SCACHE (1 << 4)
70 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
71 * GFX10: This also invalidates the L1 shader array cache. */
72 #define SI_CONTEXT_INV_VCACHE (1 << 5)
73 /* L2 cache + L2 metadata cache writeback & invalidate.
74 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
75 #define SI_CONTEXT_INV_L2 (1 << 6)
76 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
77 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
78 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
79 #define SI_CONTEXT_WB_L2 (1 << 7)
80 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
81 * a CB or DB flush. */
82 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
83 /* Framebuffer caches. */
84 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
85 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
86 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
87 /* Engine synchronization. */
88 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
89 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
90 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
91 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
92 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
93
94 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
95 #define SI_PREFETCH_LS (1 << 1)
96 #define SI_PREFETCH_HS (1 << 2)
97 #define SI_PREFETCH_ES (1 << 3)
98 #define SI_PREFETCH_GS (1 << 4)
99 #define SI_PREFETCH_VS (1 << 5)
100 #define SI_PREFETCH_PS (1 << 6)
101
102 #define SI_MAX_BORDER_COLORS 4096
103 #define SI_MAX_VIEWPORTS 16
104 #define SIX_BITS 0x3F
105 #define SI_MAP_BUFFER_ALIGNMENT 64
106 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
107
108 #define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
109 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
110 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
111 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
112 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
113 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
114 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
115 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
116 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
117 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
118 /* Set a micro tile mode: */
119 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
120 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
121 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \
122 (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
123 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
124 (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
125 #define SI_RESOURCE_FLAG_UNCACHED (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
126
127 enum si_clear_code
128 {
129 DCC_CLEAR_COLOR_0000 = 0x00000000,
130 DCC_CLEAR_COLOR_0001 = 0x40404040,
131 DCC_CLEAR_COLOR_1110 = 0x80808080,
132 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
133 DCC_CLEAR_COLOR_REG = 0x20202020,
134 DCC_UNCOMPRESSED = 0xFFFFFFFF,
135 };
136
137 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
138 #define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
139
140 /* Debug flags. */
141 enum
142 {
143 /* Shader logging options: */
144 DBG_VS = PIPE_SHADER_VERTEX,
145 DBG_PS = PIPE_SHADER_FRAGMENT,
146 DBG_GS = PIPE_SHADER_GEOMETRY,
147 DBG_TCS = PIPE_SHADER_TESS_CTRL,
148 DBG_TES = PIPE_SHADER_TESS_EVAL,
149 DBG_CS = PIPE_SHADER_COMPUTE,
150 DBG_NO_IR,
151 DBG_NO_NIR,
152 DBG_NO_ASM,
153 DBG_PREOPT_IR,
154
155 /* Shader compiler options the shader cache should be aware of: */
156 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
157 DBG_GISEL,
158 DBG_W32_GE,
159 DBG_W32_PS,
160 DBG_W32_CS,
161 DBG_W64_GE,
162 DBG_W64_PS,
163 DBG_W64_CS,
164 DBG_KILL_PS_INF_INTERP,
165
166 /* Shader compiler options (with no effect on the shader cache): */
167 DBG_CHECK_IR,
168 DBG_MONOLITHIC_SHADERS,
169 DBG_NO_OPT_VARIANT,
170
171 /* Information logging options: */
172 DBG_INFO,
173 DBG_TEX,
174 DBG_COMPUTE,
175 DBG_VM,
176 DBG_CACHE_STATS,
177
178 /* Driver options: */
179 DBG_FORCE_SDMA,
180 DBG_NO_SDMA,
181 DBG_NO_SDMA_CLEARS,
182 DBG_NO_SDMA_COPY_IMAGE,
183 DBG_NO_WC,
184 DBG_CHECK_VM,
185 DBG_RESERVE_VMID,
186 DBG_ZERO_VRAM,
187
188 /* 3D engine options: */
189 DBG_NO_GFX,
190 DBG_NO_NGG,
191 DBG_ALWAYS_NGG_CULLING_ALL,
192 DBG_ALWAYS_NGG_CULLING_TESS,
193 DBG_NO_NGG_CULLING,
194 DBG_ALWAYS_PD,
195 DBG_PD,
196 DBG_NO_PD,
197 DBG_SWITCH_ON_EOP,
198 DBG_NO_OUT_OF_ORDER,
199 DBG_NO_DPBB,
200 DBG_NO_DFSM,
201 DBG_DPBB,
202 DBG_DFSM,
203 DBG_NO_HYPERZ,
204 DBG_NO_RB_PLUS,
205 DBG_NO_2D_TILING,
206 DBG_NO_TILING,
207 DBG_NO_DCC,
208 DBG_NO_DCC_CLEAR,
209 DBG_NO_DCC_FB,
210 DBG_NO_DCC_MSAA,
211 DBG_NO_FMASK,
212
213 DBG_COUNT
214 };
215
216 enum
217 {
218 /* Tests: */
219 DBG_TEST_DMA,
220 DBG_TEST_VMFAULT_CP,
221 DBG_TEST_VMFAULT_SDMA,
222 DBG_TEST_VMFAULT_SHADER,
223 DBG_TEST_DMA_PERF,
224 DBG_TEST_GDS,
225 DBG_TEST_GDS_MM,
226 DBG_TEST_GDS_OA_MM,
227 };
228
229 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
230 #define DBG(name) (1ull << DBG_##name)
231
232 enum si_cache_policy
233 {
234 L2_BYPASS,
235 L2_STREAM, /* same as SLC=1 */
236 L2_LRU, /* same as SLC=0 */
237 };
238
239 enum si_coherency
240 {
241 SI_COHERENCY_NONE, /* no cache flushes needed */
242 SI_COHERENCY_SHADER,
243 SI_COHERENCY_CB_META,
244 SI_COHERENCY_DB_META,
245 SI_COHERENCY_CP,
246 };
247
248 struct si_compute;
249 struct si_shader_context;
250 struct hash_table;
251 struct u_suballocator;
252
253 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
254 * at the moment.
255 */
256 struct si_resource {
257 struct threaded_resource b;
258
259 /* Winsys objects. */
260 struct pb_buffer *buf;
261 uint64_t gpu_address;
262 /* Memory usage if the buffer placement is optimal. */
263 uint64_t vram_usage;
264 uint64_t gart_usage;
265
266 /* Resource properties. */
267 uint64_t bo_size;
268 unsigned bo_alignment;
269 enum radeon_bo_domain domains;
270 enum radeon_bo_flag flags;
271 unsigned bind_history;
272 int max_forced_staging_uploads;
273
274 /* The buffer range which is initialized (with a write transfer,
275 * streamout, DMA, or as a random access target). The rest of
276 * the buffer is considered invalid and can be mapped unsynchronized.
277 *
278 * This allows unsychronized mapping of a buffer range which hasn't
279 * been used yet. It's for applications which forget to use
280 * the unsynchronized map flag and expect the driver to figure it out.
281 */
282 struct util_range valid_buffer_range;
283
284 /* For buffers only. This indicates that a write operation has been
285 * performed by TC L2, but the cache hasn't been flushed.
286 * Any hw block which doesn't use or bypasses TC L2 should check this
287 * flag and flush the cache before using the buffer.
288 *
289 * For example, TC L2 must be flushed if a buffer which has been
290 * modified by a shader store instruction is about to be used as
291 * an index buffer. The reason is that VGT DMA index fetching doesn't
292 * use TC L2.
293 */
294 bool TC_L2_dirty;
295
296 /* Whether this resource is referenced by bindless handles. */
297 bool texture_handle_allocated;
298 bool image_handle_allocated;
299
300 /* Whether the resource has been exported via resource_get_handle. */
301 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
302 };
303
304 struct si_transfer {
305 struct threaded_transfer b;
306 struct si_resource *staging;
307 unsigned offset;
308 };
309
310 struct si_texture {
311 struct si_resource buffer;
312
313 struct radeon_surf surface;
314 struct si_texture *flushed_depth_texture;
315
316 /* One texture allocation can contain these buffers:
317 * - image (pixel data)
318 * - FMASK buffer (MSAA compression)
319 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
320 * - HTILE buffer (Z/S compression and fast Z/S clear)
321 * - DCC buffer (color compression and new fast color clear)
322 * - displayable DCC buffer (if the DCC buffer is not displayable)
323 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
324 */
325 uint64_t cmask_base_address_reg;
326 struct si_resource *cmask_buffer;
327 unsigned cb_color_info; /* fast clear enable bit */
328 unsigned color_clear_value[2];
329 unsigned last_msaa_resolve_target_micro_mode;
330 unsigned num_level0_transfers;
331 unsigned plane_index; /* other planes are different pipe_resources */
332 unsigned num_planes;
333
334 /* Depth buffer compression and fast clear. */
335 float depth_clear_value;
336 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
337 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
338 enum pipe_format db_render_format : 16;
339 uint8_t stencil_clear_value;
340 bool fmask_is_identity : 1;
341 bool tc_compatible_htile : 1;
342 bool enable_tc_compatible_htile_next_clear : 1;
343 bool htile_stencil_disabled : 1;
344 bool depth_cleared : 1; /* if it was cleared at least once */
345 bool stencil_cleared : 1; /* if it was cleared at least once */
346 bool upgraded_depth : 1; /* upgraded from unorm to Z32_FLOAT */
347 bool is_depth : 1;
348 bool db_compatible : 1;
349 bool can_sample_z : 1;
350 bool can_sample_s : 1;
351
352 /* We need to track DCC dirtiness, because st/dri usually calls
353 * flush_resource twice per frame (not a bug) and we don't wanna
354 * decompress DCC twice. Also, the dirty tracking must be done even
355 * if DCC isn't used, because it's required by the DCC usage analysis
356 * for a possible future enablement.
357 */
358 bool separate_dcc_dirty : 1;
359 bool displayable_dcc_dirty : 1;
360
361 /* Statistics gathering for the DCC enablement heuristic. */
362 bool dcc_gather_statistics : 1;
363 /* Counter that should be non-zero if the texture is bound to a
364 * framebuffer.
365 */
366 unsigned framebuffers_bound;
367 /* Whether the texture is a displayable back buffer and needs DCC
368 * decompression, which is expensive. Therefore, it's enabled only
369 * if statistics suggest that it will pay off and it's allocated
370 * separately. It can't be bound as a sampler by apps. Limited to
371 * target == 2D and last_level == 0. If enabled, dcc_offset contains
372 * the absolute GPUVM address, not the relative one.
373 */
374 struct si_resource *dcc_separate_buffer;
375 /* When DCC is temporarily disabled, the separate buffer is here. */
376 struct si_resource *last_dcc_separate_buffer;
377 /* Estimate of how much this color buffer is written to in units of
378 * full-screen draws: ps_invocations / (width * height)
379 * Shader kills, late Z, and blending with trivial discards make it
380 * inaccurate (we need to count CB updates, not PS invocations).
381 */
382 unsigned ps_draw_ratio;
383 /* The number of clears since the last DCC usage analysis. */
384 unsigned num_slow_clears;
385 };
386
387 struct si_surface {
388 struct pipe_surface base;
389
390 /* These can vary with block-compressed textures. */
391 uint16_t width0;
392 uint16_t height0;
393
394 bool color_initialized : 1;
395 bool depth_initialized : 1;
396
397 /* Misc. color flags. */
398 bool color_is_int8 : 1;
399 bool color_is_int10 : 1;
400 bool dcc_incompatible : 1;
401
402 /* Color registers. */
403 unsigned cb_color_info;
404 unsigned cb_color_view;
405 unsigned cb_color_attrib;
406 unsigned cb_color_attrib2; /* GFX9 and later */
407 unsigned cb_color_attrib3; /* GFX10 and later */
408 unsigned cb_dcc_control; /* GFX8 and later */
409 unsigned spi_shader_col_format : 8; /* no blending, no alpha-to-coverage. */
410 unsigned spi_shader_col_format_alpha : 8; /* alpha-to-coverage */
411 unsigned spi_shader_col_format_blend : 8; /* blending without alpha. */
412 unsigned spi_shader_col_format_blend_alpha : 8; /* blending with alpha. */
413
414 /* DB registers. */
415 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
416 uint64_t db_stencil_base;
417 uint64_t db_htile_data_base;
418 unsigned db_depth_info;
419 unsigned db_z_info;
420 unsigned db_z_info2; /* GFX9 only */
421 unsigned db_depth_view;
422 unsigned db_depth_size;
423 unsigned db_depth_slice;
424 unsigned db_stencil_info;
425 unsigned db_stencil_info2; /* GFX9 only */
426 unsigned db_htile_surface;
427 };
428
429 struct si_mmio_counter {
430 unsigned busy;
431 unsigned idle;
432 };
433
434 union si_mmio_counters {
435 struct si_mmio_counters_named {
436 /* For global GPU load including SDMA. */
437 struct si_mmio_counter gpu;
438
439 /* GRBM_STATUS */
440 struct si_mmio_counter spi;
441 struct si_mmio_counter gui;
442 struct si_mmio_counter ta;
443 struct si_mmio_counter gds;
444 struct si_mmio_counter vgt;
445 struct si_mmio_counter ia;
446 struct si_mmio_counter sx;
447 struct si_mmio_counter wd;
448 struct si_mmio_counter bci;
449 struct si_mmio_counter sc;
450 struct si_mmio_counter pa;
451 struct si_mmio_counter db;
452 struct si_mmio_counter cp;
453 struct si_mmio_counter cb;
454
455 /* SRBM_STATUS2 */
456 struct si_mmio_counter sdma;
457
458 /* CP_STAT */
459 struct si_mmio_counter pfp;
460 struct si_mmio_counter meq;
461 struct si_mmio_counter me;
462 struct si_mmio_counter surf_sync;
463 struct si_mmio_counter cp_dma;
464 struct si_mmio_counter scratch_ram;
465 } named;
466
467 unsigned array[sizeof(struct si_mmio_counters_named) / sizeof(unsigned)];
468 };
469
470 struct si_memory_object {
471 struct pipe_memory_object b;
472 struct pb_buffer *buf;
473 uint32_t stride;
474 };
475
476 /* Saved CS data for debugging features. */
477 struct radeon_saved_cs {
478 uint32_t *ib;
479 unsigned num_dw;
480
481 struct radeon_bo_list_item *bo_list;
482 unsigned bo_count;
483 };
484
485 struct si_screen {
486 struct pipe_screen b;
487 struct radeon_winsys *ws;
488 struct disk_cache *disk_shader_cache;
489
490 struct radeon_info info;
491 uint64_t debug_flags;
492 char renderer_string[183];
493
494 void (*make_texture_descriptor)(struct si_screen *screen, struct si_texture *tex, bool sampler,
495 enum pipe_texture_target target, enum pipe_format pipe_format,
496 const unsigned char state_swizzle[4], unsigned first_level,
497 unsigned last_level, unsigned first_layer, unsigned last_layer,
498 unsigned width, unsigned height, unsigned depth, uint32_t *state,
499 uint32_t *fmask_state);
500
501 unsigned num_vbos_in_user_sgprs;
502 unsigned pa_sc_raster_config;
503 unsigned pa_sc_raster_config_1;
504 unsigned se_tile_repeat;
505 unsigned gs_table_depth;
506 unsigned tess_offchip_block_dw_size;
507 unsigned tess_offchip_ring_size;
508 unsigned tess_factor_ring_size;
509 unsigned vgt_hs_offchip_param;
510 unsigned eqaa_force_coverage_samples;
511 unsigned eqaa_force_z_samples;
512 unsigned eqaa_force_color_samples;
513 bool has_draw_indirect_multi;
514 bool has_out_of_order_rast;
515 bool assume_no_z_fights;
516 bool commutative_blend_add;
517 bool dpbb_allowed;
518 bool dfsm_allowed;
519 bool llvm_has_working_vgpr_indexing;
520 bool use_ngg;
521 bool use_ngg_culling;
522 bool always_use_ngg_culling_all;
523 bool always_use_ngg_culling_tess;
524 bool use_ngg_streamout;
525
526 struct {
527 #define OPT_BOOL(name, dflt, description) bool name : 1;
528 #include "si_debug_options.h"
529 } options;
530
531 /* Whether shaders are monolithic (1-part) or separate (3-part). */
532 bool use_monolithic_shaders;
533 bool record_llvm_ir;
534 bool dcc_msaa_allowed;
535
536 struct slab_parent_pool pool_transfers;
537
538 /* Texture filter settings. */
539 int force_aniso; /* -1 = disabled */
540
541 /* Auxiliary context. Mainly used to initialize resources.
542 * It must be locked prior to using and flushed before unlocking. */
543 struct pipe_context *aux_context;
544 simple_mtx_t aux_context_lock;
545
546 /* This must be in the screen, because UE4 uses one context for
547 * compilation and another one for rendering.
548 */
549 unsigned num_compilations;
550 /* Along with ST_DEBUG=precompile, this should show if applications
551 * are loading shaders on demand. This is a monotonic counter.
552 */
553 unsigned num_shaders_created;
554 unsigned num_memory_shader_cache_hits;
555 unsigned num_memory_shader_cache_misses;
556 unsigned num_disk_shader_cache_hits;
557 unsigned num_disk_shader_cache_misses;
558
559 /* GPU load thread. */
560 simple_mtx_t gpu_load_mutex;
561 thrd_t gpu_load_thread;
562 union si_mmio_counters mmio_counters;
563 volatile unsigned gpu_load_stop_thread; /* bool */
564
565 /* Performance counters. */
566 struct si_perfcounters *perfcounters;
567
568 /* If pipe_screen wants to recompute and re-emit the framebuffer,
569 * sampler, and image states of all contexts, it should atomically
570 * increment this.
571 *
572 * Each context will compare this with its own last known value of
573 * the counter before drawing and re-emit the states accordingly.
574 */
575 unsigned dirty_tex_counter;
576 unsigned dirty_buf_counter;
577
578 /* Atomically increment this counter when an existing texture's
579 * metadata is enabled or disabled in a way that requires changing
580 * contexts' compressed texture binding masks.
581 */
582 unsigned compressed_colortex_counter;
583
584 struct {
585 /* Context flags to set so that all writes from earlier jobs
586 * in the CP are seen by L2 clients.
587 */
588 unsigned cp_to_L2;
589
590 /* Context flags to set so that all writes from earlier jobs
591 * that end in L2 are seen by CP.
592 */
593 unsigned L2_to_cp;
594 } barrier_flags;
595
596 simple_mtx_t shader_parts_mutex;
597 struct si_shader_part *vs_prologs;
598 struct si_shader_part *tcs_epilogs;
599 struct si_shader_part *gs_prologs;
600 struct si_shader_part *ps_prologs;
601 struct si_shader_part *ps_epilogs;
602
603 /* Shader cache in memory.
604 *
605 * Design & limitations:
606 * - The shader cache is per screen (= per process), never saved to
607 * disk, and skips redundant shader compilations from NIR to bytecode.
608 * - It can only be used with one-variant-per-shader support, in which
609 * case only the main (typically middle) part of shaders is cached.
610 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
611 * variants of VS and TES are cached, so LS and ES aren't.
612 * - GS and CS aren't cached, but it's certainly possible to cache
613 * those as well.
614 */
615 simple_mtx_t shader_cache_mutex;
616 struct hash_table *shader_cache;
617
618 /* Shader cache of live shaders. */
619 struct util_live_shader_cache live_shader_cache;
620
621 /* Shader compiler queue for multithreaded compilation. */
622 struct util_queue shader_compiler_queue;
623 /* Use at most 3 normal compiler threads on quadcore and better.
624 * Hyperthreaded CPUs report the number of threads, but we want
625 * the number of cores. We only need this many threads for shader-db. */
626 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
627
628 struct util_queue shader_compiler_queue_low_priority;
629 /* Use at most 2 low priority threads on quadcore and better.
630 * We want to minimize the impact on multithreaded Mesa. */
631 struct ac_llvm_compiler compiler_lowp[10];
632
633 unsigned compute_wave_size;
634 unsigned ps_wave_size;
635 unsigned ge_wave_size;
636 };
637
638 struct si_blend_color {
639 struct pipe_blend_color state;
640 bool any_nonzeros;
641 };
642
643 struct si_sampler_view {
644 struct pipe_sampler_view base;
645 /* [0..7] = image descriptor
646 * [4..7] = buffer descriptor */
647 uint32_t state[8];
648 uint32_t fmask_state[8];
649 const struct legacy_surf_level *base_level_info;
650 ubyte base_level;
651 ubyte block_width;
652 bool is_stencil_sampler;
653 bool is_integer;
654 bool dcc_incompatible;
655 };
656
657 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
658
659 struct si_sampler_state {
660 #ifndef NDEBUG
661 unsigned magic;
662 #endif
663 uint32_t val[4];
664 uint32_t integer_val[4];
665 uint32_t upgraded_depth_val[4];
666 };
667
668 struct si_cs_shader_state {
669 struct si_compute *program;
670 struct si_compute *emitted_program;
671 unsigned offset;
672 bool initialized;
673 bool uses_scratch;
674 };
675
676 struct si_samplers {
677 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
678 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
679
680 /* The i-th bit is set if that element is enabled (non-NULL resource). */
681 unsigned enabled_mask;
682 uint32_t needs_depth_decompress_mask;
683 uint32_t needs_color_decompress_mask;
684 };
685
686 struct si_images {
687 struct pipe_image_view views[SI_NUM_IMAGES];
688 uint32_t needs_color_decompress_mask;
689 unsigned enabled_mask;
690 };
691
692 struct si_framebuffer {
693 struct pipe_framebuffer_state state;
694 unsigned colorbuf_enabled_4bit;
695 unsigned spi_shader_col_format;
696 unsigned spi_shader_col_format_alpha;
697 unsigned spi_shader_col_format_blend;
698 unsigned spi_shader_col_format_blend_alpha;
699 ubyte nr_samples : 5; /* at most 16xAA */
700 ubyte log_samples : 3; /* at most 4 = 16xAA */
701 ubyte nr_color_samples; /* at most 8xAA */
702 ubyte compressed_cb_mask;
703 ubyte uncompressed_cb_mask;
704 ubyte displayable_dcc_cb_mask;
705 ubyte color_is_int8;
706 ubyte color_is_int10;
707 ubyte dirty_cbufs;
708 ubyte dcc_overwrite_combiner_watermark;
709 ubyte min_bytes_per_pixel;
710 bool dirty_zsbuf;
711 bool any_dst_linear;
712 bool CB_has_shader_readable_metadata;
713 bool DB_has_shader_readable_metadata;
714 bool all_DCC_pipe_aligned;
715 bool color_big_page;
716 bool zs_big_page;
717 };
718
719 enum si_quant_mode
720 {
721 /* This is the list we want to support. */
722 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
723 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
724 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
725 };
726
727 struct si_signed_scissor {
728 int minx;
729 int miny;
730 int maxx;
731 int maxy;
732 enum si_quant_mode quant_mode;
733 };
734
735 struct si_viewports {
736 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
737 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
738 bool y_inverted;
739 };
740
741 struct si_clip_state {
742 struct pipe_clip_state state;
743 bool any_nonzeros;
744 };
745
746 struct si_streamout_target {
747 struct pipe_stream_output_target b;
748
749 /* The buffer where BUFFER_FILLED_SIZE is stored. */
750 struct si_resource *buf_filled_size;
751 unsigned buf_filled_size_offset;
752 bool buf_filled_size_valid;
753
754 unsigned stride_in_dw;
755 };
756
757 struct si_streamout {
758 bool begin_emitted;
759
760 unsigned enabled_mask;
761 unsigned num_targets;
762 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
763
764 unsigned append_bitmask;
765 bool suspended;
766
767 /* External state which comes from the vertex shader,
768 * it must be set explicitly when binding a shader. */
769 uint16_t *stride_in_dw;
770 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
771
772 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
773 unsigned hw_enabled_mask;
774
775 /* The state of VGT_STRMOUT_(CONFIG|EN). */
776 bool streamout_enabled;
777 bool prims_gen_query_enabled;
778 int num_prims_gen_queries;
779 };
780
781 /* A shader state consists of the shader selector, which is a constant state
782 * object shared by multiple contexts and shouldn't be modified, and
783 * the current shader variant selected for this context.
784 */
785 struct si_shader_ctx_state {
786 struct si_shader_selector *cso;
787 struct si_shader *current;
788 };
789
790 #define SI_NUM_VGT_PARAM_KEY_BITS 12
791 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
792
793 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
794 * Some fields are set by state-change calls, most are set by draw_vbo.
795 */
796 union si_vgt_param_key {
797 struct {
798 #if UTIL_ARCH_LITTLE_ENDIAN
799 unsigned prim : 4;
800 unsigned uses_instancing : 1;
801 unsigned multi_instances_smaller_than_primgroup : 1;
802 unsigned primitive_restart : 1;
803 unsigned count_from_stream_output : 1;
804 unsigned line_stipple_enabled : 1;
805 unsigned uses_tess : 1;
806 unsigned tess_uses_prim_id : 1;
807 unsigned uses_gs : 1;
808 unsigned _pad : 32 - SI_NUM_VGT_PARAM_KEY_BITS;
809 #else /* UTIL_ARCH_BIG_ENDIAN */
810 unsigned _pad : 32 - SI_NUM_VGT_PARAM_KEY_BITS;
811 unsigned uses_gs : 1;
812 unsigned tess_uses_prim_id : 1;
813 unsigned uses_tess : 1;
814 unsigned line_stipple_enabled : 1;
815 unsigned count_from_stream_output : 1;
816 unsigned primitive_restart : 1;
817 unsigned multi_instances_smaller_than_primgroup : 1;
818 unsigned uses_instancing : 1;
819 unsigned prim : 4;
820 #endif
821 } u;
822 uint32_t index;
823 };
824
825 #define SI_NUM_VGT_STAGES_KEY_BITS 6
826 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
827
828 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
829 * Some fields are set by state-change calls, most are set by draw_vbo.
830 */
831 union si_vgt_stages_key {
832 struct {
833 #if UTIL_ARCH_LITTLE_ENDIAN
834 unsigned tess : 1;
835 unsigned gs : 1;
836 unsigned ngg_gs_fast_launch : 1;
837 unsigned ngg_passthrough : 1;
838 unsigned ngg : 1; /* gfx10+ */
839 unsigned streamout : 1; /* only used with NGG */
840 unsigned _pad : 32 - SI_NUM_VGT_STAGES_KEY_BITS;
841 #else /* UTIL_ARCH_BIG_ENDIAN */
842 unsigned _pad : 32 - SI_NUM_VGT_STAGES_KEY_BITS;
843 unsigned streamout : 1;
844 unsigned ngg : 1;
845 unsigned ngg_passthrough : 1;
846 unsigned ngg_gs_fast_launch : 1;
847 unsigned gs : 1;
848 unsigned tess : 1;
849 #endif
850 } u;
851 uint32_t index;
852 };
853
854 struct si_texture_handle {
855 unsigned desc_slot;
856 bool desc_dirty;
857 struct pipe_sampler_view *view;
858 struct si_sampler_state sstate;
859 };
860
861 struct si_image_handle {
862 unsigned desc_slot;
863 bool desc_dirty;
864 struct pipe_image_view view;
865 };
866
867 struct si_saved_cs {
868 struct pipe_reference reference;
869 struct si_context *ctx;
870 struct radeon_saved_cs gfx;
871 struct radeon_saved_cs compute;
872 struct si_resource *trace_buf;
873 unsigned trace_id;
874
875 unsigned gfx_last_dw;
876 unsigned compute_last_dw;
877 bool flushed;
878 int64_t time_flush;
879 };
880
881 struct si_sdma_upload {
882 struct si_resource *dst;
883 struct si_resource *src;
884 unsigned src_offset;
885 unsigned dst_offset;
886 unsigned size;
887 };
888
889 struct si_small_prim_cull_info {
890 float scale[2], translate[2];
891 };
892
893 struct si_context {
894 struct pipe_context b; /* base class */
895
896 enum radeon_family family;
897 enum chip_class chip_class;
898
899 struct radeon_winsys *ws;
900 struct radeon_winsys_ctx *ctx;
901 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
902 struct radeon_cmdbuf *sdma_cs;
903 struct pipe_fence_handle *last_gfx_fence;
904 struct pipe_fence_handle *last_sdma_fence;
905 struct si_resource *eop_bug_scratch;
906 struct u_upload_mgr *cached_gtt_allocator;
907 struct threaded_context *tc;
908 struct u_suballocator *allocator_zeroed_memory;
909 struct slab_child_pool pool_transfers;
910 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
911 struct pipe_device_reset_callback device_reset_callback;
912 struct u_log_context *log;
913 void *query_result_shader;
914 void *sh_query_result_shader;
915
916 void (*emit_cache_flush)(struct si_context *ctx);
917
918 struct blitter_context *blitter;
919 void *noop_blend;
920 void *noop_dsa;
921 void *discard_rasterizer_state;
922 void *custom_dsa_flush;
923 void *custom_blend_resolve;
924 void *custom_blend_fmask_decompress;
925 void *custom_blend_eliminate_fastclear;
926 void *custom_blend_dcc_decompress;
927 void *vs_blit_pos;
928 void *vs_blit_pos_layered;
929 void *vs_blit_color;
930 void *vs_blit_color_layered;
931 void *vs_blit_texcoord;
932 void *cs_clear_buffer;
933 void *cs_copy_buffer;
934 void *cs_copy_image;
935 void *cs_copy_image_1d_array;
936 void *cs_clear_render_target;
937 void *cs_clear_render_target_1d_array;
938 void *cs_clear_12bytes_buffer;
939 void *cs_dcc_decompress;
940 void *cs_dcc_retile;
941 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
942 struct si_screen *screen;
943 struct pipe_debug_callback debug;
944 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
945 struct si_shader_ctx_state fixed_func_tcs_shader;
946 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
947 struct si_resource *wait_mem_scratch;
948 unsigned wait_mem_number;
949 uint16_t prefetch_L2_mask;
950
951 bool has_graphics;
952 bool gfx_flush_in_progress : 1;
953 bool gfx_last_ib_is_busy : 1;
954 bool compute_is_busy : 1;
955
956 unsigned num_gfx_cs_flushes;
957 unsigned initial_gfx_cs_size;
958 unsigned last_dirty_tex_counter;
959 unsigned last_dirty_buf_counter;
960 unsigned last_compressed_colortex_counter;
961 unsigned last_num_draw_calls;
962 unsigned flags; /* flush flags */
963 /* Current unaccounted memory usage. */
964 uint64_t vram;
965 uint64_t gtt;
966
967 /* Compute-based primitive discard. */
968 unsigned prim_discard_vertex_count_threshold;
969 struct pb_buffer *gds;
970 struct pb_buffer *gds_oa;
971 struct radeon_cmdbuf *prim_discard_compute_cs;
972 unsigned compute_gds_offset;
973 struct si_shader *compute_ib_last_shader;
974 uint32_t compute_rewind_va;
975 unsigned compute_num_prims_in_batch;
976 bool preserve_prim_restart_gds_at_flush;
977 /* index_ring is divided into 2 halves for doublebuffering. */
978 struct si_resource *index_ring;
979 unsigned index_ring_base; /* offset of a per-IB portion */
980 unsigned index_ring_offset; /* offset within a per-IB portion */
981 unsigned index_ring_size_per_ib; /* max available size per IB */
982 bool prim_discard_compute_ib_initialized;
983 /* For tracking the last execution barrier - it can be either
984 * a WRITE_DATA packet or a fence. */
985 uint32_t *last_pkt3_write_data;
986 struct si_resource *barrier_buf;
987 unsigned barrier_buf_offset;
988 struct pipe_fence_handle *last_ib_barrier_fence;
989 struct si_resource *last_ib_barrier_buf;
990 unsigned last_ib_barrier_buf_offset;
991
992 /* Atoms (direct states). */
993 union si_state_atoms atoms;
994 unsigned dirty_atoms; /* mask */
995 /* PM4 states (precomputed immutable states) */
996 unsigned dirty_states;
997 union si_state queued;
998 union si_state emitted;
999
1000 /* Atom declarations. */
1001 struct si_framebuffer framebuffer;
1002 unsigned sample_locs_num_samples;
1003 uint16_t sample_mask;
1004 unsigned last_cb_target_mask;
1005 struct si_blend_color blend_color;
1006 struct si_clip_state clip_state;
1007 struct si_shader_data shader_pointers;
1008 struct si_stencil_ref stencil_ref;
1009 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
1010 struct si_streamout streamout;
1011 struct si_viewports viewports;
1012 unsigned num_window_rectangles;
1013 bool window_rectangles_include;
1014 struct pipe_scissor_state window_rectangles[4];
1015
1016 /* Precomputed states. */
1017 struct si_pm4_state *cs_preamble_state;
1018 struct si_pm4_state *cs_preamble_gs_rings;
1019 bool cs_preamble_has_vgt_flush;
1020 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
1021
1022 /* shaders */
1023 struct si_shader_ctx_state ps_shader;
1024 struct si_shader_ctx_state gs_shader;
1025 struct si_shader_ctx_state vs_shader;
1026 struct si_shader_ctx_state tcs_shader;
1027 struct si_shader_ctx_state tes_shader;
1028 struct si_shader_ctx_state cs_prim_discard_state;
1029 struct si_cs_shader_state cs_shader_state;
1030
1031 /* shader information */
1032 struct si_vertex_elements *vertex_elements;
1033 unsigned num_vertex_elements;
1034 unsigned sprite_coord_enable;
1035 unsigned cs_max_waves_per_sh;
1036 bool flatshade;
1037 bool do_update_shaders;
1038 bool compute_shaderbuf_sgprs_dirty;
1039 bool compute_image_sgprs_dirty;
1040
1041 /* shader descriptors */
1042 struct si_descriptors descriptors[SI_NUM_DESCS];
1043 unsigned descriptors_dirty;
1044 unsigned shader_pointers_dirty;
1045 unsigned shader_needs_decompress_mask;
1046 struct si_buffer_resources rw_buffers;
1047 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1048 struct si_samplers samplers[SI_NUM_SHADERS];
1049 struct si_images images[SI_NUM_SHADERS];
1050 bool bo_list_add_all_resident_resources;
1051 bool bo_list_add_all_gfx_resources;
1052 bool bo_list_add_all_compute_resources;
1053
1054 /* other shader resources */
1055 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1056 struct pipe_resource *esgs_ring;
1057 struct pipe_resource *gsvs_ring;
1058 struct pipe_resource *tess_rings;
1059 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1060 struct si_resource *border_color_buffer;
1061 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1062 unsigned border_color_count;
1063 unsigned num_vs_blit_sgprs;
1064 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1065 uint32_t cs_user_data[4];
1066
1067 /* Vertex buffers. */
1068 bool vertex_buffers_dirty;
1069 bool vertex_buffer_pointer_dirty;
1070 bool vertex_buffer_user_sgprs_dirty;
1071 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1072 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1073 uint32_t *vb_descriptors_gpu_list;
1074 struct si_resource *vb_descriptors_buffer;
1075 unsigned vb_descriptors_offset;
1076 unsigned vb_descriptor_user_sgprs[5 * 4];
1077
1078 /* MSAA config state. */
1079 int ps_iter_samples;
1080 bool ps_uses_fbfetch;
1081 bool smoothing_enabled;
1082
1083 /* DB render state. */
1084 unsigned ps_db_shader_control;
1085 unsigned dbcb_copy_sample;
1086 bool dbcb_depth_copy_enabled : 1;
1087 bool dbcb_stencil_copy_enabled : 1;
1088 bool db_flush_depth_inplace : 1;
1089 bool db_flush_stencil_inplace : 1;
1090 bool db_depth_clear : 1;
1091 bool db_depth_disable_expclear : 1;
1092 bool db_stencil_clear : 1;
1093 bool db_stencil_disable_expclear : 1;
1094 bool occlusion_queries_disabled : 1;
1095 bool generate_mipmap_for_depth : 1;
1096
1097 /* Emitted draw state. */
1098 bool gs_tri_strip_adj_fix : 1;
1099 bool ls_vgpr_fix : 1;
1100 bool prim_discard_cs_instancing : 1;
1101 bool ngg : 1;
1102 uint8_t ngg_culling;
1103 int last_index_size;
1104 int last_base_vertex;
1105 int last_start_instance;
1106 int last_instance_count;
1107 int last_drawid;
1108 int last_sh_base_reg;
1109 int last_primitive_restart_en;
1110 int last_restart_index;
1111 int last_prim;
1112 int last_multi_vgt_param;
1113 int last_gs_out_prim;
1114 int last_binning_enabled;
1115 unsigned current_vs_state;
1116 unsigned last_vs_state;
1117 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1118
1119 struct si_small_prim_cull_info last_small_prim_cull_info;
1120 struct si_resource *small_prim_cull_info_buf;
1121 uint64_t small_prim_cull_info_address;
1122 bool small_prim_cull_info_dirty;
1123
1124 /* Scratch buffer */
1125 struct si_resource *scratch_buffer;
1126 unsigned scratch_waves;
1127 unsigned spi_tmpring_size;
1128 unsigned max_seen_scratch_bytes_per_wave;
1129 unsigned max_seen_compute_scratch_bytes_per_wave;
1130
1131 struct si_resource *compute_scratch_buffer;
1132
1133 /* Emitted derived tessellation state. */
1134 /* Local shader (VS), or HS if LS-HS are merged. */
1135 struct si_shader *last_ls;
1136 struct si_shader_selector *last_tcs;
1137 int last_num_tcs_input_cp;
1138 int last_tes_sh_base;
1139 bool last_tess_uses_primid;
1140 unsigned last_num_patches;
1141 int last_ls_hs_config;
1142
1143 /* Debug state. */
1144 bool is_debug;
1145 struct si_saved_cs *current_saved_cs;
1146 uint64_t dmesg_timestamp;
1147 unsigned apitrace_call_number;
1148
1149 /* Other state */
1150 bool need_check_render_feedback;
1151 bool decompression_enabled;
1152 bool dpbb_force_off;
1153 bool vs_writes_viewport_index;
1154 bool vs_disables_clipping_viewport;
1155
1156 /* Precomputed IA_MULTI_VGT_PARAM */
1157 union si_vgt_param_key ia_multi_vgt_param_key;
1158 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1159
1160 /* Bindless descriptors. */
1161 struct si_descriptors bindless_descriptors;
1162 struct util_idalloc bindless_used_slots;
1163 unsigned num_bindless_descriptors;
1164 bool bindless_descriptors_dirty;
1165 bool graphics_bindless_pointer_dirty;
1166 bool compute_bindless_pointer_dirty;
1167
1168 /* Allocated bindless handles */
1169 struct hash_table *tex_handles;
1170 struct hash_table *img_handles;
1171
1172 /* Resident bindless handles */
1173 struct util_dynarray resident_tex_handles;
1174 struct util_dynarray resident_img_handles;
1175
1176 /* Resident bindless handles which need decompression */
1177 struct util_dynarray resident_tex_needs_color_decompress;
1178 struct util_dynarray resident_img_needs_color_decompress;
1179 struct util_dynarray resident_tex_needs_depth_decompress;
1180
1181 /* Bindless state */
1182 bool uses_bindless_samplers;
1183 bool uses_bindless_images;
1184
1185 /* MSAA sample locations.
1186 * The first index is the sample index.
1187 * The second index is the coordinate: X, Y. */
1188 struct {
1189 float x1[1][2];
1190 float x2[2][2];
1191 float x4[4][2];
1192 float x8[8][2];
1193 float x16[16][2];
1194 } sample_positions;
1195 struct pipe_resource *sample_pos_buffer;
1196
1197 /* Misc stats. */
1198 unsigned num_draw_calls;
1199 unsigned num_decompress_calls;
1200 unsigned num_mrt_draw_calls;
1201 unsigned num_prim_restart_calls;
1202 unsigned num_spill_draw_calls;
1203 unsigned num_compute_calls;
1204 unsigned num_spill_compute_calls;
1205 unsigned num_dma_calls;
1206 unsigned num_cp_dma_calls;
1207 unsigned num_vs_flushes;
1208 unsigned num_ps_flushes;
1209 unsigned num_cs_flushes;
1210 unsigned num_cb_cache_flushes;
1211 unsigned num_db_cache_flushes;
1212 unsigned num_L2_invalidates;
1213 unsigned num_L2_writebacks;
1214 unsigned num_resident_handles;
1215 uint64_t num_alloc_tex_transfer_bytes;
1216 unsigned last_tex_ps_draw_ratio; /* for query */
1217 unsigned compute_num_verts_accepted;
1218 unsigned compute_num_verts_rejected;
1219 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1220 unsigned context_roll;
1221
1222 /* Queries. */
1223 /* Maintain the list of active queries for pausing between IBs. */
1224 int num_occlusion_queries;
1225 int num_perfect_occlusion_queries;
1226 int num_pipeline_stat_queries;
1227 struct list_head active_queries;
1228 unsigned num_cs_dw_queries_suspend;
1229
1230 /* Render condition. */
1231 struct pipe_query *render_cond;
1232 unsigned render_cond_mode;
1233 bool render_cond_invert;
1234 bool render_cond_force_off; /* for u_blitter */
1235
1236 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1237 bool sdma_uploads_in_progress;
1238 struct si_sdma_upload *sdma_uploads;
1239 unsigned num_sdma_uploads;
1240 unsigned max_sdma_uploads;
1241
1242 /* Shader-based queries. */
1243 struct list_head shader_query_buffers;
1244 unsigned num_active_shader_queries;
1245
1246 /* Statistics gathering for the DCC enablement heuristic. It can't be
1247 * in si_texture because si_texture can be shared by multiple
1248 * contexts. This is for back buffers only. We shouldn't get too many
1249 * of those.
1250 *
1251 * X11 DRI3 rotates among a finite set of back buffers. They should
1252 * all fit in this array. If they don't, separate DCC might never be
1253 * enabled by DCC stat gathering.
1254 */
1255 struct {
1256 struct si_texture *tex;
1257 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1258 struct pipe_query *ps_stats[3];
1259 /* If all slots are used and another slot is needed,
1260 * the least recently used slot is evicted based on this. */
1261 int64_t last_use_timestamp;
1262 bool query_active;
1263 } dcc_stats[5];
1264
1265 /* Copy one resource to another using async DMA. */
1266 void (*dma_copy)(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dst_level,
1267 unsigned dst_x, unsigned dst_y, unsigned dst_z, struct pipe_resource *src,
1268 unsigned src_level, const struct pipe_box *src_box);
1269
1270 struct si_tracked_regs tracked_regs;
1271 };
1272
1273 /* cik_sdma.c */
1274 void cik_init_sdma_functions(struct si_context *sctx);
1275
1276 /* si_blit.c */
1277 enum si_blitter_op /* bitmask */
1278 {
1279 SI_SAVE_TEXTURES = 1,
1280 SI_SAVE_FRAMEBUFFER = 2,
1281 SI_SAVE_FRAGMENT_STATE = 4,
1282 SI_DISABLE_RENDER_COND = 8,
1283 };
1284
1285 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1286 void si_blitter_end(struct si_context *sctx);
1287 void si_init_blit_functions(struct si_context *sctx);
1288 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1289 void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
1290 unsigned level, unsigned first_layer, unsigned last_layer);
1291 void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
1292 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1293 struct pipe_resource *src, unsigned src_level,
1294 const struct pipe_box *src_box);
1295 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1296
1297 /* si_buffer.c */
1298 bool si_rings_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf,
1299 enum radeon_bo_usage usage);
1300 void *si_buffer_map_sync_with_rings(struct si_context *sctx, struct si_resource *resource,
1301 unsigned usage);
1302 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1303 unsigned alignment);
1304 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1305 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1306 unsigned usage, unsigned size, unsigned alignment);
1307 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1308 unsigned usage, unsigned size, unsigned alignment);
1309 void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst,
1310 struct pipe_resource *src);
1311 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1312 void si_init_buffer_functions(struct si_context *sctx);
1313
1314 /* si_clear.c */
1315 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1316 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1317 bool vi_dcc_clear_level(struct si_context *sctx, struct si_texture *tex, unsigned level,
1318 unsigned clear_value);
1319 void si_init_clear_functions(struct si_context *sctx);
1320
1321 /* si_compute_blit.c */
1322 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1323 enum si_cache_policy cache_policy);
1324 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset,
1325 uint64_t size, uint32_t *clear_value, uint32_t clear_value_size,
1326 enum si_coherency coher, bool force_cpdma);
1327 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1328 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1329 void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1330 struct pipe_resource *src, unsigned src_level, unsigned dstx,
1331 unsigned dsty, unsigned dstz, const struct pipe_box *src_box,
1332 bool is_dcc_decompress);
1333 void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dstsurf,
1334 const union pipe_color_union *color, unsigned dstx,
1335 unsigned dsty, unsigned width, unsigned height,
1336 bool render_condition_enabled);
1337 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1338 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1339 void si_init_compute_blit_functions(struct si_context *sctx);
1340
1341 /* si_cp_dma.c */
1342 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1343 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1344 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1345 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1346 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1347 #define SI_CPDMA_SKIP_TMZ (1 << 5) /* don't update tmz state */
1348 #define SI_CPDMA_SKIP_ALL \
1349 (SI_CPDMA_SKIP_CHECK_CS_SPACE | SI_CPDMA_SKIP_SYNC_AFTER | SI_CPDMA_SKIP_SYNC_BEFORE | \
1350 SI_CPDMA_SKIP_GFX_SYNC | SI_CPDMA_SKIP_BO_LIST_UPDATE | SI_CPDMA_SKIP_TMZ)
1351
1352 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1353 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1354 struct pipe_resource *dst, uint64_t offset, uint64_t size,
1355 unsigned value, unsigned user_flags, enum si_coherency coher,
1356 enum si_cache_policy cache_policy);
1357 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1358 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1359 unsigned size, unsigned user_flags, enum si_coherency coher,
1360 enum si_cache_policy cache_policy);
1361 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf, uint64_t offset,
1362 unsigned size);
1363 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1364 void si_test_gds(struct si_context *sctx);
1365 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1366 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1367 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1368 struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
1369 struct si_resource *src, unsigned src_offset);
1370
1371 /* si_debug.c */
1372 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1373 bool get_buffer_list);
1374 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1375 void si_destroy_saved_cs(struct si_saved_cs *scs);
1376 void si_auto_log_cs(void *data, struct u_log_context *log);
1377 void si_log_hw_flush(struct si_context *sctx);
1378 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1379 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1380 void si_init_debug_functions(struct si_context *sctx);
1381 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved,
1382 enum ring_type ring);
1383 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1384
1385 /* si_dma_cs.c */
1386 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst, uint64_t offset);
1387 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset,
1388 uint64_t size, unsigned clear_value);
1389 void si_sdma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1390 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1391 uint64_t size);
1392 void si_need_dma_space(struct si_context *ctx, unsigned num_dw, struct si_resource *dst,
1393 struct si_resource *src);
1394 void si_flush_dma_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1395 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset,
1396 uint64_t size, unsigned value);
1397
1398 /* si_fence.c */
1399 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1400 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1401 struct si_resource *buf, uint64_t va, uint32_t new_fence,
1402 unsigned query_type);
1403 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1404 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1405 uint32_t mask, unsigned flags);
1406 void si_init_fence_functions(struct si_context *ctx);
1407 void si_init_screen_fence_functions(struct si_screen *screen);
1408 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1409 struct tc_unflushed_batch_token *tc_token);
1410
1411 /* si_get.c */
1412 void si_init_screen_get_functions(struct si_screen *sscreen);
1413
1414 /* si_gfx_cs.c */
1415 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1416 void si_allocate_gds(struct si_context *ctx);
1417 void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
1418 void si_begin_new_gfx_cs(struct si_context *ctx);
1419 void si_need_gfx_cs_space(struct si_context *ctx);
1420 void si_unref_sdma_uploads(struct si_context *sctx);
1421
1422 /* si_gpu_load.c */
1423 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1424 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1425 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1426
1427 /* si_compute.c */
1428 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1429 void si_init_compute_functions(struct si_context *sctx);
1430
1431 /* si_compute_prim_discard.c */
1432 enum si_prim_discard_outcome
1433 {
1434 SI_PRIM_DISCARD_ENABLED,
1435 SI_PRIM_DISCARD_DISABLED,
1436 SI_PRIM_DISCARD_DRAW_SPLIT,
1437 };
1438
1439 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1440 enum si_prim_discard_outcome
1441 si_prepare_prim_discard_or_split_draw(struct si_context *sctx, const struct pipe_draw_info *info,
1442 bool primitive_restart);
1443 void si_compute_signal_gfx(struct si_context *sctx);
1444 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1445 const struct pipe_draw_info *info, unsigned index_size,
1446 unsigned base_vertex, uint64_t input_indexbuf_va,
1447 unsigned input_indexbuf_max_elements);
1448 void si_initialize_prim_discard_tunables(struct si_screen *sscreen, bool is_aux_context,
1449 unsigned *prim_discard_vertex_count_threshold,
1450 unsigned *index_ring_size_per_ib);
1451
1452 /* si_pipe.c */
1453 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler);
1454
1455 /* si_perfcounters.c */
1456 void si_init_perfcounters(struct si_screen *screen);
1457 void si_destroy_perfcounters(struct si_screen *screen);
1458
1459 /* si_query.c */
1460 void si_init_screen_query_functions(struct si_screen *sscreen);
1461 void si_init_query_functions(struct si_context *sctx);
1462 void si_suspend_queries(struct si_context *sctx);
1463 void si_resume_queries(struct si_context *sctx);
1464
1465 /* si_shaderlib_tgsi.c */
1466 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1467 unsigned num_layers);
1468 void *si_create_fixed_func_tcs(struct si_context *sctx);
1469 void *si_create_dma_compute_shader(struct pipe_context *ctx, unsigned num_dwords_per_thread,
1470 bool dst_stream_cache_policy, bool is_copy);
1471 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1472 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1473 void *si_create_dcc_decompress_cs(struct pipe_context *ctx);
1474 void *si_clear_render_target_shader(struct pipe_context *ctx);
1475 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1476 void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx);
1477 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1478 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples, bool is_array);
1479 void *si_create_query_result_cs(struct si_context *sctx);
1480 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1481
1482 /* gfx10_query.c */
1483 void gfx10_init_query(struct si_context *sctx);
1484 void gfx10_destroy_query(struct si_context *sctx);
1485
1486 /* si_test_dma.c */
1487 void si_test_dma(struct si_screen *sscreen);
1488
1489 /* si_test_clearbuffer.c */
1490 void si_test_dma_perf(struct si_screen *sscreen);
1491
1492 /* si_uvd.c */
1493 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1494 const struct pipe_video_codec *templ);
1495
1496 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1497 const struct pipe_video_buffer *tmpl);
1498
1499 /* si_viewport.c */
1500 void si_update_ngg_small_prim_precision(struct si_context *ctx);
1501 void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_cull_info *out);
1502 void si_update_vs_viewport_state(struct si_context *ctx);
1503 void si_init_viewport_functions(struct si_context *ctx);
1504
1505 /* si_texture.c */
1506 bool si_prepare_for_dma_blit(struct si_context *sctx, struct si_texture *dst, unsigned dst_level,
1507 unsigned dstx, unsigned dsty, unsigned dstz, struct si_texture *src,
1508 unsigned src_level, const struct pipe_box *src_box);
1509 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1510 bool *ctx_flushed);
1511 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex);
1512 bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture);
1513 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
1514 struct u_log_context *log);
1515 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1516 const struct pipe_resource *templ);
1517 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1,
1518 enum pipe_format format2);
1519 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level,
1520 enum pipe_format view_format);
1521 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1522 unsigned level, enum pipe_format view_format);
1523 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1524 struct pipe_resource *texture,
1525 const struct pipe_surface *templ, unsigned width0,
1526 unsigned height0, unsigned width, unsigned height);
1527 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1528 void vi_separate_dcc_try_enable(struct si_context *sctx, struct si_texture *tex);
1529 void vi_separate_dcc_start_query(struct si_context *sctx, struct si_texture *tex);
1530 void vi_separate_dcc_stop_query(struct si_context *sctx, struct si_texture *tex);
1531 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx, struct si_texture *tex);
1532 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1533 void si_init_screen_texture_functions(struct si_screen *sscreen);
1534 void si_init_context_texture_functions(struct si_context *sctx);
1535
1536 /*
1537 * common helpers
1538 */
1539
1540 static inline struct si_resource *si_resource(struct pipe_resource *r)
1541 {
1542 return (struct si_resource *)r;
1543 }
1544
1545 static inline void si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1546 {
1547 pipe_resource_reference((struct pipe_resource **)ptr, (struct pipe_resource *)res);
1548 }
1549
1550 static inline void si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1551 {
1552 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1553 }
1554
1555 static inline void
1556 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */
1557 struct si_shader_selector **dst, struct si_shader_selector *src)
1558 {
1559 if (*dst == src)
1560 return;
1561
1562 struct si_screen *sscreen = src ? src->screen : (*dst)->screen;
1563 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src);
1564 }
1565
1566 static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level)
1567 {
1568 return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels;
1569 }
1570
1571 static inline unsigned si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1572 {
1573 if (stencil)
1574 return tex->surface.u.legacy.stencil_tiling_index[level];
1575 else
1576 return tex->surface.u.legacy.tiling_index[level];
1577 }
1578
1579 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1580 {
1581 /* Don't count the needed CS space exactly and just use an upper bound.
1582 *
1583 * Also reserve space for stopping queries at the end of IB, because
1584 * the number of active queries is unlimited in theory.
1585 */
1586 return 2048 + sctx->num_cs_dw_queries_suspend;
1587 }
1588
1589 static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1590 {
1591 if (r) {
1592 /* Add memory usage for need_gfx_cs_space */
1593 sctx->vram += si_resource(r)->vram_usage;
1594 sctx->gtt += si_resource(r)->gart_usage;
1595 }
1596 }
1597
1598 static inline void si_invalidate_draw_sh_constants(struct si_context *sctx)
1599 {
1600 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1601 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1602 }
1603
1604 static inline unsigned si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1605 {
1606 return 1 << (atom - sctx->atoms.array);
1607 }
1608
1609 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1610 {
1611 unsigned bit = si_get_atom_bit(sctx, atom);
1612
1613 if (dirty)
1614 sctx->dirty_atoms |= bit;
1615 else
1616 sctx->dirty_atoms &= ~bit;
1617 }
1618
1619 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1620 {
1621 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1622 }
1623
1624 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1625 {
1626 si_set_atom_dirty(sctx, atom, true);
1627 }
1628
1629 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1630 {
1631 if (sctx->gs_shader.cso)
1632 return &sctx->gs_shader;
1633 if (sctx->tes_shader.cso)
1634 return &sctx->tes_shader;
1635
1636 return &sctx->vs_shader;
1637 }
1638
1639 static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
1640 {
1641 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1642
1643 return vs->cso ? &vs->cso->info : NULL;
1644 }
1645
1646 static inline struct si_shader *si_get_vs_state(struct si_context *sctx)
1647 {
1648 if (sctx->gs_shader.cso && sctx->gs_shader.current && !sctx->gs_shader.current->key.as_ngg)
1649 return sctx->gs_shader.cso->gs_copy_shader;
1650
1651 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1652 return vs->current ? vs->current : NULL;
1653 }
1654
1655 static inline bool si_can_dump_shader(struct si_screen *sscreen, unsigned processor)
1656 {
1657 return sscreen->debug_flags & (1 << processor);
1658 }
1659
1660 static inline bool si_get_strmout_en(struct si_context *sctx)
1661 {
1662 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;
1663 }
1664
1665 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1666 {
1667 unsigned alignment, tcc_cache_line_size;
1668
1669 /* If the upload size is less than the cache line size (e.g. 16, 32),
1670 * the whole thing will fit into a cache line if we align it to its size.
1671 * The idea is that multiple small uploads can share a cache line.
1672 * If the upload size is greater, align it to the cache line size.
1673 */
1674 alignment = util_next_power_of_two(upload_size);
1675 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1676 return MIN2(alignment, tcc_cache_line_size);
1677 }
1678
1679 static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1680 {
1681 if (pipe_reference(&(*dst)->reference, &src->reference))
1682 si_destroy_saved_cs(*dst);
1683
1684 *dst = src;
1685 }
1686
1687 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1688 bool shaders_read_metadata, bool dcc_pipe_aligned)
1689 {
1690 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE;
1691
1692 if (sctx->chip_class >= GFX10) {
1693 if (sctx->screen->info.tcc_harvested)
1694 sctx->flags |= SI_CONTEXT_INV_L2;
1695 else if (shaders_read_metadata)
1696 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1697 } else if (sctx->chip_class == GFX9) {
1698 /* Single-sample color is coherent with shaders on GFX9, but
1699 * L2 metadata must be flushed if shaders read metadata.
1700 * (DCC, CMASK).
1701 */
1702 if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned))
1703 sctx->flags |= SI_CONTEXT_INV_L2;
1704 else if (shaders_read_metadata)
1705 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1706 } else {
1707 /* GFX6-GFX8 */
1708 sctx->flags |= SI_CONTEXT_INV_L2;
1709 }
1710 }
1711
1712 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1713 bool include_stencil, bool shaders_read_metadata)
1714 {
1715 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
1716
1717 if (sctx->chip_class >= GFX10) {
1718 if (sctx->screen->info.tcc_harvested)
1719 sctx->flags |= SI_CONTEXT_INV_L2;
1720 else if (shaders_read_metadata)
1721 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1722 } else if (sctx->chip_class == GFX9) {
1723 /* Single-sample depth (not stencil) is coherent with shaders
1724 * on GFX9, but L2 metadata must be flushed if shaders read
1725 * metadata.
1726 */
1727 if (num_samples >= 2 || include_stencil)
1728 sctx->flags |= SI_CONTEXT_INV_L2;
1729 else if (shaders_read_metadata)
1730 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1731 } else {
1732 /* GFX6-GFX8 */
1733 sctx->flags |= SI_CONTEXT_INV_L2;
1734 }
1735 }
1736
1737 static inline bool si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1738 {
1739 return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z);
1740 }
1741
1742 static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1743 {
1744 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1745 return false;
1746
1747 return tex->surface.htile_offset && level == 0;
1748 }
1749
1750 static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,
1751 unsigned zs_mask)
1752 {
1753 assert(!tex->tc_compatible_htile || tex->surface.htile_offset);
1754 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1755 }
1756
1757 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1758 {
1759 if (sctx->ps_uses_fbfetch)
1760 return sctx->framebuffer.nr_color_samples;
1761
1762 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1763 }
1764
1765 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1766 {
1767 if (sctx->queued.named.rasterizer->rasterizer_discard)
1768 return 0;
1769
1770 struct si_shader_selector *ps = sctx->ps_shader.cso;
1771 if (!ps)
1772 return 0;
1773
1774 unsigned colormask =
1775 sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask;
1776
1777 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1778 colormask &= ps->colors_written_4bit;
1779 else if (!ps->colors_written_4bit)
1780 colormask = 0; /* color0 writes all cbufs, but it's not written */
1781
1782 return colormask;
1783 }
1784
1785 #define UTIL_ALL_PRIM_LINE_MODES \
1786 ((1 << PIPE_PRIM_LINES) | (1 << PIPE_PRIM_LINE_LOOP) | (1 << PIPE_PRIM_LINE_STRIP) | \
1787 (1 << PIPE_PRIM_LINES_ADJACENCY) | (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1788
1789 static inline bool util_prim_is_lines(unsigned prim)
1790 {
1791 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1792 }
1793
1794 static inline bool util_prim_is_points_or_lines(unsigned prim)
1795 {
1796 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | (1 << PIPE_PRIM_POINTS))) != 0;
1797 }
1798
1799 static inline bool util_rast_prim_is_triangles(unsigned prim)
1800 {
1801 return ((1 << prim) &
1802 ((1 << PIPE_PRIM_TRIANGLES) | (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1803 (1 << PIPE_PRIM_TRIANGLE_FAN) | (1 << PIPE_PRIM_QUADS) | (1 << PIPE_PRIM_QUAD_STRIP) |
1804 (1 << PIPE_PRIM_POLYGON) | (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1805 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1806 }
1807
1808 /**
1809 * Return true if there is enough memory in VRAM and GTT for the buffers
1810 * added so far.
1811 *
1812 * \param vram VRAM memory size not added to the buffer list yet
1813 * \param gtt GTT memory size not added to the buffer list yet
1814 */
1815 static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, struct radeon_cmdbuf *cs,
1816 uint64_t vram, uint64_t gtt)
1817 {
1818 vram += cs->used_vram;
1819 gtt += cs->used_gart;
1820
1821 /* Anything that goes above the VRAM size should go to GTT. */
1822 if (vram > screen->info.vram_size)
1823 gtt += vram - screen->info.vram_size;
1824
1825 /* Now we just need to check if we have enough GTT. */
1826 return gtt < screen->info.gart_size * 0.7;
1827 }
1828
1829 /**
1830 * Add a buffer to the buffer list for the given command stream (CS).
1831 *
1832 * All buffers used by a CS must be added to the list. This tells the kernel
1833 * driver which buffers are used by GPU commands. Other buffers can
1834 * be swapped out (not accessible) during execution.
1835 *
1836 * The buffer list becomes empty after every context flush and must be
1837 * rebuilt.
1838 */
1839 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
1840 struct si_resource *bo, enum radeon_bo_usage usage,
1841 enum radeon_bo_priority priority)
1842 {
1843 assert(usage);
1844 sctx->ws->cs_add_buffer(cs, bo->buf, (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1845 bo->domains, priority);
1846 }
1847
1848 /**
1849 * Same as above, but also checks memory usage and flushes the context
1850 * accordingly.
1851 *
1852 * When this SHOULD NOT be used:
1853 *
1854 * - if si_context_add_resource_size has been called for the buffer
1855 * followed by *_need_cs_space for checking the memory usage
1856 *
1857 * - if si_need_dma_space has been called for the buffer
1858 *
1859 * - when emitting state packets and draw packets (because preceding packets
1860 * can't be re-emitted at that point)
1861 *
1862 * - if shader resource "enabled_mask" is not up-to-date or there is
1863 * a different constraint disallowing a context flush
1864 */
1865 static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1866 struct si_resource *bo,
1867 enum radeon_bo_usage usage,
1868 enum radeon_bo_priority priority,
1869 bool check_mem)
1870 {
1871 if (check_mem &&
1872 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs, sctx->vram + bo->vram_usage,
1873 sctx->gtt + bo->gart_usage))
1874 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1875
1876 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1877 }
1878
1879 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1880 {
1881 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1882 }
1883
1884 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1885 enum pipe_shader_type shader_type, bool ngg, bool es,
1886 bool gs_fast_launch, bool prim_discard_cs)
1887 {
1888 if (shader_type == PIPE_SHADER_COMPUTE)
1889 return sscreen->compute_wave_size;
1890 else if (shader_type == PIPE_SHADER_FRAGMENT)
1891 return sscreen->ps_wave_size;
1892 else if (gs_fast_launch)
1893 return 32; /* GS fast launch hangs with Wave64, so always use Wave32. */
1894 else if ((shader_type == PIPE_SHADER_VERTEX && prim_discard_cs) || /* only Wave64 implemented */
1895 (shader_type == PIPE_SHADER_VERTEX && es && !ngg) ||
1896 (shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1897 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1898 return 64;
1899 else
1900 return sscreen->ge_wave_size;
1901 }
1902
1903 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1904 {
1905 return si_get_wave_size(shader->selector->screen, shader->selector->type, shader->key.as_ngg,
1906 shader->key.as_es,
1907 shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL,
1908 shader->key.opt.vs_as_prim_discard_cs);
1909 }
1910
1911 #define PRINT_ERR(fmt, args...) \
1912 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1913
1914 #endif