2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "si_shader.h"
31 #include "util/u_dynarray.h"
33 #ifdef PIPE_ARCH_BIG_ENDIAN
34 #define SI_BIG_ENDIAN 1
36 #define SI_BIG_ENDIAN 0
39 /* The base vertex and primitive restart can be any number, but we must pick
40 * one which will mean "unknown" for the purpose of state tracking and
41 * the number shouldn't be a commonly-used one. */
42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
45 #define SI_GS_PER_ES 128
46 /* Alignment for optimal CP DMA performance. */
47 #define SI_CPDMA_ALIGNMENT 32
49 /* Instruction cache. */
50 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
51 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
52 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
53 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
54 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
55 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
56 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
57 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
58 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
59 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
61 /* Framebuffer caches. */
62 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 7)
63 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8)
64 /* Engine synchronization. */
65 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
66 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
67 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
68 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
69 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
71 #define SI_MAX_BORDER_COLORS 4096
76 struct u_suballocator
;
79 struct r600_common_screen b
;
80 unsigned gs_table_depth
;
81 unsigned tess_offchip_block_dw_size
;
82 bool has_distributed_tess
;
83 bool has_draw_indirect_multi
;
85 bool has_msaa_sample_loc_bug
;
86 bool llvm_has_working_vgpr_indexing
;
88 /* Whether shaders are monolithic (1-part) or separate (3-part). */
89 bool use_monolithic_shaders
;
92 mtx_t shader_parts_mutex
;
93 struct si_shader_part
*vs_prologs
;
94 struct si_shader_part
*tcs_epilogs
;
95 struct si_shader_part
*gs_prologs
;
96 struct si_shader_part
*ps_prologs
;
97 struct si_shader_part
*ps_epilogs
;
99 /* Shader cache in memory.
101 * Design & limitations:
102 * - The shader cache is per screen (= per process), never saved to
103 * disk, and skips redundant shader compilations from TGSI to bytecode.
104 * - It can only be used with one-variant-per-shader support, in which
105 * case only the main (typically middle) part of shaders is cached.
106 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
107 * variants of VS and TES are cached, so LS and ES aren't.
108 * - GS and CS aren't cached, but it's certainly possible to cache
111 mtx_t shader_cache_mutex
;
112 struct hash_table
*shader_cache
;
114 /* Shader compiler queue for multithreaded compilation. */
115 struct util_queue shader_compiler_queue
;
116 /* Use at most 3 normal compiler threads on quadcore and better.
117 * Hyperthreaded CPUs report the number of threads, but we want
118 * the number of cores. */
119 LLVMTargetMachineRef tm
[3]; /* used by the queue only */
121 struct util_queue shader_compiler_queue_low_priority
;
122 /* Use at most 2 low priority threads on quadcore and better.
123 * We want to minimize the impact on multithreaded Mesa. */
124 LLVMTargetMachineRef tm_low_priority
[2]; /* at most 2 threads */
127 struct si_blend_color
{
128 struct r600_atom atom
;
129 struct pipe_blend_color state
;
133 struct si_sampler_view
{
134 struct pipe_sampler_view base
;
135 /* [0..7] = image descriptor
136 * [4..7] = buffer descriptor */
138 uint32_t fmask_state
[8];
139 const struct legacy_surf_level
*base_level_info
;
142 bool is_stencil_sampler
;
143 bool dcc_incompatible
;
146 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
148 struct si_sampler_state
{
155 struct si_cs_shader_state
{
156 struct si_compute
*program
;
157 struct si_compute
*emitted_program
;
163 struct si_textures_info
{
164 struct si_sampler_views views
;
165 uint32_t needs_depth_decompress_mask
;
166 uint32_t needs_color_decompress_mask
;
169 struct si_images_info
{
170 struct pipe_image_view views
[SI_NUM_IMAGES
];
171 uint32_t needs_color_decompress_mask
;
172 unsigned enabled_mask
;
175 struct si_framebuffer
{
176 struct r600_atom atom
;
177 struct pipe_framebuffer_state state
;
178 unsigned colorbuf_enabled_4bit
;
179 unsigned spi_shader_col_format
;
180 unsigned spi_shader_col_format_alpha
;
181 unsigned spi_shader_col_format_blend
;
182 unsigned spi_shader_col_format_blend_alpha
;
183 ubyte nr_samples
:5; /* at most 16xAA */
184 ubyte log_samples
:3; /* at most 4 = 16xAA */
185 ubyte compressed_cb_mask
;
187 ubyte color_is_int10
;
193 struct si_clip_state
{
194 struct r600_atom atom
;
195 struct pipe_clip_state state
;
199 struct si_sample_locs
{
200 struct r600_atom atom
;
204 struct si_sample_mask
{
205 struct r600_atom atom
;
206 uint16_t sample_mask
;
209 /* A shader state consists of the shader selector, which is a constant state
210 * object shared by multiple contexts and shouldn't be modified, and
211 * the current shader variant selected for this context.
213 struct si_shader_ctx_state
{
214 struct si_shader_selector
*cso
;
215 struct si_shader
*current
;
218 #define SI_NUM_VGT_PARAM_KEY_BITS 12
219 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
221 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
222 * Some fields are set by state-change calls, most are set by draw_vbo.
224 union si_vgt_param_key
{
227 unsigned uses_instancing
:1;
228 unsigned multi_instances_smaller_than_primgroup
:1;
229 unsigned primitive_restart
:1;
230 unsigned count_from_stream_output
:1;
231 unsigned line_stipple_enabled
:1;
232 unsigned uses_tess
:1;
233 unsigned tess_uses_prim_id
:1;
235 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
240 struct si_bindless_descriptor
242 struct pb_slab_entry entry
;
243 struct r600_resource
*buffer
;
245 uint32_t desc_list
[16];
249 struct si_texture_handle
251 struct si_bindless_descriptor
*desc
;
252 struct pipe_sampler_view
*view
;
253 struct si_sampler_state sstate
;
256 struct si_image_handle
258 struct si_bindless_descriptor
*desc
;
259 struct pipe_image_view view
;
263 struct r600_common_context b
;
264 struct blitter_context
*blitter
;
265 void *custom_dsa_flush
;
266 void *custom_blend_resolve
;
267 void *custom_blend_fmask_decompress
;
268 void *custom_blend_eliminate_fastclear
;
269 void *custom_blend_dcc_decompress
;
270 struct si_screen
*screen
;
271 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
272 struct si_shader_ctx_state fixed_func_tcs_shader
;
273 struct r600_resource
*wait_mem_scratch
;
274 unsigned wait_mem_number
;
276 struct radeon_winsys_cs
*ce_ib
;
277 struct radeon_winsys_cs
*ce_preamble_ib
;
278 struct r600_resource
*ce_ram_saved_buffer
;
279 struct u_suballocator
*ce_suballocator
;
280 unsigned ce_ram_saved_offset
;
281 uint16_t total_ce_ram_allocated
;
282 bool ce_need_synchronization
:1;
284 bool gfx_flush_in_progress
:1;
285 bool compute_is_busy
:1;
287 /* Atoms (direct states). */
288 union si_state_atoms atoms
;
289 unsigned dirty_atoms
; /* mask */
290 /* PM4 states (precomputed immutable states) */
291 unsigned dirty_states
;
292 union si_state queued
;
293 union si_state emitted
;
295 /* Atom declarations. */
296 struct r600_atom prefetch_L2
;
297 struct si_framebuffer framebuffer
;
298 struct si_sample_locs msaa_sample_locs
;
299 struct r600_atom db_render_state
;
300 struct r600_atom msaa_config
;
301 struct si_sample_mask sample_mask
;
302 struct r600_atom cb_render_state
;
303 unsigned last_cb_target_mask
;
304 struct si_blend_color blend_color
;
305 struct r600_atom clip_regs
;
306 struct si_clip_state clip_state
;
307 struct si_shader_data shader_userdata
;
308 struct si_stencil_ref stencil_ref
;
309 struct r600_atom spi_map
;
311 /* Precomputed states. */
312 struct si_pm4_state
*init_config
;
313 struct si_pm4_state
*init_config_gs_rings
;
314 bool init_config_has_vgt_flush
;
315 struct si_pm4_state
*vgt_shader_config
[4];
318 struct si_shader_ctx_state ps_shader
;
319 struct si_shader_ctx_state gs_shader
;
320 struct si_shader_ctx_state vs_shader
;
321 struct si_shader_ctx_state tcs_shader
;
322 struct si_shader_ctx_state tes_shader
;
323 struct si_cs_shader_state cs_shader_state
;
325 /* shader information */
326 struct si_vertex_elements
*vertex_elements
;
327 unsigned sprite_coord_enable
;
329 bool do_update_shaders
;
331 /* shader descriptors */
332 struct si_descriptors vertex_buffers
;
333 struct si_descriptors descriptors
[SI_NUM_DESCS
];
334 unsigned descriptors_dirty
;
335 unsigned shader_pointers_dirty
;
336 unsigned shader_needs_decompress_mask
;
337 struct si_buffer_resources rw_buffers
;
338 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
339 struct si_textures_info samplers
[SI_NUM_SHADERS
];
340 struct si_images_info images
[SI_NUM_SHADERS
];
342 /* other shader resources */
343 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
344 struct pipe_resource
*esgs_ring
;
345 struct pipe_resource
*gsvs_ring
;
346 struct pipe_resource
*tf_ring
;
347 struct pipe_resource
*tess_offchip_ring
;
348 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
349 struct r600_resource
*border_color_buffer
;
350 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
351 unsigned border_color_count
;
353 /* Vertex and index buffers. */
354 bool vertex_buffers_dirty
;
355 bool vertex_buffer_pointer_dirty
;
356 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
358 /* MSAA config state. */
360 bool smoothing_enabled
;
362 /* DB render state. */
363 unsigned ps_db_shader_control
;
364 unsigned dbcb_copy_sample
;
365 bool dbcb_depth_copy_enabled
:1;
366 bool dbcb_stencil_copy_enabled
:1;
367 bool db_flush_depth_inplace
:1;
368 bool db_flush_stencil_inplace
:1;
369 bool db_depth_clear
:1;
370 bool db_depth_disable_expclear
:1;
371 bool db_stencil_clear
:1;
372 bool db_stencil_disable_expclear
:1;
373 bool occlusion_queries_disabled
:1;
374 bool generate_mipmap_for_depth
:1;
376 /* Emitted draw state. */
377 bool gs_tri_strip_adj_fix
:1;
379 int last_base_vertex
;
380 int last_start_instance
;
382 int last_sh_base_reg
;
383 int last_primitive_restart_en
;
384 int last_restart_index
;
385 int last_gs_out_prim
;
387 int last_multi_vgt_param
;
389 unsigned last_sc_line_stipple
;
390 unsigned current_vs_state
;
391 unsigned last_vs_state
;
392 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
395 struct r600_atom scratch_state
;
396 struct r600_resource
*scratch_buffer
;
397 unsigned scratch_waves
;
398 unsigned spi_tmpring_size
;
400 struct r600_resource
*compute_scratch_buffer
;
402 /* Emitted derived tessellation state. */
403 /* Local shader (VS), or HS if LS-HS are merged. */
404 struct si_shader
*last_ls
;
405 struct si_shader_selector
*last_tcs
;
406 int last_num_tcs_input_cp
;
407 int last_tes_sh_base
;
408 bool last_tess_uses_primid
;
409 unsigned last_num_patches
;
413 struct radeon_saved_cs last_gfx
;
414 struct radeon_saved_cs last_ce
;
415 struct r600_resource
*last_trace_buf
;
416 struct r600_resource
*trace_buf
;
418 uint64_t dmesg_timestamp
;
419 unsigned apitrace_call_number
;
422 bool need_check_render_feedback
;
423 bool decompression_enabled
;
425 /* Precomputed IA_MULTI_VGT_PARAM */
426 union si_vgt_param_key ia_multi_vgt_param_key
;
427 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
429 /* Slab allocator for bindless descriptors. */
430 struct pb_slabs bindless_descriptor_slabs
;
432 /* Bindless descriptors. */
433 struct util_dynarray bindless_descriptors
;
434 bool bindless_descriptors_dirty
;
436 /* Allocated bindless handles */
437 struct hash_table
*tex_handles
;
438 struct hash_table
*img_handles
;
440 /* Resident bindless handles */
441 struct util_dynarray resident_tex_handles
;
442 struct util_dynarray resident_img_handles
;
444 /* Resident bindless handles which need decompression */
445 struct util_dynarray resident_tex_needs_color_decompress
;
446 struct util_dynarray resident_img_needs_color_decompress
;
447 struct util_dynarray resident_tex_needs_depth_decompress
;
450 bool uses_bindless_samplers
;
451 bool uses_bindless_images
;
455 void cik_init_sdma_functions(struct si_context
*sctx
);
458 void si_init_blit_functions(struct si_context
*sctx
);
459 void si_decompress_graphics_textures(struct si_context
*sctx
);
460 void si_decompress_compute_textures(struct si_context
*sctx
);
461 void si_resource_copy_region(struct pipe_context
*ctx
,
462 struct pipe_resource
*dst
,
464 unsigned dstx
, unsigned dsty
, unsigned dstz
,
465 struct pipe_resource
*src
,
467 const struct pipe_box
*src_box
);
470 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
471 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
472 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
473 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
474 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
475 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
476 SI_CPDMA_SKIP_SYNC_AFTER | \
477 SI_CPDMA_SKIP_SYNC_BEFORE | \
478 SI_CPDMA_SKIP_GFX_SYNC | \
479 SI_CPDMA_SKIP_BO_LIST_UPDATE)
481 void si_copy_buffer(struct si_context
*sctx
,
482 struct pipe_resource
*dst
, struct pipe_resource
*src
,
483 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
484 unsigned user_flags
);
485 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
486 uint64_t offset
, unsigned size
);
487 void si_init_cp_dma_functions(struct si_context
*sctx
);
490 void si_init_debug_functions(struct si_context
*sctx
);
491 void si_check_vm_faults(struct r600_common_context
*ctx
,
492 struct radeon_saved_cs
*saved
, enum ring_type ring
);
493 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
496 void si_init_dma_functions(struct si_context
*sctx
);
498 /* si_hw_context.c */
499 void si_context_gfx_flush(void *context
, unsigned flags
,
500 struct pipe_fence_handle
**fence
);
501 void si_begin_new_cs(struct si_context
*ctx
);
502 void si_need_cs_space(struct si_context
*ctx
);
505 void si_init_compute_functions(struct si_context
*sctx
);
507 /* si_perfcounters.c */
508 void si_init_perfcounters(struct si_screen
*screen
);
511 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
512 const struct pipe_video_codec
*templ
);
514 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
515 const struct pipe_video_buffer
*tmpl
);
522 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
524 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
528 si_set_atom_dirty(struct si_context
*sctx
,
529 struct r600_atom
*atom
, bool dirty
)
531 unsigned bit
= 1 << atom
->id
;
534 sctx
->dirty_atoms
|= bit
;
536 sctx
->dirty_atoms
&= ~bit
;
540 si_is_atom_dirty(struct si_context
*sctx
,
541 struct r600_atom
*atom
)
543 unsigned bit
= 1 << atom
->id
;
545 return sctx
->dirty_atoms
& bit
;
549 si_mark_atom_dirty(struct si_context
*sctx
,
550 struct r600_atom
*atom
)
552 si_set_atom_dirty(sctx
, atom
, true);
555 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
557 if (sctx
->gs_shader
.cso
)
558 return &sctx
->gs_shader
;
559 if (sctx
->tes_shader
.cso
)
560 return &sctx
->tes_shader
;
562 return &sctx
->vs_shader
;
565 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
567 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
569 return vs
->cso
? &vs
->cso
->info
: NULL
;
572 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
574 if (sctx
->gs_shader
.cso
)
575 return sctx
->gs_shader
.cso
->gs_copy_shader
;
577 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
578 return vs
->current
? vs
->current
: NULL
;
581 static inline unsigned
582 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
584 unsigned alignment
, tcc_cache_line_size
;
586 /* If the upload size is less than the cache line size (e.g. 16, 32),
587 * the whole thing will fit into a cache line if we align it to its size.
588 * The idea is that multiple small uploads can share a cache line.
589 * If the upload size is greater, align it to the cache line size.
591 alignment
= util_next_power_of_two(upload_size
);
592 tcc_cache_line_size
= sctx
->screen
->b
.info
.tcc_cache_line_size
;
593 return MIN2(alignment
, tcc_cache_line_size
);