2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_MAX_POINT_SIZE 2048
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
56 /* Tunables for compute-based clear_buffer and copy_buffer: */
57 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
58 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
59 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61 /* Pipeline & streamout query controls. */
62 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
63 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
64 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
65 /* Instruction cache. */
66 #define SI_CONTEXT_INV_ICACHE (1 << 3)
67 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
68 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
69 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
70 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
71 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
72 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
73 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
74 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
75 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
76 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
77 * a CB or DB flush. */
78 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
79 /* Framebuffer caches. */
80 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
81 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
82 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
83 /* Engine synchronization. */
84 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
85 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
86 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
87 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
88 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
90 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
91 #define SI_PREFETCH_LS (1 << 1)
92 #define SI_PREFETCH_HS (1 << 2)
93 #define SI_PREFETCH_ES (1 << 3)
94 #define SI_PREFETCH_GS (1 << 4)
95 #define SI_PREFETCH_VS (1 << 5)
96 #define SI_PREFETCH_PS (1 << 6)
98 #define SI_MAX_BORDER_COLORS 4096
99 #define SI_MAX_VIEWPORTS 16
100 #define SIX_BITS 0x3F
101 #define SI_MAP_BUFFER_ALIGNMENT 64
102 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
104 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
105 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
106 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
107 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
108 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
109 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
110 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
111 #define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
115 /* Shader logging options: */
116 DBG_VS
= PIPE_SHADER_VERTEX
,
117 DBG_PS
= PIPE_SHADER_FRAGMENT
,
118 DBG_GS
= PIPE_SHADER_GEOMETRY
,
119 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
120 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
121 DBG_CS
= PIPE_SHADER_COMPUTE
,
127 /* Shader compiler options the shader cache should be aware of: */
128 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
133 /* Shader compiler options (with no effect on the shader cache): */
136 DBG_MONOLITHIC_SHADERS
,
139 /* Information logging options: */
145 /* Driver options: */
153 /* 3D engine options: */
173 DBG_TEST_VMFAULT_SDMA
,
174 DBG_TEST_VMFAULT_SHADER
,
181 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
182 #define DBG(name) (1ull << DBG_##name)
184 enum si_cache_policy
{
186 L2_STREAM
, /* same as SLC=1 */
187 L2_LRU
, /* same as SLC=0 */
191 SI_COHERENCY_NONE
, /* no cache flushes needed */
193 SI_COHERENCY_CB_META
,
199 struct u_suballocator
;
201 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
204 struct r600_resource
{
205 struct threaded_resource b
;
207 /* Winsys objects. */
208 struct pb_buffer
*buf
;
209 uint64_t gpu_address
;
210 /* Memory usage if the buffer placement is optimal. */
214 /* Resource properties. */
216 unsigned bo_alignment
;
217 enum radeon_bo_domain domains
;
218 enum radeon_bo_flag flags
;
219 unsigned bind_history
;
220 int max_forced_staging_uploads
;
222 /* The buffer range which is initialized (with a write transfer,
223 * streamout, DMA, or as a random access target). The rest of
224 * the buffer is considered invalid and can be mapped unsynchronized.
226 * This allows unsychronized mapping of a buffer range which hasn't
227 * been used yet. It's for applications which forget to use
228 * the unsynchronized map flag and expect the driver to figure it out.
230 struct util_range valid_buffer_range
;
232 /* For buffers only. This indicates that a write operation has been
233 * performed by TC L2, but the cache hasn't been flushed.
234 * Any hw block which doesn't use or bypasses TC L2 should check this
235 * flag and flush the cache before using the buffer.
237 * For example, TC L2 must be flushed if a buffer which has been
238 * modified by a shader store instruction is about to be used as
239 * an index buffer. The reason is that VGT DMA index fetching doesn't
244 /* Whether this resource is referenced by bindless handles. */
245 bool texture_handle_allocated
;
246 bool image_handle_allocated
;
248 /* Whether the resource has been exported via resource_get_handle. */
249 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
253 struct threaded_transfer b
;
254 struct r600_resource
*staging
;
259 struct r600_resource buffer
;
261 struct radeon_surf surface
;
263 struct si_texture
*flushed_depth_texture
;
265 /* Colorbuffer compression and fast clear. */
266 uint64_t fmask_offset
;
267 uint64_t cmask_offset
;
268 uint64_t cmask_base_address_reg
;
269 struct r600_resource
*cmask_buffer
;
270 uint64_t dcc_offset
; /* 0 = disabled */
271 unsigned cb_color_info
; /* fast clear enable bit */
272 unsigned color_clear_value
[2];
273 unsigned last_msaa_resolve_target_micro_mode
;
274 unsigned num_level0_transfers
;
276 /* Depth buffer compression and fast clear. */
277 uint64_t htile_offset
;
278 float depth_clear_value
;
279 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
280 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
281 enum pipe_format db_render_format
:16;
282 uint8_t stencil_clear_value
;
283 bool tc_compatible_htile
:1;
284 bool depth_cleared
:1; /* if it was cleared at least once */
285 bool stencil_cleared
:1; /* if it was cleared at least once */
286 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
288 bool db_compatible
:1;
292 /* We need to track DCC dirtiness, because st/dri usually calls
293 * flush_resource twice per frame (not a bug) and we don't wanna
294 * decompress DCC twice. Also, the dirty tracking must be done even
295 * if DCC isn't used, because it's required by the DCC usage analysis
296 * for a possible future enablement.
298 bool separate_dcc_dirty
:1;
299 /* Statistics gathering for the DCC enablement heuristic. */
300 bool dcc_gather_statistics
:1;
301 /* Counter that should be non-zero if the texture is bound to a
304 unsigned framebuffers_bound
;
305 /* Whether the texture is a displayable back buffer and needs DCC
306 * decompression, which is expensive. Therefore, it's enabled only
307 * if statistics suggest that it will pay off and it's allocated
308 * separately. It can't be bound as a sampler by apps. Limited to
309 * target == 2D and last_level == 0. If enabled, dcc_offset contains
310 * the absolute GPUVM address, not the relative one.
312 struct r600_resource
*dcc_separate_buffer
;
313 /* When DCC is temporarily disabled, the separate buffer is here. */
314 struct r600_resource
*last_dcc_separate_buffer
;
315 /* Estimate of how much this color buffer is written to in units of
316 * full-screen draws: ps_invocations / (width * height)
317 * Shader kills, late Z, and blending with trivial discards make it
318 * inaccurate (we need to count CB updates, not PS invocations).
320 unsigned ps_draw_ratio
;
321 /* The number of clears since the last DCC usage analysis. */
322 unsigned num_slow_clears
;
326 struct pipe_surface base
;
328 /* These can vary with block-compressed textures. */
332 bool color_initialized
:1;
333 bool depth_initialized
:1;
335 /* Misc. color flags. */
336 bool color_is_int8
:1;
337 bool color_is_int10
:1;
338 bool dcc_incompatible
:1;
340 /* Color registers. */
341 unsigned cb_color_info
;
342 unsigned cb_color_view
;
343 unsigned cb_color_attrib
;
344 unsigned cb_color_attrib2
; /* GFX9 and later */
345 unsigned cb_dcc_control
; /* VI and later */
346 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
347 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
348 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
349 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
352 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
353 uint64_t db_stencil_base
;
354 uint64_t db_htile_data_base
;
355 unsigned db_depth_info
;
357 unsigned db_z_info2
; /* GFX9+ */
358 unsigned db_depth_view
;
359 unsigned db_depth_size
;
360 unsigned db_depth_slice
;
361 unsigned db_stencil_info
;
362 unsigned db_stencil_info2
; /* GFX9+ */
363 unsigned db_htile_surface
;
366 struct si_mmio_counter
{
371 union si_mmio_counters
{
373 /* For global GPU load including SDMA. */
374 struct si_mmio_counter gpu
;
377 struct si_mmio_counter spi
;
378 struct si_mmio_counter gui
;
379 struct si_mmio_counter ta
;
380 struct si_mmio_counter gds
;
381 struct si_mmio_counter vgt
;
382 struct si_mmio_counter ia
;
383 struct si_mmio_counter sx
;
384 struct si_mmio_counter wd
;
385 struct si_mmio_counter bci
;
386 struct si_mmio_counter sc
;
387 struct si_mmio_counter pa
;
388 struct si_mmio_counter db
;
389 struct si_mmio_counter cp
;
390 struct si_mmio_counter cb
;
393 struct si_mmio_counter sdma
;
396 struct si_mmio_counter pfp
;
397 struct si_mmio_counter meq
;
398 struct si_mmio_counter me
;
399 struct si_mmio_counter surf_sync
;
400 struct si_mmio_counter cp_dma
;
401 struct si_mmio_counter scratch_ram
;
406 struct si_memory_object
{
407 struct pipe_memory_object b
;
408 struct pb_buffer
*buf
;
412 /* Saved CS data for debugging features. */
413 struct radeon_saved_cs
{
417 struct radeon_bo_list_item
*bo_list
;
422 struct pipe_screen b
;
423 struct radeon_winsys
*ws
;
424 struct disk_cache
*disk_shader_cache
;
426 struct radeon_info info
;
427 uint64_t debug_flags
;
428 char renderer_string
[183];
430 unsigned pa_sc_raster_config
;
431 unsigned pa_sc_raster_config_1
;
432 unsigned se_tile_repeat
;
433 unsigned gs_table_depth
;
434 unsigned tess_offchip_block_dw_size
;
435 unsigned tess_offchip_ring_size
;
436 unsigned tess_factor_ring_size
;
437 unsigned vgt_hs_offchip_param
;
438 unsigned eqaa_force_coverage_samples
;
439 unsigned eqaa_force_z_samples
;
440 unsigned eqaa_force_color_samples
;
441 bool has_clear_state
;
442 bool has_distributed_tess
;
443 bool has_draw_indirect_multi
;
444 bool has_out_of_order_rast
;
445 bool assume_no_z_fights
;
446 bool commutative_blend_add
;
447 bool clear_db_cache_before_clear
;
448 bool has_msaa_sample_loc_bug
;
449 bool has_ls_vgpr_init_bug
;
450 bool has_dcc_constant_encode
;
453 bool llvm_has_working_vgpr_indexing
;
455 /* Whether shaders are monolithic (1-part) or separate (3-part). */
456 bool use_monolithic_shaders
;
458 bool has_rbplus
; /* if RB+ registers exist */
459 bool rbplus_allowed
; /* if RB+ is allowed */
460 bool dcc_msaa_allowed
;
461 bool cpdma_prefetch_writes_memory
;
463 struct slab_parent_pool pool_transfers
;
465 /* Texture filter settings. */
466 int force_aniso
; /* -1 = disabled */
468 /* Auxiliary context. Mainly used to initialize resources.
469 * It must be locked prior to using and flushed before unlocking. */
470 struct pipe_context
*aux_context
;
471 mtx_t aux_context_lock
;
473 /* This must be in the screen, because UE4 uses one context for
474 * compilation and another one for rendering.
476 unsigned num_compilations
;
477 /* Along with ST_DEBUG=precompile, this should show if applications
478 * are loading shaders on demand. This is a monotonic counter.
480 unsigned num_shaders_created
;
481 unsigned num_shader_cache_hits
;
483 /* GPU load thread. */
484 mtx_t gpu_load_mutex
;
485 thrd_t gpu_load_thread
;
486 union si_mmio_counters mmio_counters
;
487 volatile unsigned gpu_load_stop_thread
; /* bool */
489 /* Performance counters. */
490 struct si_perfcounters
*perfcounters
;
492 /* If pipe_screen wants to recompute and re-emit the framebuffer,
493 * sampler, and image states of all contexts, it should atomically
496 * Each context will compare this with its own last known value of
497 * the counter before drawing and re-emit the states accordingly.
499 unsigned dirty_tex_counter
;
501 /* Atomically increment this counter when an existing texture's
502 * metadata is enabled or disabled in a way that requires changing
503 * contexts' compressed texture binding masks.
505 unsigned compressed_colortex_counter
;
508 /* Context flags to set so that all writes from earlier jobs
509 * in the CP are seen by L2 clients.
513 /* Context flags to set so that all writes from earlier jobs
514 * that end in L2 are seen by CP.
519 mtx_t shader_parts_mutex
;
520 struct si_shader_part
*vs_prologs
;
521 struct si_shader_part
*tcs_epilogs
;
522 struct si_shader_part
*gs_prologs
;
523 struct si_shader_part
*ps_prologs
;
524 struct si_shader_part
*ps_epilogs
;
526 /* Shader cache in memory.
528 * Design & limitations:
529 * - The shader cache is per screen (= per process), never saved to
530 * disk, and skips redundant shader compilations from TGSI to bytecode.
531 * - It can only be used with one-variant-per-shader support, in which
532 * case only the main (typically middle) part of shaders is cached.
533 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
534 * variants of VS and TES are cached, so LS and ES aren't.
535 * - GS and CS aren't cached, but it's certainly possible to cache
538 mtx_t shader_cache_mutex
;
539 struct hash_table
*shader_cache
;
541 /* Shader compiler queue for multithreaded compilation. */
542 struct util_queue shader_compiler_queue
;
543 /* Use at most 3 normal compiler threads on quadcore and better.
544 * Hyperthreaded CPUs report the number of threads, but we want
545 * the number of cores. We only need this many threads for shader-db. */
546 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
548 struct util_queue shader_compiler_queue_low_priority
;
549 /* Use at most 2 low priority threads on quadcore and better.
550 * We want to minimize the impact on multithreaded Mesa. */
551 struct ac_llvm_compiler compiler_lowp
[10];
554 struct si_blend_color
{
555 struct pipe_blend_color state
;
559 struct si_sampler_view
{
560 struct pipe_sampler_view base
;
561 /* [0..7] = image descriptor
562 * [4..7] = buffer descriptor */
564 uint32_t fmask_state
[8];
565 const struct legacy_surf_level
*base_level_info
;
568 bool is_stencil_sampler
;
570 bool dcc_incompatible
;
573 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
575 struct si_sampler_state
{
580 uint32_t integer_val
[4];
581 uint32_t upgraded_depth_val
[4];
584 struct si_cs_shader_state
{
585 struct si_compute
*program
;
586 struct si_compute
*emitted_program
;
593 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
594 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
596 /* The i-th bit is set if that element is enabled (non-NULL resource). */
597 unsigned enabled_mask
;
598 uint32_t needs_depth_decompress_mask
;
599 uint32_t needs_color_decompress_mask
;
603 struct pipe_image_view views
[SI_NUM_IMAGES
];
604 uint32_t needs_color_decompress_mask
;
605 unsigned enabled_mask
;
608 struct si_framebuffer
{
609 struct pipe_framebuffer_state state
;
610 unsigned colorbuf_enabled_4bit
;
611 unsigned spi_shader_col_format
;
612 unsigned spi_shader_col_format_alpha
;
613 unsigned spi_shader_col_format_blend
;
614 unsigned spi_shader_col_format_blend_alpha
;
615 ubyte nr_samples
:5; /* at most 16xAA */
616 ubyte log_samples
:3; /* at most 4 = 16xAA */
617 ubyte nr_color_samples
; /* at most 8xAA */
618 ubyte compressed_cb_mask
;
619 ubyte uncompressed_cb_mask
;
621 ubyte color_is_int10
;
623 ubyte dcc_overwrite_combiner_watermark
;
626 bool CB_has_shader_readable_metadata
;
627 bool DB_has_shader_readable_metadata
;
631 /* This is the list we want to support. */
632 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
633 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
634 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
637 struct si_signed_scissor
{
642 enum si_quant_mode quant_mode
;
647 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
650 struct si_viewports
{
652 unsigned depth_range_dirty_mask
;
653 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
654 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
657 struct si_clip_state
{
658 struct pipe_clip_state state
;
662 struct si_streamout_target
{
663 struct pipe_stream_output_target b
;
665 /* The buffer where BUFFER_FILLED_SIZE is stored. */
666 struct r600_resource
*buf_filled_size
;
667 unsigned buf_filled_size_offset
;
668 bool buf_filled_size_valid
;
670 unsigned stride_in_dw
;
673 struct si_streamout
{
676 unsigned enabled_mask
;
677 unsigned num_targets
;
678 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
680 unsigned append_bitmask
;
683 /* External state which comes from the vertex shader,
684 * it must be set explicitly when binding a shader. */
685 uint16_t *stride_in_dw
;
686 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
688 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
689 unsigned hw_enabled_mask
;
691 /* The state of VGT_STRMOUT_(CONFIG|EN). */
692 bool streamout_enabled
;
693 bool prims_gen_query_enabled
;
694 int num_prims_gen_queries
;
697 /* A shader state consists of the shader selector, which is a constant state
698 * object shared by multiple contexts and shouldn't be modified, and
699 * the current shader variant selected for this context.
701 struct si_shader_ctx_state
{
702 struct si_shader_selector
*cso
;
703 struct si_shader
*current
;
706 #define SI_NUM_VGT_PARAM_KEY_BITS 12
707 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
709 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
710 * Some fields are set by state-change calls, most are set by draw_vbo.
712 union si_vgt_param_key
{
714 #ifdef PIPE_ARCH_LITTLE_ENDIAN
716 unsigned uses_instancing
:1;
717 unsigned multi_instances_smaller_than_primgroup
:1;
718 unsigned primitive_restart
:1;
719 unsigned count_from_stream_output
:1;
720 unsigned line_stipple_enabled
:1;
721 unsigned uses_tess
:1;
722 unsigned tess_uses_prim_id
:1;
724 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
725 #else /* PIPE_ARCH_BIG_ENDIAN */
726 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
728 unsigned tess_uses_prim_id
:1;
729 unsigned uses_tess
:1;
730 unsigned line_stipple_enabled
:1;
731 unsigned count_from_stream_output
:1;
732 unsigned primitive_restart
:1;
733 unsigned multi_instances_smaller_than_primgroup
:1;
734 unsigned uses_instancing
:1;
741 struct si_texture_handle
745 struct pipe_sampler_view
*view
;
746 struct si_sampler_state sstate
;
749 struct si_image_handle
753 struct pipe_image_view view
;
757 struct pipe_reference reference
;
758 struct si_context
*ctx
;
759 struct radeon_saved_cs gfx
;
760 struct r600_resource
*trace_buf
;
763 unsigned gfx_last_dw
;
769 struct pipe_context b
; /* base class */
771 enum radeon_family family
;
772 enum chip_class chip_class
;
774 struct radeon_winsys
*ws
;
775 struct radeon_winsys_ctx
*ctx
;
776 struct radeon_cmdbuf
*gfx_cs
;
777 struct radeon_cmdbuf
*dma_cs
;
778 struct pipe_fence_handle
*last_gfx_fence
;
779 struct pipe_fence_handle
*last_sdma_fence
;
780 struct r600_resource
*eop_bug_scratch
;
781 struct u_upload_mgr
*cached_gtt_allocator
;
782 struct threaded_context
*tc
;
783 struct u_suballocator
*allocator_zeroed_memory
;
784 struct slab_child_pool pool_transfers
;
785 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
786 struct pipe_device_reset_callback device_reset_callback
;
787 struct u_log_context
*log
;
788 void *query_result_shader
;
789 struct blitter_context
*blitter
;
790 void *custom_dsa_flush
;
791 void *custom_blend_resolve
;
792 void *custom_blend_fmask_decompress
;
793 void *custom_blend_eliminate_fastclear
;
794 void *custom_blend_dcc_decompress
;
796 void *vs_blit_pos_layered
;
798 void *vs_blit_color_layered
;
799 void *vs_blit_texcoord
;
800 void *cs_clear_buffer
;
801 void *cs_copy_buffer
;
802 struct si_screen
*screen
;
803 struct pipe_debug_callback debug
;
804 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
805 struct si_shader_ctx_state fixed_func_tcs_shader
;
806 struct r600_resource
*wait_mem_scratch
;
807 unsigned wait_mem_number
;
808 uint16_t prefetch_L2_mask
;
810 bool gfx_flush_in_progress
:1;
811 bool gfx_last_ib_is_busy
:1;
812 bool compute_is_busy
:1;
814 unsigned num_gfx_cs_flushes
;
815 unsigned initial_gfx_cs_size
;
816 unsigned gpu_reset_counter
;
817 unsigned last_dirty_tex_counter
;
818 unsigned last_compressed_colortex_counter
;
819 unsigned last_num_draw_calls
;
820 unsigned flags
; /* flush flags */
821 /* Current unaccounted memory usage. */
825 /* Atoms (direct states). */
826 union si_state_atoms atoms
;
827 unsigned dirty_atoms
; /* mask */
828 /* PM4 states (precomputed immutable states) */
829 unsigned dirty_states
;
830 union si_state queued
;
831 union si_state emitted
;
833 /* Atom declarations. */
834 struct si_framebuffer framebuffer
;
835 unsigned sample_locs_num_samples
;
836 uint16_t sample_mask
;
837 unsigned last_cb_target_mask
;
838 struct si_blend_color blend_color
;
839 struct si_clip_state clip_state
;
840 struct si_shader_data shader_pointers
;
841 struct si_stencil_ref stencil_ref
;
842 struct si_scissors scissors
;
843 struct si_streamout streamout
;
844 struct si_viewports viewports
;
845 unsigned num_window_rectangles
;
846 bool window_rectangles_include
;
847 struct pipe_scissor_state window_rectangles
[4];
849 /* Precomputed states. */
850 struct si_pm4_state
*init_config
;
851 struct si_pm4_state
*init_config_gs_rings
;
852 bool init_config_has_vgt_flush
;
853 struct si_pm4_state
*vgt_shader_config
[4];
856 struct si_shader_ctx_state ps_shader
;
857 struct si_shader_ctx_state gs_shader
;
858 struct si_shader_ctx_state vs_shader
;
859 struct si_shader_ctx_state tcs_shader
;
860 struct si_shader_ctx_state tes_shader
;
861 struct si_cs_shader_state cs_shader_state
;
863 /* shader information */
864 struct si_vertex_elements
*vertex_elements
;
865 unsigned sprite_coord_enable
;
866 unsigned cs_max_waves_per_sh
;
868 bool do_update_shaders
;
870 /* vertex buffer descriptors */
871 uint32_t *vb_descriptors_gpu_list
;
872 struct r600_resource
*vb_descriptors_buffer
;
873 unsigned vb_descriptors_offset
;
875 /* shader descriptors */
876 struct si_descriptors descriptors
[SI_NUM_DESCS
];
877 unsigned descriptors_dirty
;
878 unsigned shader_pointers_dirty
;
879 unsigned shader_needs_decompress_mask
;
880 struct si_buffer_resources rw_buffers
;
881 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
882 struct si_samplers samplers
[SI_NUM_SHADERS
];
883 struct si_images images
[SI_NUM_SHADERS
];
885 /* other shader resources */
886 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
887 struct pipe_resource
*esgs_ring
;
888 struct pipe_resource
*gsvs_ring
;
889 struct pipe_resource
*tess_rings
;
890 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
891 struct r600_resource
*border_color_buffer
;
892 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
893 unsigned border_color_count
;
894 unsigned num_vs_blit_sgprs
;
895 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
896 uint32_t cs_user_data
[4];
898 /* Vertex and index buffers. */
899 bool vertex_buffers_dirty
;
900 bool vertex_buffer_pointer_dirty
;
901 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
903 /* MSAA config state. */
905 bool ps_uses_fbfetch
;
906 bool smoothing_enabled
;
908 /* DB render state. */
909 unsigned ps_db_shader_control
;
910 unsigned dbcb_copy_sample
;
911 bool dbcb_depth_copy_enabled
:1;
912 bool dbcb_stencil_copy_enabled
:1;
913 bool db_flush_depth_inplace
:1;
914 bool db_flush_stencil_inplace
:1;
915 bool db_depth_clear
:1;
916 bool db_depth_disable_expclear
:1;
917 bool db_stencil_clear
:1;
918 bool db_stencil_disable_expclear
:1;
919 bool occlusion_queries_disabled
:1;
920 bool generate_mipmap_for_depth
:1;
922 /* Emitted draw state. */
923 bool gs_tri_strip_adj_fix
:1;
926 int last_base_vertex
;
927 int last_start_instance
;
929 int last_sh_base_reg
;
930 int last_primitive_restart_en
;
931 int last_restart_index
;
933 int last_multi_vgt_param
;
935 unsigned last_sc_line_stipple
;
936 unsigned current_vs_state
;
937 unsigned last_vs_state
;
938 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
941 struct r600_resource
*scratch_buffer
;
942 unsigned scratch_waves
;
943 unsigned spi_tmpring_size
;
945 struct r600_resource
*compute_scratch_buffer
;
947 /* Emitted derived tessellation state. */
948 /* Local shader (VS), or HS if LS-HS are merged. */
949 struct si_shader
*last_ls
;
950 struct si_shader_selector
*last_tcs
;
951 int last_num_tcs_input_cp
;
952 int last_tes_sh_base
;
953 bool last_tess_uses_primid
;
954 unsigned last_num_patches
;
955 int last_ls_hs_config
;
959 struct si_saved_cs
*current_saved_cs
;
960 uint64_t dmesg_timestamp
;
961 unsigned apitrace_call_number
;
964 bool need_check_render_feedback
;
965 bool decompression_enabled
;
967 bool vs_writes_viewport_index
;
968 bool vs_disables_clipping_viewport
;
970 /* Precomputed IA_MULTI_VGT_PARAM */
971 union si_vgt_param_key ia_multi_vgt_param_key
;
972 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
974 /* Bindless descriptors. */
975 struct si_descriptors bindless_descriptors
;
976 struct util_idalloc bindless_used_slots
;
977 unsigned num_bindless_descriptors
;
978 bool bindless_descriptors_dirty
;
979 bool graphics_bindless_pointer_dirty
;
980 bool compute_bindless_pointer_dirty
;
982 /* Allocated bindless handles */
983 struct hash_table
*tex_handles
;
984 struct hash_table
*img_handles
;
986 /* Resident bindless handles */
987 struct util_dynarray resident_tex_handles
;
988 struct util_dynarray resident_img_handles
;
990 /* Resident bindless handles which need decompression */
991 struct util_dynarray resident_tex_needs_color_decompress
;
992 struct util_dynarray resident_img_needs_color_decompress
;
993 struct util_dynarray resident_tex_needs_depth_decompress
;
996 bool uses_bindless_samplers
;
997 bool uses_bindless_images
;
999 /* MSAA sample locations.
1000 * The first index is the sample index.
1001 * The second index is the coordinate: X, Y. */
1009 struct pipe_resource
*sample_pos_buffer
;
1012 unsigned num_draw_calls
;
1013 unsigned num_decompress_calls
;
1014 unsigned num_mrt_draw_calls
;
1015 unsigned num_prim_restart_calls
;
1016 unsigned num_spill_draw_calls
;
1017 unsigned num_compute_calls
;
1018 unsigned num_spill_compute_calls
;
1019 unsigned num_dma_calls
;
1020 unsigned num_cp_dma_calls
;
1021 unsigned num_vs_flushes
;
1022 unsigned num_ps_flushes
;
1023 unsigned num_cs_flushes
;
1024 unsigned num_cb_cache_flushes
;
1025 unsigned num_db_cache_flushes
;
1026 unsigned num_L2_invalidates
;
1027 unsigned num_L2_writebacks
;
1028 unsigned num_resident_handles
;
1029 uint64_t num_alloc_tex_transfer_bytes
;
1030 unsigned last_tex_ps_draw_ratio
; /* for query */
1031 unsigned context_roll_counter
;
1034 /* Maintain the list of active queries for pausing between IBs. */
1035 int num_occlusion_queries
;
1036 int num_perfect_occlusion_queries
;
1037 struct list_head active_queries
;
1038 unsigned num_cs_dw_queries_suspend
;
1040 /* Render condition. */
1041 struct pipe_query
*render_cond
;
1042 unsigned render_cond_mode
;
1043 bool render_cond_invert
;
1044 bool render_cond_force_off
; /* for u_blitter */
1046 /* Statistics gathering for the DCC enablement heuristic. It can't be
1047 * in si_texture because si_texture can be shared by multiple
1048 * contexts. This is for back buffers only. We shouldn't get too many
1051 * X11 DRI3 rotates among a finite set of back buffers. They should
1052 * all fit in this array. If they don't, separate DCC might never be
1053 * enabled by DCC stat gathering.
1056 struct si_texture
*tex
;
1057 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1058 struct pipe_query
*ps_stats
[3];
1059 /* If all slots are used and another slot is needed,
1060 * the least recently used slot is evicted based on this. */
1061 int64_t last_use_timestamp
;
1065 /* Copy one resource to another using async DMA. */
1066 void (*dma_copy
)(struct pipe_context
*ctx
,
1067 struct pipe_resource
*dst
,
1069 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1070 struct pipe_resource
*src
,
1072 const struct pipe_box
*src_box
);
1074 struct si_tracked_regs tracked_regs
;
1078 void cik_init_sdma_functions(struct si_context
*sctx
);
1081 enum si_blitter_op
/* bitmask */
1083 SI_SAVE_TEXTURES
= 1,
1084 SI_SAVE_FRAMEBUFFER
= 2,
1085 SI_SAVE_FRAGMENT_STATE
= 4,
1086 SI_DISABLE_RENDER_COND
= 8,
1089 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1090 void si_blitter_end(struct si_context
*sctx
);
1091 void si_init_blit_functions(struct si_context
*sctx
);
1092 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1093 void si_resource_copy_region(struct pipe_context
*ctx
,
1094 struct pipe_resource
*dst
,
1096 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1097 struct pipe_resource
*src
,
1099 const struct pipe_box
*src_box
);
1100 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1101 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1102 struct si_texture
*texture
,
1103 struct si_texture
*staging
,
1104 unsigned first_level
, unsigned last_level
,
1105 unsigned first_layer
, unsigned last_layer
,
1106 unsigned first_sample
, unsigned last_sample
);
1109 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1110 struct pb_buffer
*buf
,
1111 enum radeon_bo_usage usage
);
1112 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1113 struct r600_resource
*resource
,
1115 void si_init_resource_fields(struct si_screen
*sscreen
,
1116 struct r600_resource
*res
,
1117 uint64_t size
, unsigned alignment
);
1118 bool si_alloc_resource(struct si_screen
*sscreen
,
1119 struct r600_resource
*res
);
1120 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1121 unsigned flags
, unsigned usage
,
1122 unsigned size
, unsigned alignment
);
1123 struct r600_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1124 unsigned flags
, unsigned usage
,
1125 unsigned size
, unsigned alignment
);
1126 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1127 struct pipe_resource
*dst
,
1128 struct pipe_resource
*src
);
1129 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1130 void si_init_buffer_functions(struct si_context
*sctx
);
1133 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1134 bool vi_alpha_is_on_msb(enum pipe_format format
);
1135 void vi_dcc_clear_level(struct si_context
*sctx
,
1136 struct si_texture
*tex
,
1137 unsigned level
, unsigned clear_value
);
1138 void si_init_clear_functions(struct si_context
*sctx
);
1140 /* si_compute_blit.c */
1141 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1142 enum si_cache_policy cache_policy
);
1143 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1144 uint64_t offset
, uint64_t size
, uint32_t *clear_value
,
1145 uint32_t clear_value_size
, enum si_coherency coher
);
1146 void si_copy_buffer(struct si_context
*sctx
,
1147 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1148 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1149 void si_init_compute_blit_functions(struct si_context
*sctx
);
1152 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1153 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1154 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1155 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1156 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1157 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1158 SI_CPDMA_SKIP_SYNC_AFTER | \
1159 SI_CPDMA_SKIP_SYNC_BEFORE | \
1160 SI_CPDMA_SKIP_GFX_SYNC | \
1161 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1163 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1164 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1165 struct pipe_resource
*dst
, uint64_t offset
,
1166 uint64_t size
, unsigned value
, unsigned user_flags
,
1167 enum si_coherency coher
, enum si_cache_policy cache_policy
);
1168 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1169 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1170 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1171 unsigned user_flags
, enum si_coherency coher
,
1172 enum si_cache_policy cache_policy
);
1173 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1174 uint64_t offset
, unsigned size
);
1175 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1176 void si_test_gds(struct si_context
*sctx
);
1179 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1180 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1181 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1182 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1183 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1184 void si_log_hw_flush(struct si_context
*sctx
);
1185 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1186 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1187 void si_init_debug_functions(struct si_context
*sctx
);
1188 void si_check_vm_faults(struct si_context
*sctx
,
1189 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1190 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1193 void si_init_dma_functions(struct si_context
*sctx
);
1196 void si_dma_emit_timestamp(struct si_context
*sctx
, struct r600_resource
*dst
,
1198 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1199 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1200 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1201 struct r600_resource
*dst
, struct r600_resource
*src
);
1202 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1203 struct pipe_fence_handle
**fence
);
1204 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1205 uint64_t offset
, uint64_t size
, unsigned value
);
1208 void si_cp_release_mem(struct si_context
*ctx
,
1209 unsigned event
, unsigned event_flags
,
1210 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1211 struct r600_resource
*buf
, uint64_t va
,
1212 uint32_t new_fence
, unsigned query_type
);
1213 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1214 void si_cp_wait_mem(struct si_context
*ctx
,
1215 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
);
1216 void si_init_fence_functions(struct si_context
*ctx
);
1217 void si_init_screen_fence_functions(struct si_screen
*screen
);
1218 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1219 struct tc_unflushed_batch_token
*tc_token
);
1222 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1225 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1226 struct pipe_fence_handle
**fence
);
1227 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1228 void si_need_gfx_cs_space(struct si_context
*ctx
);
1230 /* r600_gpu_load.c */
1231 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1232 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1233 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1237 void si_init_compute_functions(struct si_context
*sctx
);
1239 /* r600_perfcounters.c */
1240 void si_perfcounters_destroy(struct si_screen
*sscreen
);
1242 /* si_perfcounters.c */
1243 void si_init_perfcounters(struct si_screen
*screen
);
1246 bool si_check_device_reset(struct si_context
*sctx
);
1249 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1250 void si_init_query_functions(struct si_context
*sctx
);
1251 void si_suspend_queries(struct si_context
*sctx
);
1252 void si_resume_queries(struct si_context
*sctx
);
1254 /* si_shaderlib_tgsi.c */
1255 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1256 unsigned num_layers
);
1257 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1258 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1259 unsigned num_dwords_per_thread
,
1260 bool dst_stream_cache_policy
, bool is_copy
);
1261 void *si_create_query_result_cs(struct si_context
*sctx
);
1264 void si_test_dma(struct si_screen
*sscreen
);
1266 /* si_test_clearbuffer.c */
1267 void si_test_dma_perf(struct si_screen
*sscreen
);
1270 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1271 const struct pipe_video_codec
*templ
);
1273 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1274 const struct pipe_video_buffer
*tmpl
);
1277 void si_update_vs_viewport_state(struct si_context
*ctx
);
1278 void si_init_viewport_functions(struct si_context
*ctx
);
1281 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1282 struct si_texture
*dst
,
1283 unsigned dst_level
, unsigned dstx
,
1284 unsigned dsty
, unsigned dstz
,
1285 struct si_texture
*src
,
1287 const struct pipe_box
*src_box
);
1288 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1289 struct si_texture
*tex
);
1290 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1291 struct si_texture
*tex
);
1292 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1293 struct pipe_resource
*texture
,
1294 struct si_texture
**staging
);
1295 void si_print_texture_info(struct si_screen
*sscreen
,
1296 struct si_texture
*tex
, struct u_log_context
*log
);
1297 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1298 const struct pipe_resource
*templ
);
1299 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1300 enum pipe_format format2
);
1301 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1303 enum pipe_format view_format
);
1304 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1305 struct pipe_resource
*tex
,
1307 enum pipe_format view_format
);
1308 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1309 struct pipe_resource
*texture
,
1310 const struct pipe_surface
*templ
,
1311 unsigned width0
, unsigned height0
,
1312 unsigned width
, unsigned height
);
1313 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1314 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1315 struct si_texture
*tex
);
1316 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1317 struct si_texture
*tex
);
1318 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1319 struct si_texture
*tex
);
1320 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1321 struct si_texture
*tex
);
1322 bool si_texture_disable_dcc(struct si_context
*sctx
,
1323 struct si_texture
*tex
);
1324 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1325 void si_init_context_texture_functions(struct si_context
*sctx
);
1332 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
1334 return (struct r600_resource
*)r
;
1338 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
1340 pipe_resource_reference((struct pipe_resource
**)ptr
,
1341 (struct pipe_resource
*)res
);
1345 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1347 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1351 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1353 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1356 static inline unsigned
1357 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1360 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1362 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1366 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1369 /* Add memory usage for need_gfx_cs_space */
1370 sctx
->vram
+= r600_resource(r
)->vram_usage
;
1371 sctx
->gtt
+= r600_resource(r
)->gart_usage
;
1376 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1378 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1381 static inline unsigned
1382 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1384 return 1 << (atom
- sctx
->atoms
.array
);
1388 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1390 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1393 sctx
->dirty_atoms
|= bit
;
1395 sctx
->dirty_atoms
&= ~bit
;
1399 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1401 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1405 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1407 si_set_atom_dirty(sctx
, atom
, true);
1410 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1412 if (sctx
->gs_shader
.cso
)
1413 return &sctx
->gs_shader
;
1414 if (sctx
->tes_shader
.cso
)
1415 return &sctx
->tes_shader
;
1417 return &sctx
->vs_shader
;
1420 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1422 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1424 return vs
->cso
? &vs
->cso
->info
: NULL
;
1427 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1429 if (sctx
->gs_shader
.cso
)
1430 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1432 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1433 return vs
->current
? vs
->current
: NULL
;
1436 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1439 return sscreen
->debug_flags
& (1 << processor
);
1442 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1444 return sctx
->streamout
.streamout_enabled
||
1445 sctx
->streamout
.prims_gen_query_enabled
;
1448 static inline unsigned
1449 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1451 unsigned alignment
, tcc_cache_line_size
;
1453 /* If the upload size is less than the cache line size (e.g. 16, 32),
1454 * the whole thing will fit into a cache line if we align it to its size.
1455 * The idea is that multiple small uploads can share a cache line.
1456 * If the upload size is greater, align it to the cache line size.
1458 alignment
= util_next_power_of_two(upload_size
);
1459 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1460 return MIN2(alignment
, tcc_cache_line_size
);
1464 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1466 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1467 si_destroy_saved_cs(*dst
);
1473 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1474 bool shaders_read_metadata
)
1476 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1477 SI_CONTEXT_INV_VMEM_L1
;
1479 if (sctx
->chip_class
>= GFX9
) {
1480 /* Single-sample color is coherent with shaders on GFX9, but
1481 * L2 metadata must be flushed if shaders read metadata.
1484 if (num_samples
>= 2)
1485 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1486 else if (shaders_read_metadata
)
1487 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1490 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1495 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1496 bool include_stencil
, bool shaders_read_metadata
)
1498 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1499 SI_CONTEXT_INV_VMEM_L1
;
1501 if (sctx
->chip_class
>= GFX9
) {
1502 /* Single-sample depth (not stencil) is coherent with shaders
1503 * on GFX9, but L2 metadata must be flushed if shaders read
1506 if (num_samples
>= 2 || include_stencil
)
1507 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1508 else if (shaders_read_metadata
)
1509 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1512 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1517 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1519 return (stencil_sampler
&& tex
->can_sample_s
) ||
1520 (!stencil_sampler
&& tex
->can_sample_z
);
1524 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1526 return tex
->htile_offset
&& level
== 0;
1530 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1532 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1533 return tex
->tc_compatible_htile
&& level
== 0;
1536 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1538 if (sctx
->ps_uses_fbfetch
)
1539 return sctx
->framebuffer
.nr_color_samples
;
1541 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1544 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1546 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1549 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1553 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1554 sctx
->queued
.named
.blend
->cb_target_mask
;
1556 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1557 colormask
&= ps
->colors_written_4bit
;
1558 else if (!ps
->colors_written_4bit
)
1559 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1564 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1565 (1 << PIPE_PRIM_LINE_LOOP) | \
1566 (1 << PIPE_PRIM_LINE_STRIP) | \
1567 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1568 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1570 static inline bool util_prim_is_lines(unsigned prim
)
1572 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1575 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1577 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1578 (1 << PIPE_PRIM_POINTS
))) != 0;
1582 * Return true if there is enough memory in VRAM and GTT for the buffers
1585 * \param vram VRAM memory size not added to the buffer list yet
1586 * \param gtt GTT memory size not added to the buffer list yet
1589 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1590 struct radeon_cmdbuf
*cs
,
1591 uint64_t vram
, uint64_t gtt
)
1593 vram
+= cs
->used_vram
;
1594 gtt
+= cs
->used_gart
;
1596 /* Anything that goes above the VRAM size should go to GTT. */
1597 if (vram
> screen
->info
.vram_size
)
1598 gtt
+= vram
- screen
->info
.vram_size
;
1600 /* Now we just need to check if we have enough GTT. */
1601 return gtt
< screen
->info
.gart_size
* 0.7;
1605 * Add a buffer to the buffer list for the given command stream (CS).
1607 * All buffers used by a CS must be added to the list. This tells the kernel
1608 * driver which buffers are used by GPU commands. Other buffers can
1609 * be swapped out (not accessible) during execution.
1611 * The buffer list becomes empty after every context flush and must be
1614 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1615 struct radeon_cmdbuf
*cs
,
1616 struct r600_resource
*rbo
,
1617 enum radeon_bo_usage usage
,
1618 enum radeon_bo_priority priority
)
1621 sctx
->ws
->cs_add_buffer(
1623 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1624 rbo
->domains
, priority
);
1628 * Same as above, but also checks memory usage and flushes the context
1631 * When this SHOULD NOT be used:
1633 * - if si_context_add_resource_size has been called for the buffer
1634 * followed by *_need_cs_space for checking the memory usage
1636 * - if si_need_dma_space has been called for the buffer
1638 * - when emitting state packets and draw packets (because preceding packets
1639 * can't be re-emitted at that point)
1641 * - if shader resource "enabled_mask" is not up-to-date or there is
1642 * a different constraint disallowing a context flush
1645 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1646 struct r600_resource
*rbo
,
1647 enum radeon_bo_usage usage
,
1648 enum radeon_bo_priority priority
,
1652 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1653 sctx
->vram
+ rbo
->vram_usage
,
1654 sctx
->gtt
+ rbo
->gart_usage
))
1655 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1657 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, rbo
, usage
, priority
);
1660 #define PRINT_ERR(fmt, args...) \
1661 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)