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radeonsi: implement DCC fast clear swizzle constraints more accurately
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32
33 #ifdef PIPE_ARCH_BIG_ENDIAN
34 #define SI_BIG_ENDIAN 1
35 #else
36 #define SI_BIG_ENDIAN 0
37 #endif
38
39 #define ATI_VENDOR_ID 0x1002
40
41 #define SI_NOT_QUERY 0xffffffff
42
43 /* The base vertex and primitive restart can be any number, but we must pick
44 * one which will mean "unknown" for the purpose of state tracking and
45 * the number shouldn't be a commonly-used one. */
46 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
47 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
48 #define SI_NUM_SMOOTH_AA_SAMPLES 8
49 #define SI_GS_PER_ES 128
50 /* Alignment for optimal CP DMA performance. */
51 #define SI_CPDMA_ALIGNMENT 32
52
53 /* Pipeline & streamout query controls. */
54 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
55 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
56 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
57 /* Instruction cache. */
58 #define SI_CONTEXT_INV_ICACHE (1 << 3)
59 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
60 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
61 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
62 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
63 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
64 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
65 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
66 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
67 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
68 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
69 * a CB or DB flush. */
70 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
71 /* Framebuffer caches. */
72 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
73 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
74 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
75 /* Engine synchronization. */
76 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
77 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
78 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
79 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
80 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
81
82 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
83 #define SI_PREFETCH_LS (1 << 1)
84 #define SI_PREFETCH_HS (1 << 2)
85 #define SI_PREFETCH_ES (1 << 3)
86 #define SI_PREFETCH_GS (1 << 4)
87 #define SI_PREFETCH_VS (1 << 5)
88 #define SI_PREFETCH_PS (1 << 6)
89
90 #define SI_MAX_BORDER_COLORS 4096
91 #define SI_MAX_VIEWPORTS 16
92 #define SIX_BITS 0x3F
93 #define SI_MAP_BUFFER_ALIGNMENT 64
94 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
95
96 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
97 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
98 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
99 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
100 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
101 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
102 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
103
104 /* Debug flags. */
105 enum {
106 /* Shader logging options: */
107 DBG_VS = PIPE_SHADER_VERTEX,
108 DBG_PS = PIPE_SHADER_FRAGMENT,
109 DBG_GS = PIPE_SHADER_GEOMETRY,
110 DBG_TCS = PIPE_SHADER_TESS_CTRL,
111 DBG_TES = PIPE_SHADER_TESS_EVAL,
112 DBG_CS = PIPE_SHADER_COMPUTE,
113 DBG_NO_IR,
114 DBG_NO_TGSI,
115 DBG_NO_ASM,
116 DBG_PREOPT_IR,
117
118 /* Shader compiler options the shader cache should be aware of: */
119 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
120 DBG_UNSAFE_MATH,
121 DBG_SI_SCHED,
122
123 /* Shader compiler options (with no effect on the shader cache): */
124 DBG_CHECK_IR,
125 DBG_NIR,
126 DBG_MONOLITHIC_SHADERS,
127 DBG_NO_OPT_VARIANT,
128
129 /* Information logging options: */
130 DBG_INFO,
131 DBG_TEX,
132 DBG_COMPUTE,
133 DBG_VM,
134
135 /* Driver options: */
136 DBG_FORCE_DMA,
137 DBG_NO_ASYNC_DMA,
138 DBG_NO_WC,
139 DBG_CHECK_VM,
140 DBG_RESERVE_VMID,
141
142 /* 3D engine options: */
143 DBG_SWITCH_ON_EOP,
144 DBG_NO_OUT_OF_ORDER,
145 DBG_NO_DPBB,
146 DBG_NO_DFSM,
147 DBG_DPBB,
148 DBG_DFSM,
149 DBG_NO_HYPERZ,
150 DBG_NO_RB_PLUS,
151 DBG_NO_2D_TILING,
152 DBG_NO_TILING,
153 DBG_NO_DCC,
154 DBG_NO_DCC_CLEAR,
155 DBG_NO_DCC_FB,
156 DBG_NO_DCC_MSAA,
157 DBG_NO_FMASK,
158
159 /* Tests: */
160 DBG_TEST_DMA,
161 DBG_TEST_VMFAULT_CP,
162 DBG_TEST_VMFAULT_SDMA,
163 DBG_TEST_VMFAULT_SHADER,
164 };
165
166 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
167 #define DBG(name) (1ull << DBG_##name)
168
169 struct si_compute;
170 struct hash_table;
171 struct u_suballocator;
172
173 struct si_screen {
174 struct pipe_screen b;
175 struct radeon_winsys *ws;
176 struct disk_cache *disk_shader_cache;
177
178 struct radeon_info info;
179 uint64_t debug_flags;
180 char renderer_string[100];
181
182 unsigned gs_table_depth;
183 unsigned tess_offchip_block_dw_size;
184 unsigned tess_offchip_ring_size;
185 unsigned tess_factor_ring_size;
186 unsigned vgt_hs_offchip_param;
187 bool has_clear_state;
188 bool has_distributed_tess;
189 bool has_draw_indirect_multi;
190 bool has_out_of_order_rast;
191 bool assume_no_z_fights;
192 bool commutative_blend_add;
193 bool clear_db_cache_before_clear;
194 bool has_msaa_sample_loc_bug;
195 bool has_ls_vgpr_init_bug;
196 bool dpbb_allowed;
197 bool dfsm_allowed;
198 bool llvm_has_working_vgpr_indexing;
199
200 /* Whether shaders are monolithic (1-part) or separate (3-part). */
201 bool use_monolithic_shaders;
202 bool record_llvm_ir;
203 bool has_rbplus; /* if RB+ registers exist */
204 bool rbplus_allowed; /* if RB+ is allowed */
205 bool dcc_msaa_allowed;
206 bool cpdma_prefetch_writes_memory;
207
208 struct slab_parent_pool pool_transfers;
209
210 /* Texture filter settings. */
211 int force_aniso; /* -1 = disabled */
212
213 /* Auxiliary context. Mainly used to initialize resources.
214 * It must be locked prior to using and flushed before unlocking. */
215 struct pipe_context *aux_context;
216 mtx_t aux_context_lock;
217
218 /* This must be in the screen, because UE4 uses one context for
219 * compilation and another one for rendering.
220 */
221 unsigned num_compilations;
222 /* Along with ST_DEBUG=precompile, this should show if applications
223 * are loading shaders on demand. This is a monotonic counter.
224 */
225 unsigned num_shaders_created;
226 unsigned num_shader_cache_hits;
227
228 /* GPU load thread. */
229 mtx_t gpu_load_mutex;
230 thrd_t gpu_load_thread;
231 union si_mmio_counters mmio_counters;
232 volatile unsigned gpu_load_stop_thread; /* bool */
233
234 /* Performance counters. */
235 struct si_perfcounters *perfcounters;
236
237 /* If pipe_screen wants to recompute and re-emit the framebuffer,
238 * sampler, and image states of all contexts, it should atomically
239 * increment this.
240 *
241 * Each context will compare this with its own last known value of
242 * the counter before drawing and re-emit the states accordingly.
243 */
244 unsigned dirty_tex_counter;
245
246 /* Atomically increment this counter when an existing texture's
247 * metadata is enabled or disabled in a way that requires changing
248 * contexts' compressed texture binding masks.
249 */
250 unsigned compressed_colortex_counter;
251
252 struct {
253 /* Context flags to set so that all writes from earlier jobs
254 * in the CP are seen by L2 clients.
255 */
256 unsigned cp_to_L2;
257
258 /* Context flags to set so that all writes from earlier jobs
259 * that end in L2 are seen by CP.
260 */
261 unsigned L2_to_cp;
262 } barrier_flags;
263
264 mtx_t shader_parts_mutex;
265 struct si_shader_part *vs_prologs;
266 struct si_shader_part *tcs_epilogs;
267 struct si_shader_part *gs_prologs;
268 struct si_shader_part *ps_prologs;
269 struct si_shader_part *ps_epilogs;
270
271 /* Shader cache in memory.
272 *
273 * Design & limitations:
274 * - The shader cache is per screen (= per process), never saved to
275 * disk, and skips redundant shader compilations from TGSI to bytecode.
276 * - It can only be used with one-variant-per-shader support, in which
277 * case only the main (typically middle) part of shaders is cached.
278 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
279 * variants of VS and TES are cached, so LS and ES aren't.
280 * - GS and CS aren't cached, but it's certainly possible to cache
281 * those as well.
282 */
283 mtx_t shader_cache_mutex;
284 struct hash_table *shader_cache;
285
286 /* Shader compiler queue for multithreaded compilation. */
287 struct util_queue shader_compiler_queue;
288 /* Use at most 3 normal compiler threads on quadcore and better.
289 * Hyperthreaded CPUs report the number of threads, but we want
290 * the number of cores. */
291 LLVMTargetMachineRef tm[3]; /* used by the queue only */
292
293 struct util_queue shader_compiler_queue_low_priority;
294 /* Use at most 2 low priority threads on quadcore and better.
295 * We want to minimize the impact on multithreaded Mesa. */
296 LLVMTargetMachineRef tm_low_priority[2]; /* at most 2 threads */
297 };
298
299 struct si_blend_color {
300 struct r600_atom atom;
301 struct pipe_blend_color state;
302 bool any_nonzeros;
303 };
304
305 struct si_sampler_view {
306 struct pipe_sampler_view base;
307 /* [0..7] = image descriptor
308 * [4..7] = buffer descriptor */
309 uint32_t state[8];
310 uint32_t fmask_state[8];
311 const struct legacy_surf_level *base_level_info;
312 ubyte base_level;
313 ubyte block_width;
314 bool is_stencil_sampler;
315 bool is_integer;
316 bool dcc_incompatible;
317 };
318
319 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
320
321 struct si_sampler_state {
322 #ifdef DEBUG
323 unsigned magic;
324 #endif
325 uint32_t val[4];
326 uint32_t integer_val[4];
327 uint32_t upgraded_depth_val[4];
328 };
329
330 struct si_cs_shader_state {
331 struct si_compute *program;
332 struct si_compute *emitted_program;
333 unsigned offset;
334 bool initialized;
335 bool uses_scratch;
336 };
337
338 struct si_samplers {
339 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
340 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
341
342 /* The i-th bit is set if that element is enabled (non-NULL resource). */
343 unsigned enabled_mask;
344 uint32_t needs_depth_decompress_mask;
345 uint32_t needs_color_decompress_mask;
346 };
347
348 struct si_images {
349 struct pipe_image_view views[SI_NUM_IMAGES];
350 uint32_t needs_color_decompress_mask;
351 unsigned enabled_mask;
352 };
353
354 struct si_framebuffer {
355 struct r600_atom atom;
356 struct pipe_framebuffer_state state;
357 unsigned colorbuf_enabled_4bit;
358 unsigned spi_shader_col_format;
359 unsigned spi_shader_col_format_alpha;
360 unsigned spi_shader_col_format_blend;
361 unsigned spi_shader_col_format_blend_alpha;
362 ubyte nr_samples:5; /* at most 16xAA */
363 ubyte log_samples:3; /* at most 4 = 16xAA */
364 ubyte compressed_cb_mask;
365 ubyte uncompressed_cb_mask;
366 ubyte color_is_int8;
367 ubyte color_is_int10;
368 ubyte dirty_cbufs;
369 bool dirty_zsbuf;
370 bool any_dst_linear;
371 bool CB_has_shader_readable_metadata;
372 bool DB_has_shader_readable_metadata;
373 };
374
375 struct si_signed_scissor {
376 int minx;
377 int miny;
378 int maxx;
379 int maxy;
380 };
381
382 struct si_scissors {
383 struct r600_atom atom;
384 unsigned dirty_mask;
385 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
386 };
387
388 struct si_viewports {
389 struct r600_atom atom;
390 unsigned dirty_mask;
391 unsigned depth_range_dirty_mask;
392 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
393 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
394 };
395
396 struct si_clip_state {
397 struct r600_atom atom;
398 struct pipe_clip_state state;
399 bool any_nonzeros;
400 };
401
402 struct si_sample_locs {
403 struct r600_atom atom;
404 unsigned nr_samples;
405 };
406
407 struct si_sample_mask {
408 struct r600_atom atom;
409 uint16_t sample_mask;
410 };
411
412 struct si_streamout_target {
413 struct pipe_stream_output_target b;
414
415 /* The buffer where BUFFER_FILLED_SIZE is stored. */
416 struct r600_resource *buf_filled_size;
417 unsigned buf_filled_size_offset;
418 bool buf_filled_size_valid;
419
420 unsigned stride_in_dw;
421 };
422
423 struct si_streamout {
424 struct r600_atom begin_atom;
425 bool begin_emitted;
426
427 unsigned enabled_mask;
428 unsigned num_targets;
429 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
430
431 unsigned append_bitmask;
432 bool suspended;
433
434 /* External state which comes from the vertex shader,
435 * it must be set explicitly when binding a shader. */
436 uint16_t *stride_in_dw;
437 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
438
439 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
440 unsigned hw_enabled_mask;
441
442 /* The state of VGT_STRMOUT_(CONFIG|EN). */
443 struct r600_atom enable_atom;
444 bool streamout_enabled;
445 bool prims_gen_query_enabled;
446 int num_prims_gen_queries;
447 };
448
449 /* A shader state consists of the shader selector, which is a constant state
450 * object shared by multiple contexts and shouldn't be modified, and
451 * the current shader variant selected for this context.
452 */
453 struct si_shader_ctx_state {
454 struct si_shader_selector *cso;
455 struct si_shader *current;
456 };
457
458 #define SI_NUM_VGT_PARAM_KEY_BITS 12
459 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
460
461 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
462 * Some fields are set by state-change calls, most are set by draw_vbo.
463 */
464 union si_vgt_param_key {
465 struct {
466 #ifdef PIPE_ARCH_LITTLE_ENDIAN
467 unsigned prim:4;
468 unsigned uses_instancing:1;
469 unsigned multi_instances_smaller_than_primgroup:1;
470 unsigned primitive_restart:1;
471 unsigned count_from_stream_output:1;
472 unsigned line_stipple_enabled:1;
473 unsigned uses_tess:1;
474 unsigned tess_uses_prim_id:1;
475 unsigned uses_gs:1;
476 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
477 #else /* PIPE_ARCH_BIG_ENDIAN */
478 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
479 unsigned uses_gs:1;
480 unsigned tess_uses_prim_id:1;
481 unsigned uses_tess:1;
482 unsigned line_stipple_enabled:1;
483 unsigned count_from_stream_output:1;
484 unsigned primitive_restart:1;
485 unsigned multi_instances_smaller_than_primgroup:1;
486 unsigned uses_instancing:1;
487 unsigned prim:4;
488 #endif
489 } u;
490 uint32_t index;
491 };
492
493 struct si_texture_handle
494 {
495 unsigned desc_slot;
496 bool desc_dirty;
497 struct pipe_sampler_view *view;
498 struct si_sampler_state sstate;
499 };
500
501 struct si_image_handle
502 {
503 unsigned desc_slot;
504 bool desc_dirty;
505 struct pipe_image_view view;
506 };
507
508 struct si_saved_cs {
509 struct pipe_reference reference;
510 struct si_context *ctx;
511 struct radeon_saved_cs gfx;
512 struct r600_resource *trace_buf;
513 unsigned trace_id;
514
515 unsigned gfx_last_dw;
516 bool flushed;
517 int64_t time_flush;
518 };
519
520 struct si_context {
521 struct pipe_context b; /* base class */
522
523 enum radeon_family family;
524 enum chip_class chip_class;
525
526 struct radeon_winsys *ws;
527 struct radeon_winsys_ctx *ctx;
528 struct radeon_winsys_cs *gfx_cs;
529 struct radeon_winsys_cs *dma_cs;
530 struct pipe_fence_handle *last_gfx_fence;
531 struct pipe_fence_handle *last_sdma_fence;
532 struct r600_resource *eop_bug_scratch;
533 struct u_upload_mgr *cached_gtt_allocator;
534 struct threaded_context *tc;
535 struct u_suballocator *allocator_zeroed_memory;
536 struct slab_child_pool pool_transfers;
537 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
538 struct pipe_device_reset_callback device_reset_callback;
539 struct u_log_context *log;
540 void *query_result_shader;
541 struct blitter_context *blitter;
542 void *custom_dsa_flush;
543 void *custom_blend_resolve;
544 void *custom_blend_fmask_decompress;
545 void *custom_blend_eliminate_fastclear;
546 void *custom_blend_dcc_decompress;
547 void *vs_blit_pos;
548 void *vs_blit_pos_layered;
549 void *vs_blit_color;
550 void *vs_blit_color_layered;
551 void *vs_blit_texcoord;
552 struct si_screen *screen;
553 struct pipe_debug_callback debug;
554 LLVMTargetMachineRef tm; /* only non-threaded compilation */
555 struct si_shader_ctx_state fixed_func_tcs_shader;
556 struct r600_resource *wait_mem_scratch;
557 unsigned wait_mem_number;
558 uint16_t prefetch_L2_mask;
559
560 bool gfx_flush_in_progress:1;
561 bool gfx_last_ib_is_busy:1;
562 bool compute_is_busy:1;
563
564 unsigned num_gfx_cs_flushes;
565 unsigned initial_gfx_cs_size;
566 unsigned gpu_reset_counter;
567 unsigned last_dirty_tex_counter;
568 unsigned last_compressed_colortex_counter;
569 unsigned last_num_draw_calls;
570 unsigned flags; /* flush flags */
571 /* Current unaccounted memory usage. */
572 uint64_t vram;
573 uint64_t gtt;
574
575 /* Atoms (direct states). */
576 union si_state_atoms atoms;
577 unsigned dirty_atoms; /* mask */
578 /* PM4 states (precomputed immutable states) */
579 unsigned dirty_states;
580 union si_state queued;
581 union si_state emitted;
582
583 /* Atom declarations. */
584 struct si_framebuffer framebuffer;
585 struct si_sample_locs msaa_sample_locs;
586 struct r600_atom db_render_state;
587 struct r600_atom dpbb_state;
588 struct r600_atom msaa_config;
589 struct si_sample_mask sample_mask;
590 struct r600_atom cb_render_state;
591 unsigned last_cb_target_mask;
592 struct si_blend_color blend_color;
593 struct r600_atom clip_regs;
594 struct si_clip_state clip_state;
595 struct si_shader_data shader_pointers;
596 struct si_stencil_ref stencil_ref;
597 struct r600_atom spi_map;
598 struct si_scissors scissors;
599 struct si_streamout streamout;
600 struct si_viewports viewports;
601
602 /* Precomputed states. */
603 struct si_pm4_state *init_config;
604 struct si_pm4_state *init_config_gs_rings;
605 bool init_config_has_vgt_flush;
606 struct si_pm4_state *vgt_shader_config[4];
607
608 /* shaders */
609 struct si_shader_ctx_state ps_shader;
610 struct si_shader_ctx_state gs_shader;
611 struct si_shader_ctx_state vs_shader;
612 struct si_shader_ctx_state tcs_shader;
613 struct si_shader_ctx_state tes_shader;
614 struct si_cs_shader_state cs_shader_state;
615
616 /* shader information */
617 struct si_vertex_elements *vertex_elements;
618 unsigned sprite_coord_enable;
619 bool flatshade;
620 bool do_update_shaders;
621
622 /* vertex buffer descriptors */
623 uint32_t *vb_descriptors_gpu_list;
624 struct r600_resource *vb_descriptors_buffer;
625 unsigned vb_descriptors_offset;
626
627 /* shader descriptors */
628 struct si_descriptors descriptors[SI_NUM_DESCS];
629 unsigned descriptors_dirty;
630 unsigned shader_pointers_dirty;
631 unsigned shader_needs_decompress_mask;
632 struct si_buffer_resources rw_buffers;
633 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
634 struct si_samplers samplers[SI_NUM_SHADERS];
635 struct si_images images[SI_NUM_SHADERS];
636
637 /* other shader resources */
638 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
639 struct pipe_resource *esgs_ring;
640 struct pipe_resource *gsvs_ring;
641 struct pipe_resource *tess_rings;
642 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
643 struct r600_resource *border_color_buffer;
644 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
645 unsigned border_color_count;
646 unsigned num_vs_blit_sgprs;
647 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
648
649 /* Vertex and index buffers. */
650 bool vertex_buffers_dirty;
651 bool vertex_buffer_pointer_dirty;
652 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
653
654 /* MSAA config state. */
655 int ps_iter_samples;
656 bool ps_uses_fbfetch;
657 bool smoothing_enabled;
658
659 /* DB render state. */
660 unsigned ps_db_shader_control;
661 unsigned dbcb_copy_sample;
662 bool dbcb_depth_copy_enabled:1;
663 bool dbcb_stencil_copy_enabled:1;
664 bool db_flush_depth_inplace:1;
665 bool db_flush_stencil_inplace:1;
666 bool db_depth_clear:1;
667 bool db_depth_disable_expclear:1;
668 bool db_stencil_clear:1;
669 bool db_stencil_disable_expclear:1;
670 bool occlusion_queries_disabled:1;
671 bool generate_mipmap_for_depth:1;
672
673 /* Emitted draw state. */
674 bool gs_tri_strip_adj_fix:1;
675 bool ls_vgpr_fix:1;
676 int last_index_size;
677 int last_base_vertex;
678 int last_start_instance;
679 int last_drawid;
680 int last_sh_base_reg;
681 int last_primitive_restart_en;
682 int last_restart_index;
683 int last_gs_out_prim;
684 int last_prim;
685 int last_multi_vgt_param;
686 int last_rast_prim;
687 unsigned last_sc_line_stipple;
688 unsigned current_vs_state;
689 unsigned last_vs_state;
690 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
691
692 /* Scratch buffer */
693 struct r600_atom scratch_state;
694 struct r600_resource *scratch_buffer;
695 unsigned scratch_waves;
696 unsigned spi_tmpring_size;
697
698 struct r600_resource *compute_scratch_buffer;
699
700 /* Emitted derived tessellation state. */
701 /* Local shader (VS), or HS if LS-HS are merged. */
702 struct si_shader *last_ls;
703 struct si_shader_selector *last_tcs;
704 int last_num_tcs_input_cp;
705 int last_tes_sh_base;
706 bool last_tess_uses_primid;
707 unsigned last_num_patches;
708
709 /* Debug state. */
710 bool is_debug;
711 struct si_saved_cs *current_saved_cs;
712 uint64_t dmesg_timestamp;
713 unsigned apitrace_call_number;
714
715 /* Other state */
716 bool need_check_render_feedback;
717 bool decompression_enabled;
718
719 bool vs_writes_viewport_index;
720 bool vs_disables_clipping_viewport;
721
722 /* Precomputed IA_MULTI_VGT_PARAM */
723 union si_vgt_param_key ia_multi_vgt_param_key;
724 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
725
726 /* Bindless descriptors. */
727 struct si_descriptors bindless_descriptors;
728 struct util_idalloc bindless_used_slots;
729 unsigned num_bindless_descriptors;
730 bool bindless_descriptors_dirty;
731 bool graphics_bindless_pointer_dirty;
732 bool compute_bindless_pointer_dirty;
733
734 /* Allocated bindless handles */
735 struct hash_table *tex_handles;
736 struct hash_table *img_handles;
737
738 /* Resident bindless handles */
739 struct util_dynarray resident_tex_handles;
740 struct util_dynarray resident_img_handles;
741
742 /* Resident bindless handles which need decompression */
743 struct util_dynarray resident_tex_needs_color_decompress;
744 struct util_dynarray resident_img_needs_color_decompress;
745 struct util_dynarray resident_tex_needs_depth_decompress;
746
747 /* Bindless state */
748 bool uses_bindless_samplers;
749 bool uses_bindless_images;
750
751 /* MSAA sample locations.
752 * The first index is the sample index.
753 * The second index is the coordinate: X, Y. */
754 float sample_locations_1x[1][2];
755 float sample_locations_2x[2][2];
756 float sample_locations_4x[4][2];
757 float sample_locations_8x[8][2];
758 float sample_locations_16x[16][2];
759
760 /* Misc stats. */
761 unsigned num_draw_calls;
762 unsigned num_decompress_calls;
763 unsigned num_mrt_draw_calls;
764 unsigned num_prim_restart_calls;
765 unsigned num_spill_draw_calls;
766 unsigned num_compute_calls;
767 unsigned num_spill_compute_calls;
768 unsigned num_dma_calls;
769 unsigned num_cp_dma_calls;
770 unsigned num_vs_flushes;
771 unsigned num_ps_flushes;
772 unsigned num_cs_flushes;
773 unsigned num_cb_cache_flushes;
774 unsigned num_db_cache_flushes;
775 unsigned num_L2_invalidates;
776 unsigned num_L2_writebacks;
777 unsigned num_resident_handles;
778 uint64_t num_alloc_tex_transfer_bytes;
779 unsigned last_tex_ps_draw_ratio; /* for query */
780
781 /* Queries. */
782 /* Maintain the list of active queries for pausing between IBs. */
783 int num_occlusion_queries;
784 int num_perfect_occlusion_queries;
785 struct list_head active_queries;
786 unsigned num_cs_dw_queries_suspend;
787
788 /* Render condition. */
789 struct r600_atom render_cond_atom;
790 struct pipe_query *render_cond;
791 unsigned render_cond_mode;
792 bool render_cond_invert;
793 bool render_cond_force_off; /* for u_blitter */
794
795 /* Statistics gathering for the DCC enablement heuristic. It can't be
796 * in r600_texture because r600_texture can be shared by multiple
797 * contexts. This is for back buffers only. We shouldn't get too many
798 * of those.
799 *
800 * X11 DRI3 rotates among a finite set of back buffers. They should
801 * all fit in this array. If they don't, separate DCC might never be
802 * enabled by DCC stat gathering.
803 */
804 struct {
805 struct r600_texture *tex;
806 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
807 struct pipe_query *ps_stats[3];
808 /* If all slots are used and another slot is needed,
809 * the least recently used slot is evicted based on this. */
810 int64_t last_use_timestamp;
811 bool query_active;
812 } dcc_stats[5];
813
814 /* Copy one resource to another using async DMA. */
815 void (*dma_copy)(struct pipe_context *ctx,
816 struct pipe_resource *dst,
817 unsigned dst_level,
818 unsigned dst_x, unsigned dst_y, unsigned dst_z,
819 struct pipe_resource *src,
820 unsigned src_level,
821 const struct pipe_box *src_box);
822
823 void (*dma_clear_buffer)(struct si_context *sctx, struct pipe_resource *dst,
824 uint64_t offset, uint64_t size, unsigned value);
825 };
826
827 /* cik_sdma.c */
828 void cik_init_sdma_functions(struct si_context *sctx);
829
830 /* si_blit.c */
831 enum si_blitter_op /* bitmask */
832 {
833 SI_SAVE_TEXTURES = 1,
834 SI_SAVE_FRAMEBUFFER = 2,
835 SI_SAVE_FRAGMENT_STATE = 4,
836 SI_DISABLE_RENDER_COND = 8,
837 };
838
839 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
840 void si_blitter_end(struct si_context *sctx);
841 void si_init_blit_functions(struct si_context *sctx);
842 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
843 void si_resource_copy_region(struct pipe_context *ctx,
844 struct pipe_resource *dst,
845 unsigned dst_level,
846 unsigned dstx, unsigned dsty, unsigned dstz,
847 struct pipe_resource *src,
848 unsigned src_level,
849 const struct pipe_box *src_box);
850 void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex);
851 void si_blit_decompress_depth(struct pipe_context *ctx,
852 struct r600_texture *texture,
853 struct r600_texture *staging,
854 unsigned first_level, unsigned last_level,
855 unsigned first_layer, unsigned last_layer,
856 unsigned first_sample, unsigned last_sample);
857
858 /* si_buffer.c */
859 bool si_rings_is_buffer_referenced(struct si_context *sctx,
860 struct pb_buffer *buf,
861 enum radeon_bo_usage usage);
862 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
863 struct r600_resource *resource,
864 unsigned usage);
865 void si_init_resource_fields(struct si_screen *sscreen,
866 struct r600_resource *res,
867 uint64_t size, unsigned alignment);
868 bool si_alloc_resource(struct si_screen *sscreen,
869 struct r600_resource *res);
870 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
871 unsigned flags,
872 unsigned usage,
873 unsigned size,
874 unsigned alignment);
875 void si_replace_buffer_storage(struct pipe_context *ctx,
876 struct pipe_resource *dst,
877 struct pipe_resource *src);
878 void si_init_screen_buffer_functions(struct si_screen *sscreen);
879 void si_init_buffer_functions(struct si_context *sctx);
880
881 /* si_clear.c */
882 enum pipe_format si_simplify_cb_format(enum pipe_format format);
883 bool vi_alpha_is_on_msb(enum pipe_format format);
884 void vi_dcc_clear_level(struct si_context *sctx,
885 struct r600_texture *rtex,
886 unsigned level, unsigned clear_value);
887 void si_init_clear_functions(struct si_context *sctx);
888
889 /* si_cp_dma.c */
890 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
891 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
892 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
893 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
894 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
895 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
896 SI_CPDMA_SKIP_SYNC_AFTER | \
897 SI_CPDMA_SKIP_SYNC_BEFORE | \
898 SI_CPDMA_SKIP_GFX_SYNC | \
899 SI_CPDMA_SKIP_BO_LIST_UPDATE)
900
901 enum si_coherency {
902 SI_COHERENCY_NONE, /* no cache flushes needed */
903 SI_COHERENCY_SHADER,
904 SI_COHERENCY_CB_META,
905 };
906
907 void si_cp_dma_wait_for_idle(struct si_context *sctx);
908 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
909 uint64_t offset, uint64_t size, unsigned value,
910 enum si_coherency coher);
911 void si_copy_buffer(struct si_context *sctx,
912 struct pipe_resource *dst, struct pipe_resource *src,
913 uint64_t dst_offset, uint64_t src_offset, unsigned size,
914 unsigned user_flags);
915 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
916 uint64_t offset, unsigned size);
917 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
918 void si_init_cp_dma_functions(struct si_context *sctx);
919
920 /* si_debug.c */
921 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
922 struct radeon_saved_cs *saved, bool get_buffer_list);
923 void si_clear_saved_cs(struct radeon_saved_cs *saved);
924 void si_destroy_saved_cs(struct si_saved_cs *scs);
925 void si_auto_log_cs(void *data, struct u_log_context *log);
926 void si_log_hw_flush(struct si_context *sctx);
927 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
928 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
929 void si_init_debug_functions(struct si_context *sctx);
930 void si_check_vm_faults(struct si_context *sctx,
931 struct radeon_saved_cs *saved, enum ring_type ring);
932 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
933
934 /* si_dma.c */
935 void si_init_dma_functions(struct si_context *sctx);
936
937 /* si_dma_cs.c */
938 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
939 struct r600_resource *dst, struct r600_resource *src);
940 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
941 struct pipe_fence_handle **fence);
942 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
943 uint64_t offset, uint64_t size, unsigned value);
944
945 /* si_fence.c */
946 void si_gfx_write_event_eop(struct si_context *ctx,
947 unsigned event, unsigned event_flags,
948 unsigned data_sel,
949 struct r600_resource *buf, uint64_t va,
950 uint32_t new_fence, unsigned query_type);
951 unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
952 void si_gfx_wait_fence(struct si_context *ctx,
953 uint64_t va, uint32_t ref, uint32_t mask);
954 void si_init_fence_functions(struct si_context *ctx);
955 void si_init_screen_fence_functions(struct si_screen *screen);
956 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
957 struct tc_unflushed_batch_token *tc_token);
958
959 /* si_get.c */
960 const char *si_get_family_name(const struct si_screen *sscreen);
961 void si_init_screen_get_functions(struct si_screen *sscreen);
962
963 /* si_gfx_cs.c */
964 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
965 struct pipe_fence_handle **fence);
966 void si_begin_new_gfx_cs(struct si_context *ctx);
967 void si_need_gfx_cs_space(struct si_context *ctx);
968
969 /* r600_gpu_load.c */
970 void si_gpu_load_kill_thread(struct si_screen *sscreen);
971 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
972 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
973 uint64_t begin);
974
975 /* si_compute.c */
976 void si_init_compute_functions(struct si_context *sctx);
977
978 /* si_perfcounters.c */
979 void si_init_perfcounters(struct si_screen *screen);
980
981 /* si_pipe.c */
982 bool si_check_device_reset(struct si_context *sctx);
983
984 /* si_query.c */
985 void si_init_screen_query_functions(struct si_screen *sscreen);
986 void si_init_query_functions(struct si_context *sctx);
987 void si_suspend_queries(struct si_context *sctx);
988 void si_resume_queries(struct si_context *sctx);
989
990 /* si_test_dma.c */
991 void si_test_dma(struct si_screen *sscreen);
992
993 /* si_uvd.c */
994 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
995 const struct pipe_video_codec *templ);
996
997 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
998 const struct pipe_video_buffer *tmpl);
999
1000 /* si_viewport.c */
1001 void si_update_vs_viewport_state(struct si_context *ctx);
1002 void si_init_viewport_functions(struct si_context *ctx);
1003
1004 /* r600_texture.c */
1005 bool si_prepare_for_dma_blit(struct si_context *sctx,
1006 struct r600_texture *rdst,
1007 unsigned dst_level, unsigned dstx,
1008 unsigned dsty, unsigned dstz,
1009 struct r600_texture *rsrc,
1010 unsigned src_level,
1011 const struct pipe_box *src_box);
1012 void si_texture_get_fmask_info(struct si_screen *sscreen,
1013 struct r600_texture *rtex,
1014 unsigned nr_samples,
1015 struct r600_fmask_info *out);
1016 void si_texture_get_cmask_info(struct si_screen *sscreen,
1017 struct r600_texture *rtex,
1018 struct r600_cmask_info *out);
1019 void si_eliminate_fast_color_clear(struct si_context *sctx,
1020 struct r600_texture *rtex);
1021 void si_texture_discard_cmask(struct si_screen *sscreen,
1022 struct r600_texture *rtex);
1023 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1024 struct pipe_resource *texture,
1025 struct r600_texture **staging);
1026 void si_print_texture_info(struct si_screen *sscreen,
1027 struct r600_texture *rtex, struct u_log_context *log);
1028 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1029 const struct pipe_resource *templ);
1030 bool vi_dcc_formats_compatible(enum pipe_format format1,
1031 enum pipe_format format2);
1032 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1033 unsigned level,
1034 enum pipe_format view_format);
1035 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1036 struct pipe_resource *tex,
1037 unsigned level,
1038 enum pipe_format view_format);
1039 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1040 struct pipe_resource *texture,
1041 const struct pipe_surface *templ,
1042 unsigned width0, unsigned height0,
1043 unsigned width, unsigned height);
1044 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1045 void vi_separate_dcc_try_enable(struct si_context *sctx,
1046 struct r600_texture *tex);
1047 void vi_separate_dcc_start_query(struct si_context *sctx,
1048 struct r600_texture *tex);
1049 void vi_separate_dcc_stop_query(struct si_context *sctx,
1050 struct r600_texture *tex);
1051 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1052 struct r600_texture *tex);
1053 bool si_texture_disable_dcc(struct si_context *sctx,
1054 struct r600_texture *rtex);
1055 void si_init_screen_texture_functions(struct si_screen *sscreen);
1056 void si_init_context_texture_functions(struct si_context *sctx);
1057
1058
1059 /*
1060 * common helpers
1061 */
1062
1063 static inline void
1064 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1065 {
1066 struct r600_resource *res = (struct r600_resource *)r;
1067
1068 if (res) {
1069 /* Add memory usage for need_gfx_cs_space */
1070 sctx->vram += res->vram_usage;
1071 sctx->gtt += res->gart_usage;
1072 }
1073 }
1074
1075 static inline void
1076 si_invalidate_draw_sh_constants(struct si_context *sctx)
1077 {
1078 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1079 }
1080
1081 static inline void
1082 si_set_atom_dirty(struct si_context *sctx,
1083 struct r600_atom *atom, bool dirty)
1084 {
1085 unsigned bit = 1 << atom->id;
1086
1087 if (dirty)
1088 sctx->dirty_atoms |= bit;
1089 else
1090 sctx->dirty_atoms &= ~bit;
1091 }
1092
1093 static inline bool
1094 si_is_atom_dirty(struct si_context *sctx,
1095 struct r600_atom *atom)
1096 {
1097 unsigned bit = 1 << atom->id;
1098
1099 return sctx->dirty_atoms & bit;
1100 }
1101
1102 static inline void
1103 si_mark_atom_dirty(struct si_context *sctx,
1104 struct r600_atom *atom)
1105 {
1106 si_set_atom_dirty(sctx, atom, true);
1107 }
1108
1109 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1110 {
1111 if (sctx->gs_shader.cso)
1112 return &sctx->gs_shader;
1113 if (sctx->tes_shader.cso)
1114 return &sctx->tes_shader;
1115
1116 return &sctx->vs_shader;
1117 }
1118
1119 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1120 {
1121 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1122
1123 return vs->cso ? &vs->cso->info : NULL;
1124 }
1125
1126 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1127 {
1128 if (sctx->gs_shader.cso)
1129 return sctx->gs_shader.cso->gs_copy_shader;
1130
1131 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1132 return vs->current ? vs->current : NULL;
1133 }
1134
1135 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1136 unsigned processor)
1137 {
1138 return sscreen->debug_flags & (1 << processor);
1139 }
1140
1141 static inline bool si_extra_shader_checks(struct si_screen *sscreen,
1142 unsigned processor)
1143 {
1144 return (sscreen->debug_flags & DBG(CHECK_IR)) ||
1145 si_can_dump_shader(sscreen, processor);
1146 }
1147
1148 static inline bool si_get_strmout_en(struct si_context *sctx)
1149 {
1150 return sctx->streamout.streamout_enabled ||
1151 sctx->streamout.prims_gen_query_enabled;
1152 }
1153
1154 static inline unsigned
1155 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1156 {
1157 unsigned alignment, tcc_cache_line_size;
1158
1159 /* If the upload size is less than the cache line size (e.g. 16, 32),
1160 * the whole thing will fit into a cache line if we align it to its size.
1161 * The idea is that multiple small uploads can share a cache line.
1162 * If the upload size is greater, align it to the cache line size.
1163 */
1164 alignment = util_next_power_of_two(upload_size);
1165 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1166 return MIN2(alignment, tcc_cache_line_size);
1167 }
1168
1169 static inline void
1170 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1171 {
1172 if (pipe_reference(&(*dst)->reference, &src->reference))
1173 si_destroy_saved_cs(*dst);
1174
1175 *dst = src;
1176 }
1177
1178 static inline void
1179 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1180 bool shaders_read_metadata)
1181 {
1182 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1183 SI_CONTEXT_INV_VMEM_L1;
1184
1185 if (sctx->chip_class >= GFX9) {
1186 /* Single-sample color is coherent with shaders on GFX9, but
1187 * L2 metadata must be flushed if shaders read metadata.
1188 * (DCC, CMASK).
1189 */
1190 if (num_samples >= 2)
1191 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1192 else if (shaders_read_metadata)
1193 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1194 } else {
1195 /* SI-CI-VI */
1196 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1197 }
1198 }
1199
1200 static inline void
1201 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1202 bool include_stencil, bool shaders_read_metadata)
1203 {
1204 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1205 SI_CONTEXT_INV_VMEM_L1;
1206
1207 if (sctx->chip_class >= GFX9) {
1208 /* Single-sample depth (not stencil) is coherent with shaders
1209 * on GFX9, but L2 metadata must be flushed if shaders read
1210 * metadata.
1211 */
1212 if (num_samples >= 2 || include_stencil)
1213 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1214 else if (shaders_read_metadata)
1215 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1216 } else {
1217 /* SI-CI-VI */
1218 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1219 }
1220 }
1221
1222 static inline bool
1223 si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
1224 {
1225 return (stencil_sampler && tex->can_sample_s) ||
1226 (!stencil_sampler && tex->can_sample_z);
1227 }
1228
1229 static inline bool
1230 si_htile_enabled(struct r600_texture *tex, unsigned level)
1231 {
1232 return tex->htile_offset && level == 0;
1233 }
1234
1235 static inline bool
1236 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
1237 {
1238 assert(!tex->tc_compatible_htile || tex->htile_offset);
1239 return tex->tc_compatible_htile && level == 0;
1240 }
1241
1242 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1243 {
1244 if (sctx->ps_uses_fbfetch)
1245 return sctx->framebuffer.nr_samples;
1246
1247 return sctx->ps_iter_samples;
1248 }
1249
1250 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1251 {
1252 if (sctx->queued.named.rasterizer->rasterizer_discard)
1253 return 0;
1254
1255 struct si_shader_selector *ps = sctx->ps_shader.cso;
1256 if (!ps)
1257 return 0;
1258
1259 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1260 sctx->queued.named.blend->cb_target_mask;
1261
1262 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1263 colormask &= ps->colors_written_4bit;
1264 else if (!ps->colors_written_4bit)
1265 colormask = 0; /* color0 writes all cbufs, but it's not written */
1266
1267 return colormask;
1268 }
1269
1270 /**
1271 * Return true if there is enough memory in VRAM and GTT for the buffers
1272 * added so far.
1273 *
1274 * \param vram VRAM memory size not added to the buffer list yet
1275 * \param gtt GTT memory size not added to the buffer list yet
1276 */
1277 static inline bool
1278 radeon_cs_memory_below_limit(struct si_screen *screen,
1279 struct radeon_winsys_cs *cs,
1280 uint64_t vram, uint64_t gtt)
1281 {
1282 vram += cs->used_vram;
1283 gtt += cs->used_gart;
1284
1285 /* Anything that goes above the VRAM size should go to GTT. */
1286 if (vram > screen->info.vram_size)
1287 gtt += vram - screen->info.vram_size;
1288
1289 /* Now we just need to check if we have enough GTT. */
1290 return gtt < screen->info.gart_size * 0.7;
1291 }
1292
1293 /**
1294 * Add a buffer to the buffer list for the given command stream (CS).
1295 *
1296 * All buffers used by a CS must be added to the list. This tells the kernel
1297 * driver which buffers are used by GPU commands. Other buffers can
1298 * be swapped out (not accessible) during execution.
1299 *
1300 * The buffer list becomes empty after every context flush and must be
1301 * rebuilt.
1302 */
1303 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1304 struct radeon_winsys_cs *cs,
1305 struct r600_resource *rbo,
1306 enum radeon_bo_usage usage,
1307 enum radeon_bo_priority priority)
1308 {
1309 assert(usage);
1310 sctx->ws->cs_add_buffer(
1311 cs, rbo->buf,
1312 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1313 rbo->domains, priority);
1314 }
1315
1316 /**
1317 * Same as above, but also checks memory usage and flushes the context
1318 * accordingly.
1319 *
1320 * When this SHOULD NOT be used:
1321 *
1322 * - if si_context_add_resource_size has been called for the buffer
1323 * followed by *_need_cs_space for checking the memory usage
1324 *
1325 * - if si_need_dma_space has been called for the buffer
1326 *
1327 * - when emitting state packets and draw packets (because preceding packets
1328 * can't be re-emitted at that point)
1329 *
1330 * - if shader resource "enabled_mask" is not up-to-date or there is
1331 * a different constraint disallowing a context flush
1332 */
1333 static inline void
1334 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1335 struct r600_resource *rbo,
1336 enum radeon_bo_usage usage,
1337 enum radeon_bo_priority priority,
1338 bool check_mem)
1339 {
1340 if (check_mem &&
1341 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1342 sctx->vram + rbo->vram_usage,
1343 sctx->gtt + rbo->gart_usage))
1344 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1345
1346 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
1347 }
1348
1349 #define PRINT_ERR(fmt, args...) \
1350 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1351
1352 #endif